阅读说明：本技术 一种扫描测试压缩的优化方法 (Optimization method for scan test compression ) 是由 赵毅强 李松 林元琦 甄帅 于 2019-09-03 设计创作，主要内容包括：本发明公开提出一种扫描测试压缩的优化方法,首先采用分析压缩率的的方法来衡量故障覆盖率的损失；在满足覆盖率要求的范围内通过固定扫描通道的方法提升压缩率,适当的减少扫描链的长度和增加扫描链的数量,分析测试向量和测试时间等测试压缩结果；采用固定压缩率的方式增加扫描通道的个数,在并行度不变的条件下增加扫描链的数量同时减少扫描链长度,分析测试向量和测试时间等测试压缩结果；最后综合两方面的来得出最佳的扫描链的长度范围和扫描链的数量。本发明可以给出更为优化的测试压缩方案,降低芯片在测试环节的成本。(The invention discloses and proposes the compressed optimization method of a scanning test, adopt the method of the analytical compression ratio to measure the loss of the fault coverage at first; the compression rate is improved by a method of fixing a scanning channel within the range meeting the requirement of the coverage rate, the length of a scanning chain is properly reduced, the number of the scanning chains is increased, and test compression results such as test vectors, test time and the like are analyzed; increasing the number of scanning channels by adopting a fixed compression rate mode, increasing the number of scanning chains under the condition of unchanged parallelism, simultaneously reducing the length of the scanning chains, and analyzing test compression results such as test vectors, test time and the like; and finally, combining the two aspects to obtain the optimal length range of the scan chains and the number of the scan chains. The invention can provide a more optimized test compression scheme and reduce the cost of the chip in the test link.)

1. A scan test compression optimization method is characterized by comprising the following steps:

firstly, performing compression rate analysis on a scanning test circuit, and entering the step of scanning test compression analysis under the condition of meeting the test coverage rate;

in the step of scan test compression analysis, the following two analysis methods are used:

one is a fixed scanning channel analysis method, which reduces the length of the scanning chain under the condition of unchanged IOs (input/output) of test ports, increases the compression ratio and finds out the length range of the scanning chain meeting the test compression condition;

the other method is a fixed compression ratio analysis method, the number of test ports is increased under the condition that the compression ratio is not changed, the length of a scanning chain is reduced while the number of the scanning chains is increased, and the number of the test ports and the length range of the scanning chains meeting the test compression condition are found out;

and (4) combining the two analysis methods to obtain an optimal test compression scheme.

2. The optimization method of scan test compression according to claim 1, wherein the two analysis methods can be executed in parallel or sequentially according to mutually derived results.

3. The optimization method of scan test compression according to claim 1, wherein the fixed compression ratio analysis method is to increase the number of test channels to analyze the test compression result under the condition that the compression ratio is not changed, so as to achieve the purpose of not changing the test parallelism during the test compression of the chip, and effectively reducing the time of the chip test by using more test ports.

4. The optimization method of scan test compression as claimed in claim 1, wherein the fixed scan channel analysis method is a compression analysis of scan test under the condition of keeping the number of scan channels, and is a test compression analysis performed by increasing the number of scan chains to reduce the test time required for each test vector, so as to reduce the test vector volume and the test time.

Technical Field

The invention relates to the technical field of image sensors, in particular to an optimization method for scan test compression.

Background

The DFT (design for testability) technique is an effective approach to test very large scale integrated circuits, and as the scale of a chip is enlarged, the test data volume and the test time of the chip are increased, and ATE (automatic test equipment) needs to provide more memories and test data transmission channels to meet the test requirements, thereby increasing the test difficulty. The embedded test compression method is to add compression logic in the scanning circuit to realize decompression of test excitation and compression of test response, thereby reducing the number of test data and test channels.

The compression of scan test is mainly divided into decompression of test excitation and compression of test response, and the methods for decompression of test excitation mainly include methods based on coding, such as dictionary coding, Huffman coding, Golomb coding, and the like, decompression mechanisms based on time sequence linear shift feedback registers, and decompression mechanisms based on broadcast scan mechanisms, and the methods for compression of test response mainly include two types, spatial compression and temporal compression.

At present, the mainstream compressor in the industry has DFTMAX of Synopsys and tesenttestkompres of Mentor, respectively, adopts a test excitation decompression scheme based on a time sequence linear shift feedback register and a broadcast scanning mechanism, and test responses adopt a space compression method. For the scan test compression of a chip, the length and the number of scan chains are required to be determined in the design of test compression, and the efficiency of test compression can be increased by adopting proper scan chain configuration, so that the optimal test compression scheme can be obtained by performing scan test compression analysis on a circuit before the scan chain is designed.

Disclosure of Invention

The invention aims to provide an optimization method for scan test compression, aiming at the technical defects in the prior art.

The technical scheme adopted for realizing the purpose of the invention is as follows:

a scan test compression optimization method comprises the following steps:

firstly, performing compression rate analysis on a scanning test circuit, and entering the step of scanning test compression analysis under the condition of meeting the test coverage rate;

in the step of scan test compression analysis, the following two analysis methods are used:

one is a fixed scanning channel analysis method, which reduces the length of the scanning chain under the condition of unchanged IOs (input/output) of test ports, increases the compression ratio and finds out the length range of the scanning chain meeting the test compression condition;

the other method is a fixed compression ratio analysis method, the number of test ports is increased under the condition that the compression ratio is not changed, the length of a scanning chain is reduced while the number of the scanning chains is increased, and the number of the test ports and the length range of the scanning chains meeting the test compression condition are found out;

and (4) combining the two analysis methods to obtain an optimal test compression scheme.

The two analysis methods can be executed in parallel, or can be executed sequentially according to mutually obtained results.

The fixed compression ratio analysis method is characterized in that under the condition that the compression ratio is not changed, the number of test channels is increased to analyze the test compression result, so that the test parallelism degree of the chip during test compression is not changed, and the time for testing the chip can be effectively reduced by using more test ports.

The fixed scanning channel analysis method is to perform compression analysis of scanning test under the condition of keeping the number of scanning channels, and to perform compression analysis of test by increasing the number of scanning chains to reduce the test time required by each test vector, so as to reduce the test vector volume and the test time.

The invention is based on the testing compression structure of the EDT (embedded deterministic test) of the Mentor company and proposes the optimization method of the scanning test compression, adopt the method of the analytical compression ratio to measure the loss of the fault coverage at first; the compression rate is improved by a method of fixing a scanning channel within the range meeting the requirement of the coverage rate, the length of a scanning chain is properly reduced, the number of the scanning chains is increased, and test compression results such as test vectors, test time and the like are analyzed; increasing the number of scanning channels by adopting a fixed compression rate mode, increasing the number of scanning chains under the condition of unchanged parallelism, simultaneously reducing the length of the scanning chains, and analyzing test compression results such as test vectors, test time and the like; and finally, combining the two aspects to obtain the optimal length range of the scan chains and the number of the scan chains.

Since scan test compression must evaluate and select the optimal number of scan channels and the optimal scan chain length, the optimal scan chain configuration implies a minimum pattern count. The optimized design scheme for the scan test compression of the integrated circuit provided by the invention is characterized in that before the design of the test compression circuit, the result of the scan compression is analyzed by using the method, so that the test compression efficiency of the compression circuit is higher, and the fault coverage loss caused by the test compression is minimized, thereby greatly reducing the test time and test cost required by the test of the integrated circuit while ensuring the coverage, reducing the internal memory required by ATE (automatic test equipment), improving the test efficiency and yield of the chip and reducing the risk caused by the escape of the test chip.

Drawings

FIG. 1 is a flow chart of a method for optimizing scan test compression in accordance with the present invention;

FIG. 2 is a flow chart of a fixed scan channel compression analysis.

FIG. 3 is a flow chart of a fixed compression ratio analysis method.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The scan test of the chip is divided into three processes of test initialization, shift and capture, each test vector can complete respective shift and capture, wherein the shift occupies most of the time of the scan test, therefore, under the condition of only considering the scan shift data and period, the volume V of the scan test data_testAnd a test time T_testCan be calculated by the following formula:

V_test＝IOs*Patterns*Cycles (1)

in the formula: IOs is the number of scan test ports, Patterns is the number of test vectors, Cycles is the number of shift Cycles of a test vector, F_shiftFor testing the clock frequency, the value of Cycles depends on the number of shift Cycles of the longest scan chain, and as can be seen from equations (1) and (2), the test vector volume can be reduced from the three aspects of the number of scan test ports, the number of test vectors and the length of scan chains, and under the condition that the test ports are fixed, the test time is positively correlated with the test volume.

Accordingly, the test compression analysis method provided by the invention mainly comprises the following processes:

(1) performing compression rate analysis on the scanning test circuit, and performing scanning test compression analysis under the condition of meeting the test coverage rate;

(2) the fixed scanning channel analysis method reduces the length of the scanning chain under the condition of keeping the number of the test ports IOs unchanged, increases the compression ratio and finds out the length range of the scanning chain meeting the test compression condition;

(3) and the fixed compression ratio analysis method is used for increasing the number of the test ports under the condition that the compression ratio is not changed, increasing the number of the scan chains and simultaneously reducing the length of the scan chains, and finding out the number of the test ports and the length range of the scan chains which meet the test compression condition.

Wherein, the steps (2) and (3) can be executed in parallel, and can also be executed in sequence according to the mutually obtained results, and the optimal test compression scheme is obtained by integrating the two analysis methods.

In the invention, the compression ratio analysis is to ensure that the used test compression scheme is tested and compressed under the condition of meeting the fault coverage rate, the fault coverage rate is reduced along with the increase of the compression ratio due to the limitation of the ATPG capability, and the compression ratio of the scan test is increased by the reduction of the length of the scan chain or the increase of the number of the scan chains. Therefore, the range of the maximum compression rate satisfying the fault coverage is determined by means of the compression rate analysis before the scan test compression analysis.

In the method for fixing the scanning channels, the compression analysis of the scanning test is carried out under the condition of keeping the number of the scanning channels, and the compression analysis of the scanning test is carried out by reducing the test time required by each test vector by increasing the number of the scanning chains. Since scan shift takes a significant portion of the time during testing, the effect is very significant in this way to reduce test vector volume and test time.

The analysis method of the fixed scanning channel can take the following factors into consideration:

(1) fault coverage rate: the fixed scanning channel analysis method can be used for analyzing the loss of fault coverage rate caused by the improvement of the compression rate and ensuring the correctness of test compression;

(2) number of test vectors: shortening the scan chain length reduces the shift time of each test vector, but because the number of scan chains is increased, more test vectors are needed, and the test time is increased due to the excessively high compression rate;

(3) extra shift cycles: the initialization of the EDT module needs to occupy a certain number of shift cycles, when the length of a scan chain is reduced to a certain degree, an additional shift cycle occupies a certain effective test time, and the test time is increased along with the increase of the number of test vectors;

(4) simulation time of ATPG: the increase of the number of the test vectors means that the ATPG tool needs to spend more time, and in chip design, the reduction of the ATPG time can shorten the design period of the chip and improve the working efficiency.

Combining the above aspects, an optimal scan chain length range under a certain scan channel number can be given. The fixed scan channel compresses the analysis process. As shown in fig. 2.

The fixed compression ratio analysis method is used for analyzing the test compression result by increasing the number of test channels under the condition that the compression ratio is not changed. The method is adopted to ensure that the test parallelism during the test compression of the chip is not changed, and the time for testing the chip can be effectively reduced by using more test ports.

The following three aspects can be considered in the fixed compression ratio analysis:

(1) in the method, the proportion of the extra shift period of the EDT is increased due to the reduction of the length of a scanning chain, and the effect of reducing the test time by increasing a test channel is not obvious;

(2) the volume of the test vector is increased, the parallelism of the chip test is not changed by the method of fixing the compression ratio, the quantity of the test vector required by the test is not changed too much, the volume of the test vector is increased due to the need of more test ports, and more test memory space needs to be provided by the ATE;

(3) the method can consider the influence of compression of different test pin number countermeasures of the chip to obtain the optimal test port number.

By combining the aspects, the optimal scan chain length range under the condition of certain compression rate can be given. The compression analysis process is shown in figure 3.

Table 1 below gives several major factors that influence test compression considered in the two scan test compression analysis methods, which are somewhat mutually restrictive with respect to test compression results and require balancing considerations in test compression design. During fixed scan channel analysis, an analysis mode of increasing the compression ratio C.R. is adopted, and during fixed compression ratio analysis, an analysis mode of increasing the test port IOs is adopted.

TABLE 1

The scan test compression optimization method provided by the invention considers the requirement of a test result at the beginning of scan chain design, can carry out pre-estimated test compression consideration on a chip through three processes of compression rate, fixed scan channel and fixed compression rate, balances the limiting factors among various test conditions, and provides the optimal scan chain design scheme under different test conditions.

The compression ratio analysis method can evaluate the loss of the chip test compression fault coverage rate, reduce the loss of the fault coverage rate caused by compression, can obtain the scan chain configuration range with the least test vector volume and test time by adopting the analysis method of the fixed scan channel, and can shorten the length of the scan chain to the greatest extent to reduce the test time by adopting the method of the fixed compression ratio under the condition of keeping the test compression parallelism degree, so the design of optimizing the scan test compression by combining the methods can be combined, a more optimized test compression scheme can be provided by combining the design specification of the chip, and the cost of the chip in the test link is reduced.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.