阅读说明：本技术 一种面向高速消息传输的pcie数据传输系统及计算机 (PCIE data transmission system and computer for high-speed message transmission ) 是由 牟华先 周舟 曹志强 任秀江 崔晓阳 周建毅 于 2019-09-12 设计创作，主要内容包括：本发明涉及计算机外围设备高速互联总线(PCIE)技术领域,尤其涉及一种面向高速消息传输的PCIE数据传输系统及计算机。包括采用非轮询方式进行交互的处理器和消息处理芯片；所述处理器和消息处理芯片之间的数据包包括P数据包、NP数据包、CPL数据包,并且所述处理器和所述消息处理芯片均采用专门的通道发送和接收CPL数据包。可以满足PCIE的防死锁约束,并且在工程上容易实现,能够提升PCIE整体性能。(The invention relates to the technical field of peripheral equipment high-speed interconnection buses (PCIE) of computers, in particular to a PCIE data transmission system and a computer for high-speed message transmission. The system comprises a processor and a message processing chip which are interacted in a non-polling mode; the data packets between the processor and the message processing chip comprise a P data packet, an NP data packet and a CPL data packet, and the processor and the message processing chip both adopt a special channel to send and receive the CPL data packet. The deadlock prevention constraint of the PCIE can be met, the implementation is easy in engineering, and the overall performance of the PCIE can be improved.)

1. A PCIE data transmission system facing high-speed message transmission is characterized in that:

the system comprises a processor and a message processing chip which are interacted in a non-polling mode;

the data packets between the processor and the message processing chip comprise a P data packet, an NP data packet and a CPL data packet, and the processor and the message processing chip both adopt a special channel to send and receive the CPL data packet.

2. The PCIE data transmission system oriented to high speed message transmission according to claim 1, wherein:

the message processing chip comprises a first EP transmitting channel for transmitting a P data packet, a second EP transmitting channel for transmitting an NP data packet and a third EP transmitting channel for transmitting a CPL data packet;

the processor comprises a first RC receiving channel for receiving a P data packet and an NP data packet, and a second RC receiving channel for receiving a CPL data packet;

the message processing chip is provided with a blocking module, and the blocking module is used for preventing an NP data packet sent by the message processing chip from passing through a P data packet sent by the message processing chip.

3. The PCIE data transmission system oriented to high speed message transmission according to claim 2, wherein:

the blocking module comprises NP counters which are arranged corresponding to the NP data packets in the second EP sending channel;

the counting value of the NP counter is initialized to the number of P data packets in the first EP transmitting channel before the corresponding NP data packet enters the second EP transmitting channel when each NP data packet enters the second EP transmitting channel;

when the first EP sending channel sends out a P data packet, the count value of each NP counter in the blocking module is reduced by 1;

and the blocking module judges the count value of an NP counter corresponding to the NP data packet in the blocking module when the NP data packet in the second EP transmitting channel is ready to be transmitted, if the count value is not greater than 0, the NP data packet is allowed to be transmitted, otherwise, the NP data packet is blocked.

4. The PCIE data transmission system oriented to high speed message transmission according to claim 1, wherein:

the processor comprises a first RC sending channel for sending a P data packet and an NP data packet and a second RC sending channel for sending a CPL data packet;

the message processing chip comprises a first EP receiving channel for receiving P data packets and NP data packets and a second EP receiving channel for receiving CPL data packets.

5. The PCIE data transmission system oriented to high speed message transmission according to claim 1, wherein:

the data packet between the processor and the message processing chip also comprises an RO P data packet and an RO NP data packet.

6. The PCIE data transmission system oriented to high speed message transmission of claim 5, wherein:

the processor comprises a first RC sending channel for sending a P data packet, an NP data packet and an RO P data packet, a second RC sending channel for sending a CPL data packet and a third RC sending channel for sending an RO NP data packet;

the message processing chip comprises a first EP receiving channel for receiving a P data packet and an NP data packet, a second EP receiving channel for receiving a CPL data packet, and a third EP receiving channel for receiving an RO P data packet and an RO NP data packet;

the message processing chip is provided with a blocking module, and the blocking module is used for preventing the P data packet received by the message processing chip from passing through the RO P data packet received by the message processing chip.

7. The PCIE data transmission system oriented to high speed message transmission of claim 6, wherein:

the blocking module comprises a P counter which is arranged corresponding to each P data packet in the first EP receiving channel; the count value of the P counter is initialized to the number of RO P packets in the third EP reception lane before the corresponding P packet enters the first EP reception lane when each P packet enters the first EP reception lane;

when the third EP receiving channel sends out one RO P packet, the count value of each counter in the blocking module is decremented by 1;

the blocking module judges the count value of a P counter corresponding to a P data packet in the blocking module when the P data packet in the first EP receiving channel is ready to be sent out, if the count value is not greater than 0, the P data packet is allowed to be sent out, otherwise, the P data packet is blocked.

8. The PCIE data transmission system oriented to high speed message transmission of claim 5, wherein:

the processor comprises a first RC receiving channel for receiving a P data packet and an NP data packet, and a second RC receiving channel for receiving a CPL data packet;

the message processing chip comprises a first EP transmitting channel for transmitting a P data packet, a second EP transmitting channel for transmitting an NP data packet and a third EP transmitting channel for transmitting a CPL data packet;

the message processing chip is provided with a blocking module, and the blocking module is used for preventing an NP data packet sent by the message processing chip from passing through a P data packet sent by the message processing chip.

9. The PCIE data transmission system oriented to high speed message transmission according to claim 8, wherein:

the blocking module comprises NP counters which are arranged corresponding to the NP data packets in the second EP sending channel;

the counting value of the NP counter is initialized to the number of P data packets in the first EP transmitting channel before the corresponding NP data packet enters the second EP transmitting channel when each NP data packet enters the second EP transmitting channel;

when the first EP sending channel sends out a P data packet, the count value of each NP counter in the blocking module is reduced by 1;

and the blocking module judges the count value of an NP counter corresponding to the NP data packet in the blocking module when the NP data packet in the second EP transmitting channel is ready to be transmitted, if the count value is not greater than 0, the NP data packet is allowed to be transmitted, otherwise, the NP data packet is blocked.

10. A computer, characterized by:

a PCIE data transmission system comprising any one of the claims 1 to 9.

Technical Field

The invention relates to the technical field of peripheral equipment high-speed interconnection buses (PCIE) of computers, in particular to a PCIE data transmission system and a computer for high-speed message transmission.

Background

The invention patent application with application publication number CN 109684269 a and application publication date 2019, 4, month and 26 discloses a PCIE switch chip core and a working method, which can forward PCIE transaction layer packets according to the ordering rule specified by the PCIE standard protocol so as to follow the models of producers and consumers.

The message processing chip is a core chip for realizing a high-speed message transmission mechanism, and the PCIE interface is the only access interface of the message processing chip and plays a vital role in the performance of message transmission. The forwarding sequence of the PCIE transaction layer packet is an important basis for implementing the PCIE interface. For high speed messaging, some of the rules of standard PCIE ordering do not apply completely.

Disclosure of Invention

The invention aims to provide a PCIE data transmission system and a computer aiming at high-speed message transmission application in a high-performance computer, which are used for improving the computing performance of the computer.

A PCIE data transmission system facing high-speed message transmission is characterized in that:

the system comprises a processor and a message processing chip which are interacted in a non-polling mode;

the data packets between the processor and the message processing chip comprise a P data packet, an NP data packet and a CPL data packet, and the processor and the message processing chip both adopt a special channel to send and receive the CPL data packet.

The producer-consumer scenario specified by the PCIE standard order is not all an essential component in high-speed message transmission, and the implementation of the performance-increasing order is also complicated in engineering. In the technical scheme, the processor and the message processing chip are interacted in a non-polling mode, so that the processor and the message processing chip can process the CPL data packet by adopting a special channel, deadlock prevention constraint of PCIE can be met, the implementation is easy in engineering, and the overall performance of the PCIE can be improved.

Preferably, the message processing chip comprises a first EP transmission channel for transmitting P data packets, a second EP transmission channel for transmitting NP data packets, and a third EP transmission channel for transmitting CPL data packets; the processor comprises a first RC receiving channel for receiving a P data packet and an NP data packet, and a second RC receiving channel for receiving a CPL data packet; the message processing chip is provided with a blocking module, and the blocking module is used for preventing an NP data packet sent by the message processing chip from passing through a P data packet sent by the message processing chip. And in the direction that the consumer sends the data to the producer, the anti-deadlock constraint of the PCIE sequence and the constraint of the producer consumer model are met.

Further, the blocking module includes an NP counter corresponding to each NP packet in the second EP transmission channel; the counting value of the NP counter is initialized to the number of P data packets in the first EP transmitting channel before the corresponding NP data packet enters the second EP transmitting channel when each NP data packet enters the second EP transmitting channel; when the first EP sending channel sends out a P data packet, the count value of each NP counter in the blocking module is reduced by 1; and the blocking module judges the count value of an NP counter corresponding to the NP data packet in the blocking module when the NP data packet in the second EP transmitting channel is ready to be transmitted, if the count value is not greater than 0, the NP data packet is allowed to be transmitted, otherwise, the NP data packet is blocked.

Further, the processor comprises a first RC transmission channel for transmitting the P data packet and the NP data packet, and a second RC transmission channel for transmitting the CPL data packet; the message processing chip comprises a first EP receiving channel for receiving P data packets and NP data packets and a second EP receiving channel for receiving CPL data packets. And in the direction of sending the producer to the consumer, the anti-deadlock constraint and the producer consumer model constraint of the PCIE sequence are met.

Preferably, the data packet between the processor and the message processing chip further includes an RO P data packet and an RO NP data packet. The specific Order requirement of a high-speed message mechanism is combined, a PCIE transaction layer data packet with an RO (reverse Order) mark is introduced, and the data packet of the type can violate PCIE standard Order rules so as to improve the performance of the computer.

Preferably, the processor comprises a first RC transmission channel for transmitting P data packets, NP data packets and RO P data packets, a second RC transmission channel for transmitting CPL data packets and a third RC transmission channel for transmitting RO NP data packets; the message processing chip comprises a first EP receiving channel for receiving a P data packet and an NP data packet, a second EP receiving channel for receiving a CPL data packet, and a third EP receiving channel for receiving an RO P data packet and an RO NP data packet; the message processing chip is provided with a blocking module, and the blocking module is used for preventing the P data packet received by the message processing chip from passing through the RO P data packet received by the message processing chip.

Further, the blocking module includes a P counter corresponding to each P packet in the first EP receiving channel; the count value of the P counter is initialized to the number of RO P packets in the third EP reception lane before the corresponding P packet enters the first EP reception lane when each P packet enters the first EP reception lane; when the third EP receiving channel sends out one RO P packet, the count value of each counter in the blocking module is decremented by 1; the blocking module judges the count value of a P counter corresponding to a P data packet in the blocking module when the P data packet in the first EP receiving channel is ready to be sent out, if the count value is not greater than 0, the P data packet is allowed to be sent out, otherwise, the P data packet is blocked.

Preferably, the processor comprises a first RC receiving channel for receiving P data packets and NP data packets, and a second RC receiving channel for receiving CPL data packets; the message processing chip comprises a first EP transmitting channel for transmitting a P data packet, a second EP transmitting channel for transmitting an NP data packet and a third EP transmitting channel for transmitting a CPL data packet; the message processing chip is provided with a blocking module, and the blocking module is used for preventing an NP data packet sent by the message processing chip from passing through a P data packet sent by the message processing chip.

Further, the blocking module includes an NP counter corresponding to each NP packet in the second EP transmission channel; the counting value of the NP counter is initialized to the number of P data packets in the first EP transmitting channel before the corresponding NP data packet enters the second EP transmitting channel when each NP data packet enters the second EP transmitting channel; when the first EP sending channel sends out a P data packet, the count value of each NP counter in the blocking module is reduced by 1; and the blocking module judges the count value of an NP counter corresponding to the NP data packet in the blocking module when the NP data packet in the second EP transmitting channel is ready to be transmitted, if the count value is not greater than 0, the NP data packet is allowed to be transmitted, otherwise, the NP data packet is blocked.

The invention also provides a computer, which is characterized in that: the PCIE data transmission system comprises any one of the PCIE data transmission systems.

The invention has the following beneficial effects:

aiming at the application scene of high-speed message transmission, the processor and the message processing chip are interacted by adopting interruption, so that the interaction efficiency is higher. The CPL data packet is processed by adopting a special channel, so that the deadlock prevention constraint of the PCIE can be met, the implementation on engineering is easy, and the overall performance of the PCIE can be improved.

Detailed Description

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that the conventional terms should be interpreted as having a meaning that is consistent with their meaning in the relevant art and this disclosure. The present disclosure is to be considered as an example of the invention and is not intended to limit the invention to the particular embodiments.