阅读说明：本技术 内存配置结构 (Memory configuration structure ) 是由 林正隆 梁万栋 于 2018-07-05 设计创作，主要内容包括：一种内存配置结构,包含多数基板；多数分别连通设于各基板中央处的穿孔区；多数分别连通设于各基板且位于各穿孔区一侧的第一接点区,各第一接点区用以与一内存的各接脚垫用讯号线连接；以及多数分别连通设于各基板且位于各穿孔区另一侧的第二接点区,各第二接点区用以与该内存的各接脚垫用讯号线连接,且至少包含内存的PAR接脚,并使一基板以其第一或第二接点区通过穿孔区与另一基板的第一或第二接点区相互电连接,使内存各接脚与第一及第二接点区电连接后,让各基板以其第一或第二接点区相对应的讯号线透过穿孔区的导引进行跨层电连接,使内存制作时,可有效避免参考层破碎情形,且具有较佳电源分布以及足够线路布局空间,进而维持较佳讯号完整性。(A memory configuration structure comprises a plurality of substrates; a plurality of perforated areas respectively communicated with the centers of the substrates; a plurality of first contact areas which are respectively communicated with each substrate and are positioned at one side of each perforation area, and each first contact area is used for being connected with each contact pad of an internal memory by a signal wire; and a plurality of second contact areas which are respectively communicated with each substrate and are positioned at the other side of each perforation area, each second contact area is used for being connected with each pin pad of the memory by a signal wire and at least comprises PAR pins of the memory, and a substrate is electrically connected with a first or second contact area of another substrate by the first or second contact area through the perforation area, after each pin of the memory is electrically connected with the first and second contact areas, each substrate is electrically connected with each other in a cross-layer way by the signal wire corresponding to the first or second contact area through the guidance of the perforation area, so that the situation of breaking a reference layer can be effectively avoided when the memory is manufactured, and the memory has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.)

1. A memory allocation structure, comprising:

a plurality of substrates;

a plurality of perforated areas which are respectively communicated with the center of each substrate;

a plurality of first contact areas which are respectively communicated with each substrate and are positioned at one side of each perforation area, and each first contact area is used for being connected with each contact pad of an internal memory by a signal wire; and

and the plurality of second contact areas are respectively communicated with the substrates and positioned at the other side of the perforation areas, each second contact area is used for being connected with each pin pad of the memory by a signal wire and at least comprises a PAR pin of the memory, and the first contact area or the second contact area of one substrate is mutually and electrically connected with the first contact area or the second contact area of the other substrate through the perforation areas.

2. The memory allocation structure of claim 1, wherein each of the plurality of perforation blocks comprises a first row of perforations, a second row of perforations disposed on a side of the first row of perforations, and a third row of perforations disposed on a side of the second row of perforations.

3. The memory allocation structure of claim 2, wherein each of the first rows of vias has at least eight vias, each of the second rows of vias has at least nine vias, and each of the third rows of vias has at least eight vias.

4. The memory allocation structure of claim 3, wherein each of the first row of vias, each of the second row of vias, and each of the third row of vias has a partition therebetween.

5. The memory allocation structure of claim 3, wherein the outer edge of each through hole has an insulation portion, and each through hole has a power connection portion therebetween.

6. The memory allocation structure of claim 1, wherein each of the first contact areas comprises a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, and each of the first row of contacts, each of the second row of contacts, and each of the third row of contacts has at least nine contacts.

7. The memory allocation structure of claim 1, wherein each of the second contact areas comprises a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, and each of the first row of contacts, each of the second row of contacts, and each of the third row of contacts has at least nine contacts.

8. The memory allocation structure of claim 1, wherein each of the first contact regions and each of the second contact regions are electrically connected to one contact region or the second contact region of another substrate through the through hole region via two surfaces of one of the substrates by signal lines, respectively.

9. The memory allocation structure of claim 8, wherein each signal line is the same length.

Technical Field

The present invention relates to a memory configuration structure, and more particularly, to a memory configuration structure capable of effectively preventing a reference layer from being broken during a memory manufacturing process, and having a better power distribution and a sufficient layout space, thereby maintaining a better signal integrity.

Background

Generally, in the conventional memory, each pin is electrically connected to each contact according to the configuration requirement, and each contact is electrically connected to each other by a signal line; so as to complete the setup of the memory.

However, in the conventional wiring method of the memory, through holes are formed at each position on the substrate, and each pin and each contact of the memory are directly and electrically connected with each other through the through holes by signal lines, so that the circuit layout space is more narrow, the power distribution is poor, the reference layer is broken during wiring, and the reference layer of the memory cannot have signal integrity.

Therefore, in order to overcome the above disadvantages, the inventors of the present invention have made intensive studies to develop a memory allocation structure to effectively overcome the disadvantages of the conventional memory.

Disclosure of Invention

The main objective of the present invention is to provide a memory layout structure, which can effectively avoid the situation of breaking the reference layer during the manufacturing of the memory, and has better power distribution and sufficient circuit layout space, so as to maintain better signal integrity.

To achieve the above object, the present invention is a memory allocation structure, which comprises: a plurality of substrates; a plurality of perforated areas respectively communicated with the centers of the substrates; a plurality of first contact areas which are respectively communicated with each substrate and are positioned at one side of each perforation area, and each first contact area is used for being connected with each contact pad of an internal memory by a signal wire; and a plurality of second contact areas which are respectively communicated with each substrate and are positioned at the other side of each perforation area, wherein each second contact area is used for being connected with each pin pad of the memory by a signal wire and at least comprises a PAR pin of the memory, and the first contact area or the second contact area of one substrate is mutually and electrically connected with the first contact area or the second contact area of the other substrate through the perforation area.

In an embodiment of the invention, each of the perforation areas includes a first row of perforations, a second row of perforations disposed at one side of the first row of perforations, and a third row of perforations disposed at one side of the second row of perforations.

In an embodiment of the present invention, each of the first rows of through holes has at least eight through holes, each of the second rows of through holes has at least nine through holes, and each of the third rows of through holes has at least eight through holes.

In an embodiment of the invention, a partition is respectively disposed between each first row of through holes, each second row of through holes and each third row of through holes.

In an embodiment of the invention, the outer edge of each through hole has an insulating portion, and a power connection portion is disposed between each through hole.

In an embodiment of the invention, each first contact area includes a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, and each first row of contacts, each second row of contacts, and each third row of contacts have at least nine contacts.

In an embodiment of the invention, each second contact area includes a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, and each first row of contacts, each second row of contacts, and each third row of contacts have at least nine contacts.

In an embodiment of the invention, each of the first contact areas and each of the second contact areas are electrically connected to one of the contact areas or the second contact areas of the other substrate through the through hole area via the signal line through the two surfaces of one of the substrates.

In an embodiment of the present invention, each signal line has the same length.

The invention makes each pin of the memory electrically connected with the first contact area and the second contact area, and makes each substrate perform cross-layer mutual electrical connection by the signal line corresponding to the first contact area or the second contact area through the guidance of the perforation area, so that the memory can effectively avoid the situation of breaking the reference layer during manufacturing, and has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.

Drawings

FIG. 1 is a basic schematic diagram of the present invention.

FIG. 2 is a schematic diagram illustrating the usage of the present invention.

Component reference number comparison:

a substrate 1;

a perforated zone 2;

a first row of perforations 21;

perforations 211, 221, 231;

the insulating portions 212, 222, 232;

a second row of perforations 22;

a third row of perforations 23;

a partition 24;

a power supply connection part 25;

a first contact area 3;

a first discharge point 31;

contacts 311, 321, and 331;

a second row of contacts 32;

a third row of contacts 33;

a second contact region 4;

a first row of contacts 41;

contacts 411, 421, 431;

a second row of contacts 42;

a third row of contacts 43;

a signal line 5.

Detailed Description

Please refer to fig. 1 and fig. 2, which are a basic schematic diagram and a usage status schematic diagram of the present invention, respectively. As shown in the figure: the present invention relates to a memory layout structure, which at least comprises a plurality of substrates 1, a plurality of via areas 2, a plurality of first contact areas 3 and a plurality of second contact areas 4.

Each substrate 1 is a circuit board, and each substrate 1 is provided in a vertically corresponding or stacked manner.

The respective perforated sections 2 are respectively communicated with the center of the respective substrates 1.

Each first contact area 3 is respectively communicated with each substrate 1 and located at one side of each perforation area 2, and each first contact area 3 is used for being connected with each contact pad of an internal memory by a signal line (not shown).

Each second contact area 4 is respectively communicated with each substrate 1 and is positioned at the other side of each perforation area 2, each second contact area 4 is used for being connected with each pin pad of the memory by a signal line and at least comprises a PAR pin (not shown) of the memory, and the first contact area 3 or the second contact area 4 of one substrate is mutually and electrically connected with the first contact area 3 or the second contact area 4 of the other substrate 1 through the perforation area 2.

After each pin of the memory is electrically connected with the first contact area 3 and the second contact area 4 of one of the substrates 1, the signal line 5 corresponding to the first contact area 3 and the second contact area 4 can be electrically connected with a required contact area 3 or the second contact area 4 of the other substrate 1 (not shown) in a cross-layer manner through the guidance of the through hole area 2, so that the memory can effectively avoid the situation that a reference layer is broken during manufacturing, and has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.

In an embodiment of the present invention, each of the perforation areas 2 includes a first row of perforations 21, a second row of perforations 22 disposed at one side of the first row of perforations 21, and a third row of perforations 23 disposed at one side of the second row of perforations 22, each of the first row of perforations 21 has at least eight perforations 211, each of the second row of perforations 22 has at least nine perforations 221, each of the third row of perforations 23 has at least eight perforations 231, a partition 24 is disposed between each of the first row of perforations 21, each of the second row of perforations 22, and each of the third row of perforations 23, an insulating portion 212, 222, 232 is disposed at an outer edge of each of the perforations, and a power connection portion 25 is disposed between each of the perforations 211, 221, 231.

In an embodiment of the present invention, each first contact area 3 includes a first row of contacts 31, a second row of contacts 32 disposed on one side of the first row of contacts 31, and a third row of contacts 33 disposed on one side of the second row of contacts 32, and each first row of contacts 31, each second row of contacts 32, and each third row of contacts 33 has at least nine contacts 311, 321, and 331, respectively.

In an embodiment of the present invention, each second contact area 4 includes a first row of contacts 41, a second row of contacts 42 disposed on one side of the first row of contacts 41, and a third row of contacts 43 disposed on one side of the second row of contacts 42, and each first row of contacts 41, each second row of contacts 42, and each third row of contacts 43 has at least nine contacts 411, 421, 431, respectively.

When the memory is electrically connected to the first contact area 3 and the second contact area 4 of one of the substrates 1, the following is exemplified:

when the memory is connected, at least the VDD pin of the memory is connected to the first contact 311 of the first row of contacts 31 arranged in the first contact area 3; the a13 pin of the memory is connected to the first contact 321 of the second row of contacts 32 disposed in the first contact area 3; the pin a17 of the memory is connected to the first contact 331 of the third row of contacts 33 disposed in the first contact area 3; the PAR pin of the memory is connected to the first contact 411 of the first row of contacts 41 disposed in the second contact area 4; the a11 pin of the memory is connected to the first contact 421 of the second row of contacts 42 disposed in the second contact area 4; the VSS pin of the memory is connected to the first contact 431 of the third row of contacts 43 provided in the second contact area 4.

Since the through hole 2 is disposed between the first contact area 3 and the second contact area 4, when the first contact area 3 and the second contact area 4 of the substrate 1 are electrically connected to another substrate 1 (not shown), each signal line 5 can be routed and guided through the through holes 211, 221, 231 of the first row of through holes 21, the second row of through holes 22 and the third row of through holes 23 disposed on the through hole 2 through the two surfaces of the substrate 1, so that each contact 311, 321, 331 of the first contact area 3 and each contact 411, 421, 431 of the second contact area 4 can pass through each through hole 211, 221, 231 as required, each signal line 5 can be electrically connected with the first contact area 3 and the second contact area 4 of another substrate 1 in a cross-layer manner, and each power supply line or ground line can be connected with each power connection portion 25 as required, in this embodiment, the signal lines 5 have the same length, so that the routing of the signal lines 5 is clean and free from the breakage of the reference layer, and the signal lines 5 have the same length, thereby having better power distribution and enough circuit layout space.

The first row of through holes 21, the second row of through holes 22 and the third row of through holes 23 are separated by the separating portions 24 to prevent the signal lines 5 from interfering with each other, and when the signal lines 5 are inserted into the through holes 211, 221 and 231, the insulating portions 212, 222 and 232 prevent the signal lines 5 from contacting the power connection portions 25 to cause short circuit.

In summary, the memory configuration structure of the present invention can make each pin of the memory electrically connected to the first contact area and the second contact area, and then make each substrate electrically connected to each other through the signal line corresponding to the first contact area or the second contact area by crossing layers by guiding of the via area, so that the memory can effectively avoid the situation of breaking the reference layer during the manufacturing process, and has better power distribution and sufficient circuit layout space, thereby maintaining better signal integrity; further, the present invention is more advanced, practical, and suitable for the use of consumers, and the invention is consistent with the subject matter of the present invention patent application.

However, the above description is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention; therefore, all the equivalent changes and modifications made by the claims and the content of the specification of the invention should be covered by the scope of the patent of the invention.