阅读说明：本技术 数据采集装置 (Data acquisition device ) 是由 朱波 刘龙 曾重阳 武昊 刘鲁鹏 于 2021-06-29 设计创作，主要内容包括：本发明提供一种数据采集装置,其中装置包括：FPGA单元,包括MicroBlaze软核和AXI CAN IP核,用于获取CAN总线数据；所述AXI CAN IP核的数量是基于所述CAN总线数据的通道数量确定的；处理器单元,与所述FPGA单元连接,用于对所述CAN总线数据进行处理,确定所述CAN总线数据的处理结果。本发明提供的数据采集装置,采用软件结构代替硬件控制器,能够适应大量数据的接入需求,同时由于不增加硬件控制器,节约了硬件电路的布局空间,减少了硬件电路的潜在故障点。(The invention provides a data acquisition device, wherein the device comprises: the FPGA unit comprises a MicroBlaze soft core and an AXI CAN IP core and is used for acquiring CAN bus data; the number of AXI CAN IP cores is determined based on a number of channels of the CAN bus data; and the processor unit is connected with the FPGA unit and used for processing the CAN bus data and determining the processing result of the CAN bus data. The data acquisition device provided by the invention adopts a software structure to replace a hardware controller, can meet the access requirement of a large amount of data, and simultaneously saves the layout space of a hardware circuit and reduces the potential fault points of the hardware circuit because the hardware controller is not added.)

1. A data acquisition device, comprising:

the FPGA unit comprises a MicroBlaze soft core and an AXI CAN IP core and is used for acquiring CAN bus data; the number of AXI CAN IP cores is determined based on a number of channels of the CAN bus data;

and the processor unit is connected with the FPGA unit and used for processing the CAN bus data and determining the processing result of the CAN bus data.

2. The data acquisition device as recited in claim 1 wherein said AXI CAN IP core and said MicroBlaze soft core are connected by an AXI bus.

3. The data acquisition device as recited in claim 1 wherein the number upper limit value for the AXI CAN IP cores is determined based on an AXI bus.

4. The data acquisition device of claim 1, wherein the FPGA unit further comprises:

the double-port RAM is connected with the MicroBlaze soft core and is used for storing the CAN bus data;

and one end of the communication IP core is connected with the double-port RAM, and the other end of the communication IP core is connected with the processor unit and used for controlling the CAN bus data transmission.

5. The data acquisition device of claim 1, wherein the FPGA unit further comprises:

and the clock module is connected with the MicroBlaze soft core and used for carrying out frequency multiplication and frequency division on the input clock of the FPGA unit and determining the working clock of the MicroBlaze soft core.

6. The data acquisition device of claim 1, wherein the FPGA unit further comprises:

and the debugging module is connected with the MicroBlaze soft core and is used for debugging the running program in the MicroBlaze soft core.

7. The data acquisition device of claim 1, wherein the FPGA unit and the processor unit are connected by a GPMC bus.

8. The data acquisition device according to any one of claims 1 to 7, wherein the processing result of the CAN bus data is in a Linux file system format.

9. The data acquisition device of any one of claims 1 to 7, further comprising:

and the storage unit is connected with the processor unit and used for storing the processing result of the CAN bus data.

10. The data acquisition device of any one of claims 1 to 7, further comprising:

and the interface unit is connected with the processor unit and used for transmitting the processing result of the CAN bus data.

Technical Field

The invention relates to the technical field of rail transit, in particular to a data acquisition device.

Background

In a rail transit system, a rail and a surrounding environment need to be detected in real time, so a large number of detection devices need to be deployed, and the detection devices generally adopt a CAN communication interface mode and are connected to each monitoring device of a monitoring center through a dedicated line. This way greatly wastes line resources and is not easy to manage the equipment uniformly.

In the prior art, in order to collect data through a CAN bus more conveniently, a plurality of CAN bus input interfaces are generally obtained in a hardware expansion mode. For example, the CAN bus input interface is extended by adding multiple MCP2515 controllers in the hardware circuitry. The method has the defects that the input interface obtained by a hardware expansion mode is extremely limited and fixed, and cannot adapt to the access requirement of a large amount of data; in addition, the space of the hardware circuit layout is tense due to the addition of the controller, and potential fault points are increased.

Disclosure of Invention

The invention provides a data acquisition device, which is used for solving the technical problems that the existing data acquisition device cannot adapt to the access requirement of a large amount of data and has more potential fault points.

The present invention provides a data acquisition apparatus comprising:

the FPGA unit comprises a MicroBlaze soft core and an AXI CAN IP core and is used for acquiring CAN bus data; the number of AXI CAN IP cores is determined based on a number of channels of the CAN bus data;

and the processor unit is connected with the FPGA unit and used for processing the CAN bus data and determining the processing result of the CAN bus data.

According to the data acquisition device provided by the invention, the AXI CAN IP core is connected with the MicroBlaze soft core through an AXI bus.

According to the data acquisition apparatus provided by the present invention, the upper limit value of the number of AXI CAN IP cores is determined based on an AXI bus.

According to the data acquisition device provided by the invention, the FPGA unit further comprises:

the double-port RAM is connected with the MicroBlaze soft core and is used for storing the CAN bus data;

and one end of the communication IP core is connected with the double-port RAM, and the other end of the communication IP core is connected with the processor unit and used for controlling the CAN bus data transmission.

According to the data acquisition device provided by the invention, the FPGA unit further comprises:

and the clock module is connected with the MicroBlaze soft core and used for carrying out frequency multiplication and frequency division on the input clock of the FPGA unit and determining the working clock of the MicroBlaze soft core.

According to the data acquisition device provided by the invention, the FPGA unit further comprises:

and the debugging module is connected with the MicroBlaze soft core and is used for debugging the running program in the MicroBlaze soft core.

According to the data acquisition device provided by the invention, the FPGA unit is connected with the processor unit through a GPMC bus.

According to the data acquisition device provided by the invention, the processing result of the CAN bus data is in a Linux file system format.

According to the data acquisition device provided by the invention, the data acquisition device further comprises:

and the storage unit is connected with the processor unit and used for storing the processing result of the CAN bus data.

According to the data acquisition device provided by the invention, the data acquisition device further comprises:

and the interface unit is connected with the processor unit and used for transmitting the processing result of the CAN bus data.

The data acquisition device comprises an FPGA unit and a processor unit which are connected with each other, wherein the FPGA unit comprises a MicroBlaze soft core and an AXI CAN IP core and is used for acquiring CAN bus data, the processor unit determines the processing result of the CAN bus data, the number of the AXI CAN IP cores is determined based on the number of channels of the CAN bus data, a software structure is adopted to replace a hardware controller, a CAN bus input interface CAN be set according to the acquisition requirement of the data, the access requirement of a large amount of data CAN be met, meanwhile, the layout space of a hardware circuit is saved and potential fault points of the hardware circuit are reduced because the hardware controller is not added.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a data acquisition device according to the present invention;

FIG. 2 is a schematic structural diagram of a 32-channel CAN signal acquisition and storage device provided by the present invention;

fig. 3 is a schematic structural diagram of XC7a35T FPGA provided in the present invention.

Reference numerals:

100: a data acquisition device; 110: an FPGA unit;

120: a processor unit; 111: a MicroBlaze soft core;

112: an AXI CAN IP core; 130: a storage unit;

140: an interface unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a data acquisition device provided in the present invention, and as shown in fig. 1, the data acquisition device 100 includes:

the FPGA unit 110 comprises a MicroBlaze soft core 111 and an AXI CAN IP core 112, and is used for acquiring CAN bus data; the number of AXI CAN IP cores 112 is determined based on the number of channels of CAN bus data;

and the processor unit 120 is connected with the FPGA unit 110, and is configured to process the CAN bus data and determine a processing result of the CAN bus data.

Specifically, an IP core (Intellectual Property core) is a hardware description language program with specific circuit functions, which is independent of the ic process and can be migrated to different semiconductor processes to produce ic chips. The IP cores can be implemented at different hardware description levels, thus yielding two classes of IP cores: soft cores and hard cores.

The soft core is a functional block described in a hardware description language such as VHDL, but does not relate to implementation of these functions with specific circuit elements. The soft core is usually in the form of a Hardware Description Language (HDL) source file, and the application development process is very similar to that of a common HDL design, but the required hardware and software environment is expensive to develop. The design cycle of the soft core is short, and the design investment is low. Because physical implementation is not involved, a large play space is reserved for subsequent design, and the flexibility and the adaptability of the IP core are improved. The main disadvantage is that the subsequent process cannot adapt to the overall design to a certain extent, so that a certain degree of soft core correction is required, and comprehensive optimization cannot be obtained in performance.

The hardmac provides the final stage product of the design phase. Provided in the form of a fully placed and routed netlist, such a hardmac is both predictable and power and size optimized for a particular process. The hard core lacks flexibility and portability is poor.

Most of the IP cores applied to the FPGA are soft cores, and the soft cores are beneficial to users to adjust parameters and enhance reusability. The soft core is typically provided in encrypted form so that the actual register conversion stage circuitry is not visible to the user, but is flexible in layout and routing. In these encrypted soft cores, if the kernel is parameterized, the parameters can be conveniently manipulated by the user through a header file or a graphical user interface. For cores with strict timing requirements, specific signals can be pre-routed or specific routing resources can be allocated to meet the timing requirements.

The MicroBlaze soft core is an IP core of a microprocessor based on FPGA, and can complete the design of a programmable system chip together with other peripheral IP cores. The MicroBlaze soft core adopts 32-bit instructions and data buses of RISC architecture and Harvard architecture, and can execute programs stored in an on-chip memory and an external memory at full speed and access data of the programs. All instruction words are 32 bits long, with 3 operands and 2 addressing modes. The instructions are functionally divided into logical operations, arithmetic operations, branches, memory read/write, and special instructions, etc. The pipeline of instruction execution is a parallel pipeline, which is divided into 3 stages of pipelines: fetching, decoding and executing.

An AXI CAN IP core is an IP core that supports the AXI protocol that CAN be used to transmit CAN bus data.

The data acquisition device 100 in the embodiment of the present invention includes an FPGA unit 110 and a processor unit 120 connected to each other. The FPGA unit 110 is a Field Programmable Gate Array (Field Programmable Gate Array), and may include a MicroBlaze soft core 111 and multiple AXI CAN IP cores 112. The FPGA unit 110 is connected to an external CAN bus, and the MicroBlaze soft core 111 and the AXI CAN IP core 112 are operated, so that CAN bus data transmitted in the external CAN bus CAN be collected into a memory in the FPGA unit 110.

The number of AXI CAN IP cores 112 is configurable according to the number of channels of CAN bus data. For example, when the data acquisition apparatus 100 is used to acquire 32-way CAN bus data, the number of AXI CAN IP cores 112 may be configured to be 32; when the data collection apparatus 100 is used to collect 64-way CAN bus data, the number of AXI CAN IP cores 112 may be configured to be 64.

And the processor unit 120 is configured to process the CAN bus data and determine a processing result of the CAN bus data. For example, the processor unit 120 may perform formatting on the CAN bus data, and store the obtained multiple paths of CAN bus data in a file form, so as to facilitate data copying and transmission.

The data acquisition device provided by the embodiment of the invention comprises an FPGA unit and a processor unit which are connected with each other, wherein the FPGA unit comprises a MicroBlaze soft core and an AXI CAN IP core and is used for acquiring CAN bus data, the processor unit determines the processing result of the CAN bus data, the number of the AXI CAN IP cores is determined based on the number of channels of the CAN bus data, a software structure is adopted to replace a hardware controller, a CAN bus input interface CAN be set according to the acquisition requirement of the data, the access requirement of a large amount of data CAN be adapted, meanwhile, the layout space of a hardware circuit is saved and the potential fault points of the hardware circuit are reduced because the hardware controller is not added.

Based on the above embodiment, AXI CAN IP core 112 and MicroBlaze soft core 111 are connected via an AXI bus.

Specifically, multiple AXI CAN IP cores 112 may access the MicroBlaze soft core via an AXI bus.

Axi (advanced eXtensible interface) is a Bus protocol, which is the most important part of amba (advanced Microcontroller Bus architecture)3.0 protocol, and is an on-chip Bus oriented to high performance, high bandwidth and low latency. The address/control and data phase are separated, the unaligned data transmission is supported, only the first address is needed in burst transmission, the read-write data channel is separated, the advanced transmission access and the out-of-order access are supported, and the time sequence convergence is easier to carry out. AXI is a new high performance protocol in AMBA. The AXI technology enriches the content of the existing AMBA standard and meets the requirements of ultrahigh performance and complex system-on-chip design.

Based on any of the above embodiments, the number upper limit value of the AXI CAN IP cores 112 is determined based on the AXI bus.

Specifically, in order to ensure the transmission efficiency of CAN bus data, it is necessary to set a number upper limit value to the AXI CAN IP cores 112 so that the number of AXI CAN IP cores 112 does not exceed the bearer range of the AXI bus. The number upper limit value of AXI CAN IP cores 112 may be determined from the AXI bus.

Based on any of the above embodiments, the FPGA unit further includes:

the dual-port RAM is connected with the MicroBlaze soft core 111 and is used for storing CAN bus data;

and one end of the communication IP core is connected with the double-port RAM, and the other end of the communication IP core is connected with the processor unit 120 and used for controlling CAN bus data transmission.

Specifically, a RAM (Random Access Memory) is an internal Memory that directly exchanges data with the CPU. It can be read and written at any time, and is fast, usually used as temporary data storage medium of operating system or other running program.

A dual-port RAM is a Static Random-Access Memory (SRAM) having two completely independent sets of data lines, address lines, and read/write control lines, and allowing two independent systems to randomly Access the Memory.

In the embodiment of the invention, a dual-port RAM is arranged and connected with a MicroBlaze soft core 111 for storing CAN bus data. The CAN bus data stored in the dual port RAM will be transmitted to the processor unit 120.

The CAN bus data transmission process is realized by a communication IP core. One end of the communication IP core is connected to the dual port RAM, and the other end is connected to the processor unit 120.

Based on any of the above embodiments, the FPGA unit 110 further includes:

and the clock module is connected with the MicroBlaze soft core and is used for carrying out frequency multiplication and frequency division on the input clock of the FPGA unit and determining the working clock of the MicroBlaze soft core.

Specifically, the frequency multiplication is fully called a frequency multiplication coefficient. A ratio relation exists between the core working frequency of the CPU and the external frequency, and the ratio is a frequency multiplication coefficient, which is called frequency multiplication for short. In many electronic devices, signals of different frequencies are required to work cooperatively, and a common method is to use a crystal oscillator with high stability as a main oscillation source and obtain various required frequency components through conversion.

The FPGA unit 110 provided in the embodiment of the present invention may be provided with a clock module, which performs frequency multiplication and/or frequency division on an input clock of the FPGA unit to determine a working clock of the MicroBlaze soft core.

Based on any of the above embodiments, the FPGA unit 110 further includes:

and the debugging module is connected with the MicroBlaze soft core and is used for debugging the running program in the MicroBlaze soft core.

Specifically, a debugging module may be disposed in the FPGA unit 110 for debugging the running program in the MicroBlaze soft core.

For example, a JTAG emulator, also known as a JTAG debugger, is a device that performs debugging through the JTAG boundary scan port of a chip. And connecting an interface of the debugging module with the JTAG simulator, thereby realizing debugging of the running program in the MicroBlaze soft core.

According to any of the above embodiments, the FPGA unit 110 and the processor unit 120 are connected via a GPMC bus.

Specifically, a GPMC (General-Purpose Memory Controller) is used to connect external Memory devices. Depending on the type of memory being controlled, the memory is generally divided into two categories: a dedicated memory controller and a general purpose memory controller. Through the IP core reusing mode, the universal memory can be suitable for high-performance SOC (System On a chip) systems with different requirements, so that the system development time is reduced, and the cost is saved.

Based on any of the above embodiments, the processing result of the CAN bus data is in the Linux file system format.

Specifically, there are four formats in the Linux operating system, namely Ext2, Ext3, Linux swap and VFAT.

Wherein, Ext2 is a standard file system in the Linux system. The file system is the most used file system in Linux, is specially designed for Linux, and has extremely high speed and extremely low CPU occupancy rate. Ext2 can be used in standard block devices (e.g., hard disk) as well as in removable storage devices such as floppy disks.

Ext3 is the next generation of Ext2, i.e., the format of Ext2 plus logging functionality. Ext3 is a journaling file system, and has the following characteristics: it records the entire writing action on a certain area of the disk completely so as to trace back when necessary. When interrupted at a certain process, the system can go back and reform the interrupted part directly from these records, and the reforming speed is quite fast. The partition format is widely applied to Linux systems.

The Linux swap is a swap file system specially used for swap partitions in Linux. Linux uses this entire partition as swap space. Typically, this swap format swap partition is 2 times larger than the main memory. When the memory is insufficient, Linux can write part of data to the swap partition.

The VFAT is a long file name system, is a Linux file system compatible with a Windows system, supports long file names and can be used as a partition for exchanging files between Windows and Linux.

Based on any of the above embodiments, the data acquisition apparatus 100 further includes:

and a storage unit 130 connected to the processor unit 120, for storing the processing result of the CAN bus data.

Specifically, the storage unit 130 is an external storage medium, such as an SD card or the like, for storing the processing result of the CAN bus data. For example, the processed result of the CAN bus data is stored in the Ext2 file format after being processed. At this time, the Ext2 file CAN be stored in the SD card to backup the CAN bus data and prevent data loss.

Based on any of the above embodiments, the data acquisition apparatus 100 further includes:

and an interface unit 140 connected to the processor unit 120, for transmitting the processing result of the CAN bus data.

Specifically, the interface unit 140 is connected to the processor unit 120, and is configured to transmit a processing result of CAN bus data to an external control system.

In a rail transit system, a rail and a surrounding environment need to be detected in real time, so a large number of detection devices need to be deployed, the detection devices generally adopt CAN communication interface modes, a general embedded processor CAN smoothly run a Linux system, data CAN be stored and managed by depending on a powerful file system in the Linux system, but the number of CAN interfaces of the embedded processor is limited, generally 1-4, and multiple CAN interfaces are difficult to realize.

The embodiment of the invention combines XC7A35T FPGA hardware and MicroBlaze soft core embedded processor technology with AXI CAN IP core, and CAN realize the acquisition of multiple CAN communication interfaces. The device for acquiring and storing the 32-channel CAN signals is developed by combining the advantages of the two technologies.

Based on any of the above embodiments, fig. 2 is a schematic structural diagram of a 32-way CAN signal acquisition and storage device provided by the present invention, and as shown in fig. 2, the device is composed of a XILINX FPGA XC7a35T part, an AM5718 Sitara ARM application processor part, a memory part, a USB3.0 interface part, and a CAN communication interface part.

The Linux operating system runs in the AM5718 Sitara ARM application processor, and data transmission is carried out between the AM5718 Sitara ARM application processor and the XC7A35T through a GPMC bus.

XC7A35T FPGA is responsible for 32 way CAN communication signal's the collection, runs the collection of MicroBlaze soft core + AXI CAN IP core in this FPGA, gathers CAN communication signal in the buffer memory, utilizes GPMC bus XC7A35T to transmit the data of gathering to AM5718, and AM5718 stores the data to the SD card in the form of file.

The AM5718 is provided with a USB3.0 interface, and can use a USB 3.0U disk to copy data, and the data transmission rate can reach 100MB per second.

Fig. 3 is a schematic structural diagram of an XC7a35T FPGA provided by the present invention, and as shown in fig. 3, XC7a35T extends a CAN communication interface to 32 channels. The design of a System On Programmable Chip (SOPC) is realized by using a MicroBlaze soft core embedded processor technology in XC7A35T and utilizing general resources in FPGA and AXI CAN IP core.

The part consists of a MicroBlaze soft core, a debugging module, a clock module, a memory, an AXI bus internal connector, an AXI CAN IP core, a double-port RAM and a custom IP core (BRAM Read).

Wherein the MicroBlaze soft core supports 70 configuration options, 32 general purpose registers with 3 bits and 2 special registers with 32 bits (PC pointer register and MSR status flag register).

The debugging module is used for connecting and debugging the JTAG simulator.

The clock module can carry out frequency multiplication and frequency division on an input clock, and provides a proper working clock for the MicroBlaze soft core.

The memory is used for providing storage space for the MicroBlaze soft core during operation.

The AXI bus internal connector is used for realizing the access of an IP core with an AXI protocol interface to the MicroBlaze soft core.

The AXI CAN IP core is used for realizing a CAN communication interface.

The dual-port RAM is used for data interaction between the MicroBlaze soft core and an external processor.

The user-defined IP core is a user-defined IP core, and data reading and writing of the GPMC bus and the dual-port RAM are realized.

The Linux operating system combines separate file systems into a hierarchical tree structure and represents this file system by a single entity. Linux allows new file systems to be mounted to a directory by an operation called "mount" or "mount", thereby allowing different file systems to be combined into a single entity. An important feature of the Linux operating system is that it supports many different types of file systems. The most commonly used file system in Linux is Ext2, and different types of file systems such as FAT, VFAT, FAT32, MINIX, etc. can also be supported, so that data can be conveniently exchanged with other operating systems. Since Linux supports many different file systems and organizes them into one unified virtual file system. The Ext2 file system is used in the present device.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes commands for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.