阅读说明：本技术 一种适用于usb-pd协议的bmc码异步接收方法及存储设备 (BMC code asynchronous receiving method suitable for USB-PD protocol and storage device ) 是由 施乐宁 胡如波 于 2019-08-02 设计创作，主要内容包括：本发明涉及解码技术领域,特别涉及一种适用于USB-PD协议的BMC码异步接收方法及存储设备。所述一种适用于USB-PD协议的BMC码异步接收方法,包括步骤：设置采样时钟频率为码率的数倍；并根据采样时钟频率为码率的倍数的不同,设定在不同的时钟个数内执行不同的预设操作。通过上述方法,提高解码器的运行时钟,扩大解码采样沿跳变的窗口时间,使得即使接收端时钟频偏±2％仍可以接受发送端±20％频偏的信号。(The invention relates to the technical field of decoding, in particular to a BMC (baseboard management controller) code asynchronous receiving method and storage equipment suitable for a USB-PD (Universal Serial bus-PD) protocol. The asynchronous BMC code receiving method applicable to the USB-PD protocol comprises the following steps: setting the sampling clock frequency to be multiple times of the code rate; and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate. By the method, the running clock of the decoder is improved, and the window time of decoding sampling edge jump is expanded, so that a signal with +/-20% frequency offset of a sending end can be received even if the clock frequency offset of a receiving end is +/-2%.)

1. A BMC code asynchronous receiving method suitable for a USB-PD protocol is characterized by comprising the following steps:

setting the sampling clock frequency to be multiple times of the code rate;

and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

2. The asynchronous BMC code receiving method for the USB-PD protocol as claimed in claim 1,

setting the sampling clock frequency to be ten times of the code rate 3M;

setting 0-3 clocks for waiting;

setting 4-6 clocks for sampling the intermediate level jump;

setting a waiting ending level at a 7 th clock;

set at the 8 th-13 th clock sample end level.

3. A storage device having a set of instructions stored therein, the set of instructions being operable to perform:

setting the sampling clock frequency to be multiple times of the code rate;

and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

4. A storage device according to claim 3, wherein the set of instructions is further configured to perform:

setting the sampling clock frequency to be ten times of the code rate 3M;

setting 0-3 clocks for waiting;

setting 4-6 clocks for sampling the intermediate level jump;

setting a waiting ending level at a 7 th clock;

set at the 8 th-13 th clock sample end level.

Technical Field

The invention relates to the technical field of decoding, in particular to a BMC (baseboard management controller) code asynchronous receiving method and storage equipment suitable for a USB-PD (Universal Serial bus-PD) protocol.

Background

With the development of electronic technology, the application of USB interface to provide power has risen to the position of being as important as data transmission. The newly released USB Type-C Power Delivery protocol (hereinafter referred to as PD protocol) is based on USB version 3.1, that is, a Power transmission protocol based on Type-C interface. The USB PD can support 100W (20V/5A) power transmission at most, and simultaneously support power supply role conversion, and can meet the power supply requirements of most electronic equipment. In the USB Type-C interface, the USBPD communication uses a two-way Mark Coding (BMC) to transmit data on the CC channel. The method is simple and flexible, has been released as a PD communication standard, and is gradually widely applied at present.

The BMC coding belongs to a coding technology of phase modulation, and is a coding method for mixing a clock and data together for transmission. BMC coding is characterized by a level jump at the beginning of each bit period. The level change is used to represent logic in one bit period, if the level jumps in the middle of the bit period, it represents logic "1", otherwise it represents logic "0". By using the BMC coding, the transmission end and the receiving end can transmit and receive data correctly only by one data line, and good synchronism is kept at the transmitting end and the receiving end.

In the prior art, decoding is typically performed using a fixed single clock window, but since the PD protocol allows the code to have a frequency deviation of +/-10%, a higher bit error rate results if the signal is sampled at all times with a fixed single clock window.

Disclosure of Invention

Therefore, a BMC code asynchronous receiving method suitable for a USB-PD protocol needs to be provided to solve the problem that a fixed single clock window is used for decoding in the prior art, which may result in a high error rate, and the specific technical scheme is as follows:

a BMC code asynchronous receiving method suitable for a USB-PD protocol comprises the following steps: setting the sampling clock frequency to be multiple times of the code rate; and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

Further, setting the sampling clock frequency to be ten times of the code rate 3M; setting 0-3 clocks for waiting; setting 4-6 clocks for sampling the intermediate level jump; setting a waiting ending level at a 7 th clock; set at the 8 th-13 th clock sample end level.

In order to solve the technical problem, the storage device is further provided, and the specific technical scheme is as follows:

a storage device having stored therein a set of instructions for performing: setting the sampling clock frequency to be multiple times of the code rate; and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

Further, the set of instructions is further for performing: setting the sampling clock frequency to be ten times of the code rate 3M; setting 0-3 clocks for waiting; setting 4-6 clocks for sampling the intermediate level jump; setting a waiting ending level at a 7 th clock; set at the 8 th-13 th clock sample end level.

The invention has the beneficial effects that: the range of 2.66us-4.00us is just within +/-20% of 300k specified by the BMC code. In this scheme 456clk is used to sample the inversion of the intermediate level and 8-13clk is used to sample the inversion of the end level. If the frequency offset at the receiving end is-2%, the end level inversion can be sampled at the 8 th clk; if the receiving end frequency offset is + 2%, the 13 th clk samples the inversion of the end level; therefore, after the technical scheme is adopted, even if the clock frequency deviation of the receiving end is +/-2%, the signal of +/-20% frequency deviation of the transmitting end can be still received.

Drawings

Fig. 1 is a flowchart of a BMC code asynchronous receiving method suitable for a USB-PD protocol according to an embodiment;

FIG. 2 is a flowchart illustrating setting a sampling clock frequency to ten times a code rate of 3M according to an embodiment;

FIG. 3 is a diagram illustrating setting a sampling clock frequency to ten times a code rate of 3M according to an embodiment;

FIG. 4 is a diagram illustrating BMC code features in accordance with an embodiment;

fig. 5 is a block diagram of a storage device according to an embodiment.

Description of reference numerals:

500. a storage device.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to fig. 3, in the present embodiment, a BMC code asynchronous receiving method suitable for the USB-PD protocol is applicable to a storage device, which may be a decoder.

The specific implementation mode is as follows:

step S101: and setting the sampling clock frequency to be multiple times of the code rate.

Step S102: and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

In this embodiment, it is preferable to set the sampling clock frequency to be ten times of the code rate 3M, which is a clock frequency that can ensure the receiving accuracy and is economical at present. In other embodiments, other higher-power clocks may be used to achieve higher acceptance rates. Such as: with 20M clock, the scaling up is equal, and the corresponding sampling period may be: setting for waiting at 1-6 clocks, setting for sampling at 7-12 clocks for intermediate level transition, setting for waiting at 13-14 clocks for ending, and setting for sampling at 15-26 clocks for ending.

Referring to fig. 2, the following description will be made for an embodiment of setting the sampling clock frequency to be ten times the code rate 3M:

step S201: and setting the sampling clock frequency to be ten times of the code rate 3M.

Step S202: set to 0-3 clocks for waiting.

Step S203: the sampling of the intermediate level transitions is set at 4-6 clocks.

Step S204: set at the 7 th clock wait for end level.

Step S205: set at the 8 th-13 th clock sample end level.

By the method, the running clock of the decoder is improved, and the window time of decoding sampling edge jump is expanded, so that a signal with +/-20% frequency offset of a sending end can be received even if the clock frequency offset of a receiving end is +/-2%.

Referring to fig. 3, in fig. 3, 2.66us-4.00us are exactly within ± 20% of 300k specified by BMC code. In this scheme 456clk is used to sample the inversion of the intermediate level and 8-13clk is used to sample the inversion of the end level. If the frequency offset at the receiving end is-2%, refer to min in fig. 3: at the 8 th clk the inversion of the end level may be sampled; if the receiver side frequency offset is + 2%, then referring to max in fig. 3: inversion of the end level of the 13 th clk sample; therefore, the technical scheme can enable the receiving end clock frequency deviation of +/-2% to still receive the signal of +/-20% frequency deviation of the transmitting end.

Referring to fig. 4, the specific principle of the above steps is as follows,

characteristics of the BMC code:

1. the first time of level inversion represents the position of an initial point;

2. the level reversal representation of the middle point position is 1, and the non-reversal representation of the middle point is 0;

3. therefore, the starting point, the middle point and the ending point 3 must be sampled, namely 0, 50% and 100% of 1UI are sampled;

4. since the protocol specifies that the generating end can have a frequency offset of + -10%, sampling at + -10% of 50% and + -10% of 100% is required;

5. take [270k,330k ] two endpoints as an example:

(1)、270k:1/270k*0.5*3M＝5.6；

(2)、330k:1/330k*0.5*3M＝4.5；

so if 3M clock is used for sampling, the intermediate level must be sampled at 4-6 clock times to determine whether the intermediate level is inverted;

6. the sampling end level will be sampled earlier when the sampling is ended, the principle here is the same as in item 5, but the judgment time of the sampling end is slightly enlarged in consideration of the self frequency offset of the receiving end.

Referring to fig. 5, in the present embodiment, a memory device 500 is implemented as follows:

a storage device 500 having stored therein a set of instructions for performing: setting the sampling clock frequency to be multiple times of the code rate; and setting different preset operations within different clock numbers according to the difference that the sampling clock frequency is the multiple of the code rate.

Further, the set of instructions is further for performing: setting the sampling clock frequency to be ten times of the code rate 3M; setting 0-3 clocks for waiting; setting 4-6 clocks for sampling the intermediate level jump; setting a waiting ending level at a 7 th clock; set at the 8 th-13 th clock sample end level.

By executing the above instructions through the storage device 500, the window time of decoding sampling edge jump is expanded, so that even if the clock frequency of the receiving end is shifted by ± 2%, the signal of ± 20% frequency offset of the transmitting end can be received.

Referring to fig. 3, in fig. 3, 2.66us-4.00us are exactly within ± 20% of 300k specified by BMC code. In this scheme 456clk is used to sample the inversion of the intermediate level and 8-13clk is used to sample the inversion of the end level. If the frequency offset at the receiving end is-2%, refer to min in fig. 3: at the 8 th clk the inversion of the end level may be sampled; if the receiver side frequency offset is + 2%, then referring to max in fig. 3: inversion of the end level of the 13 th clk sample; therefore, the technical scheme can enable the receiving end clock frequency deviation of +/-2% to still receive the signal of +/-20% frequency deviation of the transmitting end.

Referring to fig. 4, the specific principle of the above steps is as follows,

characteristics of the BMC code:

1. the first time of level inversion represents the position of an initial point;

2. the level reversal representation of the middle point position is 1, and the non-reversal representation of the middle point is 0;

3. therefore, the starting point, the middle point and the ending point 3 must be sampled, namely 0, 50% and 100% of 1UI are sampled;

4. since the protocol specifies that the generating end can have a frequency offset of + -10%, sampling at + -10% of 50% and + -10% of 100% is required;

5. take [270k,330k ] two endpoints as an example:

(1)、270k:1/270k*0.5*3M＝5.6；

(2)、330k:1/330k*0.5*3M＝4.5；

so if 3M clock is used for sampling, the intermediate level must be sampled at 4-6 clock times to determine whether the intermediate level is inverted;

6. the sampling end level will be sampled earlier when the sampling is ended, the principle here is the same as in item 5, but the judgment time of the sampling end is slightly enlarged in consideration of the self frequency offset of the receiving end.

In this embodiment, it is preferable to set the sampling clock frequency to be ten times the code rate 3M, which is a clock frequency that can ensure the accuracy of reception and is economical at present. In other embodiments, other higher-power clocks may be used to achieve higher acceptance rates. Such as: with 20M clock, the scaling up is equal, and the corresponding sampling period may be: setting for waiting at 1-6 clocks, setting for sampling at 7-12 clocks for intermediate level transition, setting for waiting at 13-14 clocks for ending, and setting for sampling at 15-26 clocks for ending.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.