Data acquisition circuit, and method and device for controlling read data window
阅读说明：本技术 数据采集电路、读数据窗口的控制方法及装置 (Data acquisition circuit, and method and device for controlling read data window ) 是由 黄帅 王焕东 刘志佳 于 2018-06-26 设计创作，主要内容包括：本发明提供一种数据采集电路、读数据窗口的控制方法、装置及内存控制器,通过在用于读数据的首个数据选通信号DQS的读前导区域内,确定初始门信号与首个DQS上升沿的相位关系,生成第一门延迟信号；在每个存储体对应的DQS的第一个下降沿,采集第一门延迟信号,得到每个存储体对应的第二门延迟信号的起始位置,生成每个存储体对应的第二门延迟信号；根据每个存储体对应的第二门延迟信号,或者根据第一门延迟信号和每个存储体对应的第二门延迟信号,确定每个存储体对应的读数据窗口。保证了内存控制器对DDRx SDRAM存储器读数据窗口的准确确定,保证了对DDRx存储器数据读取的可靠性。(The invention provides a data acquisition circuit, a control method and a control device of a data reading window and a memory controller, wherein a phase relation between an initial gate signal and a first data strobe signal DQS rising edge is determined in a reading leading region of the first data strobe signal DQS for reading data to generate a first gate delay signal; collecting a first gate delay signal at a first falling edge of the DQS corresponding to each memory bank to obtain a start position of a second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank; and determining a read data window corresponding to each memory bank according to the second gate delay signal corresponding to each memory bank or according to the first gate delay signal and the second gate delay signal corresponding to each memory bank. The method and the device ensure the accurate determination of the memory controller on the data reading window of the DDRx SDRAM and ensure the reliability of data reading of the DDRx SDRAM.)
1. A data acquisition circuit, comprising:
the delay circuit is used for determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a read leading region of the first data strobe signal DQS for reading data and generating a first gate delay signal;
the falling edge generation gate delay signal circuit is connected with the delay circuit, receives the DQS signal corresponding to each memory bank and receives the first gate delay signal output by the delay circuit; collecting the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank;
and the selection circuit is connected with the falling edge generation gate delay signal circuit and the delay circuit, and is used for determining a read data window corresponding to each memory bank in the DDRx SDRAM according to the second gate delay signal corresponding to each memory bank or the first gate delay signal and the second gate delay signal corresponding to each memory bank.
2. The data acquisition circuit of claim 1,
the falling edge generation gate delay signal circuit is further used for determining the signal width of the second gate delay signal corresponding to each memory bank according to a preset count value; and generating the second gate delay signal corresponding to each memory bank according to the starting position and the signal width of the second gate delay signal.
3. The data acquisition circuit of claim 2,
the falling edge generation gate delay signal circuit is also used for determining the preset count value according to the burst length BL of the read command; when the DDRx SDRAM is a DDR4 type memory, determining that the preset count value is BL/2-2, and the signal width of the second gate delay signal is +1 clock cycle of the preset count value; when the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-1, and the signal width of the second gate delay signal is +1 clock period of the preset count value.
4. The data acquisition circuit of claim 1, wherein the selection circuit comprises: or gate, selector;
the OR gate is respectively connected with the delay circuit and the falling edge generation gate delay signal circuit and is used for receiving the first gate delay signal output by the delay circuit and receiving the second gate delay signal output by the falling edge generation gate delay signal circuit; performing an or operation on the first gate delay signal and the second gate delay signal to obtain an or-processed gate delay signal;
the selector is respectively connected with the falling edge generation gate delay signal circuit and the OR gate and is used for gating the second gate delay signal output by the falling edge generation gate delay signal circuit when the DDRx SDRAM is a DDR4 type memory; determining a read data window corresponding to each memory bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each memory bank; the or gate delay signal is used for gating the or gate output when the DDRx SDRAM is a DDR2 type or DDR3 type memory; determining a read data window corresponding to each bank in the DDR2 or DDR3 memory as a signal width of the OR-processed gate delay signal corresponding to each bank.
5. The data acquisition circuit according to any one of claims 1 to 4, wherein the signal width of the first gate delay signal is less than or equal to a burst length BL/2 of a read command.
6. A memory controller, comprising: a gate signal generation module further comprising the data acquisition circuit of any one of claims 1 to 5; the gate signal generating module is used for generating the initial gate signal after the memory controller sends out a read command for reading DDRxSDRAM memory data; the delay circuit in the data acquisition circuit is connected with the gate signal generation module and used for receiving the initial gate signal.
7. A method for controlling a read data window, comprising:
determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a reading leading region of the first data strobe signal DQS for reading data to generate a first gate delay signal;
collecting the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank;
and determining a read data window corresponding to each memory bank in the DDRx SDRAM according to the second gate delay signal corresponding to each memory bank or the first gate delay signal and the second gate delay signal corresponding to each memory bank.
8. The method of claim 7, wherein the collecting the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain a start position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank comprises:
determining the signal width of the second gate delay signal according to a preset count value;
and generating the second gate delay signal according to the starting position and the signal width of the second gate delay signal.
9. The method of claim 8, further comprising:
determining the preset count value according to the burst length BL of the read command;
correspondingly, the determining the signal width of the second gate delay signal according to the preset count value includes:
if the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-2, and determining that the signal width of the second gate delay signal is +1 clock cycle of the preset count value;
if the DDRx SDRAM is a DDR4 type memory, the preset count value is BL/2-1, and the signal width of the second gate delay signal is determined to be +1 clock cycles of the preset count value.
10. The method of claim 8, wherein determining a read data window corresponding to each bank in a DDRx SDRAM memory according to the second gate delay signal corresponding to each bank, or according to the first gate delay signal and the second gate delay signal corresponding to each bank comprises:
if the DDRx SDRAM is a DDR4 type memory, determining a read data window corresponding to each bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each bank;
if the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining a read data window corresponding to each bank in the DDR2 type or DDR3 type memory to be a sum of a signal width of the second gate delay signal and a signal width of the first gate delay signal corresponding to each bank.
11. The method according to any one of claims 8 to 10, wherein the signal width of the first gate delay signal is less than or equal to a burst length BL/2 of a read command.
12. A control device for reading a data window, comprising:
the first gate delay signal generating module is used for determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a read preamble region of the first data strobe signal DQS for reading data and generating a first gate delay signal;
the second gate delay signal generation module is used for acquiring the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank and generate the second gate delay signal corresponding to each memory bank;
and the determining module is used for determining a read data window corresponding to each memory bank in the memory according to the second gate delay signal corresponding to each memory bank or according to the first gate delay signal and the second gate delay signal corresponding to each memory bank.
13. The apparatus of claim 12, wherein the second gate delay signal generating module comprises:
the determining submodule is used for determining the signal width of the second gate delay signal according to a preset counting value;
and the generation submodule is used for generating the second gate delay signal according to the starting position and the signal width of the second gate delay signal.
14. The apparatus of claim 13,
the determining module is further configured to determine the preset count value according to a burst length BL of the read command; when the DDRx SDRAM is a DDR4 type memory, determining that the preset count value is BL/2-2, and the signal width of the second gate delay signal is +1 clock cycle of the preset count value; when the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-1, and the signal width of the second gate delay signal is +1 clock period of the preset count value.
15. The apparatus of claim 12, wherein the determining module comprises:
a first determining submodule, configured to determine, when the DDRx SDRAM is a DDR4 type memory, a read data window corresponding to each bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each bank;
a second determining submodule, configured to determine, when the DDRx SDRAM is a DDR2 type or DDR3 type memory, that a read data window corresponding to each bank in the DDR2 type or DDR3 type memory is a sum of a signal width of the second gate delay signal and a signal width of the first gate delay signal corresponding to each bank.
16. The apparatus of any one of claims 12-15, wherein the first gate delay signal has a signal width equal to or less than a burst length BL/2 of a read command.
Technical Field
The present invention relates to a reading technology of a memory, and in particular, to a data acquisition circuit, a method and an apparatus for controlling a read data window, and a memory controller.
Background
In the Data reading process of a DDR Memory controller to a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), a read Data strobe signal DQS is utilized to judge when effective read Data DQ exists, and meanwhile, the relationship between the read Data strobe signal DQS and an internal system clock is utilized to determine how to synchronize the returned Data DQ into a system clock domain. But the phase relationship of the read data strobe signal DQS and the internal system clock is completely uncertain considering different system environments, such as different PCB traces, different operating frequencies, etc. Particularly, for the Fly-by routing manner of the DDR3/4 memory module, as shown in fig. 1, after the memory controller sends a Read command, the Read command may pass through each memory chip one by one, as shown by an arrow in fig. 1, pass through the
For such a situation, in the prior art, a delay circuit is usually adopted to delay a gate signal generated by a memory controller after the memory controller issues a read command, so as to obtain a rdgate signal, where a high level of the rdgate signal is located in the middle of a read DQS signal, so as to ensure that the DQS can completely read the memory data. However, since the original gate signal pulse width of the memory controller is fixed, the Burst Length (BL) is 4, the gate signal has a width of 2 clock cycles, the gate signal has a width of 4 clock cycles, the BL is 8, and thus the pulse width of the rdgate signal after the delay time is consistent with the gate signal and also has a fixed width, in order to save the design overhead, the memory controller supporting multiple banks (RANK) integrates only one rdgate module in each data processing unit, i.e. one rdgate module is used to process the read DQS signals returned from multiple RANKs sharing the same data channel, in this case, if the distances between different RANKs are too large, the phase difference between the read DQS signals will cause the effective read DQS signals to be filtered out by the internal rdgate signals, thereby generating errors, as shown in fig. 2, the memory controller determines the position of the gate signal according to rddqs0 returned from RANK0, the rddqs _ clean _0 signal is derived from the rdgate intercept rddqs0, and since there is only one rdgate block in a data processing unit, its position does not change after the rdgate signal is asserted. When RANK1 (farther from the memory controller than RANK 0) returns rddqs1, a correct clock signal rddqs _ clear _1 is obtained by the rdgate
Therefore, no matter the spacing between different memory chips in fig. 1 or the spacing between the RANKs distributed on one memory chip or different chips, the maximum number of RANKs that can be supported by one memory channel is limited, that is, the read window after the memory controller issues the read command is difficult to be accurately determined to read the data in all RANKs, and the inaccuracy of the read window is liable to cause the problem of data loss.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a method and a device for controlling a data reading window, a data acquisition circuit and a memory controller, so as to generate an accurate data reading window and ensure the complete reading of data of a plurality of memory banks.
In a first aspect, an embodiment of the present invention provides a data acquisition circuit, including:
the delay circuit is used for determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a read leading region of the first data strobe signal DQS for reading data and generating a first gate delay signal;
the falling edge generation gate delay signal circuit is connected with the delay circuit, receives the DQS signal corresponding to each memory bank and receives the first gate delay signal output by the delay circuit; collecting the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank;
and the selection circuit is connected with the falling edge generation gate delay signal circuit and the delay circuit, and is used for determining a read data window corresponding to each memory bank in the DDRx SDRAM according to the second gate delay signal corresponding to each memory bank or the first gate delay signal and the second gate delay signal corresponding to each memory bank.
Optionally, the falling edge generation gate delay signal circuit is further configured to determine, according to a preset count value, a signal width of the second gate delay signal corresponding to each memory bank; and generating the second gate delay signal corresponding to each memory bank according to the starting position and the signal width of the second gate delay signal.
Optionally, the falling edge generates a gate delay signal circuit, and is further configured to determine the preset count value according to a burst length BL of a read command; when the DDRx SDRAM is a DDR4 type memory, determining that the preset count value is BL/2-2, and the signal width of the second gate delay signal is +1 clock cycle of the preset count value; when the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-1, and the signal width of the second gate delay signal is +1 clock period of the preset count value.
Optionally, the selection circuit includes: or gate, selector;
the OR gate is respectively connected with the delay circuit and the falling edge generation gate delay signal circuit and is used for receiving the first gate delay signal output by the delay circuit and receiving the second gate delay signal output by the falling edge generation gate delay signal circuit; performing an or operation on the first gate delay signal and the second gate delay signal to obtain an or-processed gate delay signal;
the selector is respectively connected with the falling edge generation gate delay signal circuit and the OR gate and is used for gating the second gate delay signal output by the falling edge generation gate delay signal circuit when the DDRx SDRAM is a DDR4 type memory; determining a read data window corresponding to each memory bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each memory bank; the or gate delay signal is used for gating the or gate output when the DDRx SDRAM is a DDR2 type or DDR3 type memory; determining a read data window corresponding to each bank in the DDR2 or DDR3 memory as a signal width of the OR-processed gate delay signal corresponding to each bank.
Optionally, a signal width of the first gate delay signal is less than or equal to a burst length BL/2 of the read command.
In a second aspect, an embodiment of the present invention provides a memory controller, including: a gate signal generation module further comprising the data acquisition circuit of any one of the preceding third aspects; the gate signal generating module is used for generating the initial gate signal after the memory controller sends out a read command for reading DDRx SDRAM memory data; the delay circuit in the data acquisition circuit is connected with the gate signal generation module and used for receiving the initial gate signal.
In a third aspect, an embodiment of the present invention provides a method for controlling a read data window, including:
determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a reading leading region of the first data strobe signal DQS for reading data to generate a first gate delay signal;
collecting the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank;
and determining a read data window corresponding to each memory bank in the DDRx SDRAM according to the second gate delay signal corresponding to each memory bank or the first gate delay signal and the second gate delay signal corresponding to each memory bank.
Optionally, the acquiring the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain a start position of the second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank includes:
determining the signal width of the second gate delay signal according to a preset count value;
and generating the second gate delay signal according to the starting position and the signal width of the second gate delay signal.
Optionally, the method further includes:
determining the preset count value according to the burst length BL of the read command;
correspondingly, the determining the signal width of the second gate delay signal according to the preset count value includes:
if the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-2, and determining that the signal width of the second gate delay signal is +1 clock cycle of the preset count value;
if the DDRx SDRAM is a DDR4 type memory, the preset count value is BL/2-1, and the signal width of the second gate delay signal is determined to be +1 clock cycles of the preset count value.
Optionally, the determining a read data window corresponding to each memory bank in the DDRx SDRAM memory according to the second gate delay signal corresponding to each memory bank, or according to the first gate delay signal and the second gate delay signal corresponding to each memory bank, includes:
if the DDRx SDRAM is a DDR4 type memory, determining a read data window corresponding to each bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each bank;
if the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining a read data window corresponding to each bank in the DDR2 type or DDR3 type memory to be a sum of a signal width of the second gate delay signal and a signal width of the first gate delay signal corresponding to each bank.
Optionally, a signal width of the first gate delay signal is less than or equal to a burst length BL/2 of the read command.
In a fourth aspect, an embodiment of the present invention provides a control device for reading a data window, including:
the first gate delay signal generating module is used for determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a read preamble region of the first data strobe signal DQS for reading data and generating a first gate delay signal; the second gate delay signal generation module is used for acquiring the first gate delay signal at the first falling edge of the DQS corresponding to each memory bank to obtain the starting position of the second gate delay signal corresponding to each memory bank and generate the second gate delay signal corresponding to each memory bank;
and the determining module is used for determining a read data window corresponding to each memory bank in the DDRx SDRAM memory according to the second gate delay signal corresponding to each memory bank, or according to the first gate delay signal and the second gate delay signal corresponding to each memory bank.
Optionally, the second gate delay signal generating module includes:
the determining submodule is used for determining the signal width of the second gate delay signal according to a preset counting value;
and the generation submodule is used for generating the second gate delay signal according to the starting position and the signal width of the second gate delay signal.
Optionally, the determining module is further configured to determine the preset count value according to a burst length BL of the read command; when the DDRx SDRAM is a DDR4 type memory, determining that the preset count value is BL/2-2, and the signal width of the second gate delay signal is +1 clock cycle of the preset count value; when the DDRx SDRAM is a DDR2 type or DDR3 type memory, determining that the preset count value is BL/2-1, and the signal width of the second gate delay signal is +1 clock period of the preset count value.
Optionally, the determining module includes:
a first determining submodule, configured to determine, when the DDRx SDRAM is a DDR4 type memory, a read data window corresponding to each bank in the DDR4 type memory as a signal width of the second gate delay signal corresponding to each bank;
a second determining submodule, configured to determine, when the DDRx SDRAM is a DDR2 type or DDR3 type memory, that a read data window corresponding to each bank in the DDR2 type or DDR3 type memory is a sum of a signal width of the second gate delay signal and a signal width of the first gate delay signal corresponding to each bank.
Optionally, a signal width of the first gate delay signal is less than or equal to a burst length BL/2 of the read command.
The invention provides a data acquisition circuit, a control method and a control device of a data reading window and a memory controller, wherein a first gate delay signal is generated by determining the phase relation between an initial gate signal and the rising edge of a first data strobe signal DQS in a reading leading region of the first data strobe signal DQS for reading data; collecting a first gate delay signal at a first falling edge of the DQS corresponding to each memory bank to obtain a start position of a second gate delay signal corresponding to each memory bank, and generating the second gate delay signal corresponding to each memory bank; and determining a read data window corresponding to each memory bank in the DDRx SDRAM according to the second gate delay signal corresponding to each memory bank or the first gate delay signal and the second gate delay signal corresponding to each memory bank. The second gate delay signal is generated based on the position of the falling edge of the DQS corresponding to each memory bank, which appears for the first time in the first gate delay signal, so that the second gate delay signal, or the first gate delay signal and the second gate delay signal, can cover the memory bank (RANK) farthest from the memory controller, thereby ensuring the accurate determination of the memory controller on the data reading window of the DDRx SDRAM and the reliability of data reading of the DDRx SDRAM.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a topological structure of a DDRx SDRAM memory;
FIG. 2 is a diagram of read DQS returned by multiple RANKs intercepted by the rdgate signal in the prior art;
FIG. 3a is a flowchart illustrating a method for controlling a read data window of the present invention in accordance with an exemplary embodiment;
FIG. 3b is a prior art gate signal processing circuit;
FIG. 3c is a schematic diagram of a gate signal after a read command;
FIG. 3d is a signal waveform diagram of the embodiment shown in FIG. 3 a;
FIG. 4a is a flowchart illustrating a method for controlling a read data window of the present invention in accordance with another exemplary embodiment;
FIG. 4b is a signal waveform diagram of the embodiment shown in FIG. 4 a;
FIG. 4c is a schematic diagram of another signal waveform of the embodiment shown in FIG. 4 a;
FIG. 5 is a block diagram illustrating an exemplary embodiment of a control device for reading a data window according to the present invention;
FIG. 6 is a schematic diagram illustrating an exemplary embodiment of a control device for reading a data window according to the present invention;
FIG. 7 is a schematic diagram of the data acquisition circuit of the present invention in accordance with an exemplary embodiment;
fig. 8 is a schematic diagram of a data acquisition circuit according to another exemplary embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
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