阅读说明：本技术 一种3d nand及其制作方法 (3D NAND and manufacturing method thereof ) 是由 陈亮 刘威 于 2019-09-27 设计创作，主要内容包括：本申请公开一种3D NAND及其制作方法,其中,3D NAND通过第一金属部将金属层中的第一金属部和第一半导体衬底电性连接,通过第二金属部将金属层中的第二金属部和通孔中导电层电性连接,其中,通孔中的导电层、介质层与第一半导体衬底之间形成电容,使得电容位于衬底内,占据3DNAND的第一半导体衬底的闲置区域,从而避免占用较大的衬底区域。同时,第一金属部作为第一极板、第二金属部作为第二极板,第一金属部和第二金属部之间还能形成MOM电容,从而增大了第一金属部、第一半导体衬底、介质层、导电层、第二金属部之间形成的电容的容量。(The application discloses 3D NAND and a manufacturing method thereof, wherein the 3D NAND electrically connects a first metal part in a metal layer with a first semiconductor substrate through the first metal part, and electrically connects a second metal part in the metal layer with a conducting layer in a through hole through the second metal part, wherein a capacitor is formed among the conducting layer, a dielectric layer and the first semiconductor substrate in the through hole, so that the capacitor is positioned in the substrate and occupies an idle area of the first semiconductor substrate of the 3D NAND, and therefore the occupation of a large substrate area is avoided. Meanwhile, the first metal part is used as a first polar plate, the second metal part is used as a second polar plate, and an MOM capacitor can be formed between the first metal part and the second metal part, so that the capacity of the capacitor formed among the first metal part, the first semiconductor substrate, the dielectric layer, the conductive layer and the second metal part is increased.)

1. A3D NAND, comprising:

the semiconductor device includes a first semiconductor substrate including a first surface and a second surface oppositely arranged;

an insulating ring extending through the first semiconductor substrate;

a plurality of through holes which are positioned in the first semiconductor substrate surrounded by the insulating ring and penetrate through the first semiconductor substrate;

the dielectric layer is positioned on the inner wall of the through hole, and the conducting layer is filled in the through hole;

the metal layer is positioned on one side, away from the second surface, of the first surface of the first semiconductor substrate and comprises a first metal part and a second metal part which are mutually insulated;

a first contact portion electrically connecting the first semiconductor substrate and the first metal portion;

a second contact portion electrically connecting the conductive layer and the second metal portion;

the first metal part is a first polar plate, and the second metal part is a second polar plate.

2. The 3D NAND as claimed in claim 1 wherein the first metal portion and the second metal portion are metal layers at the same level.

3. The 3D NAND of claim 2 wherein the first and second metal portions are both comb-like structures.

4. The 3D NAND as claimed in claim 3 wherein the comb teeth of the first metal part and the comb teeth of the second metal part are arranged to cross each other.

5. The 3D NAND as claimed in claim 1 wherein the metal layers comprise a plurality of metal layers insulated from each other and disposed one above the other.

6. The 3D NAND of claim 5 wherein the projections of multiple metal layers onto the first semiconductor substrate overlap.

7. The 3D NAND of claim 6 wherein first metal portions of adjacent metal layers that overlap in projection on the first semiconductor substrate are electrically connected to each other; and second metal parts which are projected and overlapped on the first semiconductor substrate in the adjacent metal layers are electrically connected with each other.

8. The 3D NAND as claimed in any one of claims 1 to 7 wherein the first semiconductor substrate comprises a first region and a second region, the first region having a memory device formed on a first surface thereof, the insulating ring being formed in the second region.

9. The 3D NAND of claim 8 wherein the memory device comprises a stack of layers of alternating gate and insulating layers on the first surface, a string of memory cells through the stack of layers, and a memory cell interconnect structure in a dielectric layer over the string of memory cells, the string of memory cells comprising a tunnel hole through the stack of layers and a tunnel layer, a charge storage layer, a barrier layer, and a channel layer sequentially formed on sidewalls of the tunnel hole.

10. The 3D NAND of claim 9 further comprising a second semiconductor substrate having MOS devices and an interconnect structure of MOS devices formed thereon;

the first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed;

the memory unit interconnection structure and the first lead-out structure are respectively electrically connected with the interconnection structure of the MOS device.

11. A3D NAND manufacturing method is characterized by comprising the following steps:

providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a first surface and a second surface which are oppositely arranged;

manufacturing and forming a metal layer on one side of the first surface of the first semiconductor substrate, which is far away from the second surface, wherein the metal layer comprises a first metal part and a second metal part which are insulated from each other, and the first metal part is electrically connected with the first semiconductor substrate;

thinning the second surface of the first semiconductor substrate;

forming an insulating ring from the second surface through the first semiconductor substrate;

forming a through hole penetrating through the first semiconductor substrate in a region corresponding to the second metal portion on the first semiconductor substrate surrounded by the insulating ring;

forming a dielectric layer on the inner wall of the through hole;

and filling the through hole with a conductive material to form a conductive layer, wherein the conductive layer is electrically connected with the second metal part.

Technical Field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a 3D NAND and a manufacturing method thereof.

Background

3D NAND is a flash memory technology that employs vertically stacked memory cells to increase capacity for higher storage density.

As 3D NAND technology moves toward high density and high capacity, particularly from 64-128 layer schemes, the number of devices and the number of traces increases significantly. Conventional MOS capacitors or MOM capacitors typically require large chip area or metal trace area at the back end stage, and large area MOS capacitance can cause Time Dependent Dielectric Breakdown (TDDB) problems.

In 3D NAND technology, the memory cell is programmed and erased at high voltages, so a capacitor is required to implement the voltage boosting. Typically, MOS capacitors, MOM capacitors, or poly-to-poly capacitors are used in 3D NAND chip circuits. A large number of capacitor devices are needed in the peripheral circuit to boost voltage, and the traditional capacitor usually needs to occupy a larger silicon chip or metal wiring area, which is not beneficial to improving the integration level of the flash memory unit.

Disclosure of Invention

In view of this, the present invention provides a 3D NAND and a method for fabricating the same, so as to solve the problem in the prior art that a capacitor occupies a large area as the storage density of the 3D NAND increases, thereby improving the integration level of the flash memory cell.

In order to achieve the purpose, the invention provides the following technical scheme:

a 3D NAND, comprising:

the semiconductor device includes a first semiconductor substrate including a first surface and a second surface oppositely arranged;

an insulating ring extending through the first semiconductor substrate;

a plurality of through holes which are positioned in the first semiconductor substrate surrounded by the insulating ring and penetrate through the first semiconductor substrate;

the dielectric layer is positioned on the inner wall of the through hole, and the conducting layer is filled in the through hole;

the metal layer is positioned on one side, away from the second surface, of the first surface of the first semiconductor substrate and comprises a first metal part and a second metal part which are mutually insulated;

a first contact portion electrically connecting the first semiconductor substrate and the first metal portion;

a second contact portion electrically connecting the conductive layer and the second metal portion;

the first metal part is a first polar plate, and the second metal part is a second polar plate.

Preferably, the first metal part and the second metal part are metal layers located on the same layer.

Preferably, the first metal part and the second metal part are both comb-shaped structures.

Preferably, the comb teeth of the first metal part and the comb teeth of the second metal part are arranged to cross each other.

Preferably, the metal layer includes a plurality of metal layers insulated from each other and stacked.

Preferably, projections of the multiple metal layers on the first semiconductor substrate overlap.

Preferably, first metal parts which are projected and overlapped on the first semiconductor substrate in adjacent metal layers are electrically connected with each other; and second metal parts which are projected and overlapped on the first semiconductor substrate in the adjacent metal layers are electrically connected with each other.

Preferably, the first semiconductor substrate includes a first region and a second region, the first region having a memory device formed on a first surface thereof, and the insulating ring is formed on the second region.

Preferably, the memory device includes a stack layer in which gate layers and insulating layers are alternately stacked on the first surface, a memory cell string penetrating through the stack layer, and a memory cell interconnection structure in a dielectric layer above the memory cell string, and the memory cell string includes a channel hole penetrating through the stack layer and a tunneling layer, a charge storage layer, a blocking layer, and a channel layer sequentially formed on sidewalls of the channel hole.

Preferably, the semiconductor device further comprises a second semiconductor substrate, wherein an MOS device and an interconnection structure of the MOS device are formed on the second semiconductor substrate;

the first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed;

the memory unit interconnection structure and the first lead-out structure are respectively electrically connected with the interconnection structure of the MOS device.

The invention also provides a 3D NAND manufacturing method, which comprises the following steps:

providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a first surface and a second surface which are oppositely arranged;

manufacturing and forming a metal layer on one side of the first surface of the first semiconductor substrate, which is far away from the second surface, wherein the metal layer comprises a first metal part and a second metal part which are insulated from each other, and the first metal part is electrically connected with the first semiconductor substrate;

thinning the second surface of the first semiconductor substrate;

forming an insulating ring from the second surface through the first semiconductor substrate;

forming a through hole penetrating through the first semiconductor substrate in a region corresponding to the second metal portion on the first semiconductor substrate surrounded by the insulating ring;

forming a dielectric layer on the inner wall of the through hole;

and filling the through hole with a conductive material to form a conductive layer, wherein the conductive layer is electrically connected with the second metal part.

According to the technical scheme, in the 3D NAND provided by the invention, the first metal portion in the metal layer is electrically connected with the first semiconductor substrate through the first metal portion, and the second metal portion in the metal layer is electrically connected with the conductive layer in the through hole through the second metal portion, wherein a capacitor is formed among the conductive layer, the dielectric layer and the first semiconductor substrate in the through hole, so that the capacitor is located in the substrate and occupies an idle area of the first semiconductor substrate of the 3D NAND, thereby avoiding occupying a large substrate area. Meanwhile, the first metal part is used as a first polar plate, the second metal part is used as a second polar plate, and an MOM capacitor can be formed between the first metal part and the second metal part, so that the capacity of the capacitor formed among the first metal part, the first semiconductor substrate, the dielectric layer, the conductive layer and the second metal part is increased.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a top view structure of a 3D NAND provided in an embodiment of the present invention;

FIG. 2 is a cross-sectional view of the 3D NAND along line AA' in FIG. 1 according to the embodiment of the present invention;

FIG. 3 is a schematic diagram of another 3D NAND structure according to an embodiment of the present invention;

fig. 4 is a flowchart of a 3D NAND manufacturing method according to an embodiment of the invention.

Detailed Description

As described in the background art, MOS (metal oxide Semiconductor) devices of a peripheral circuit of a 3D NAND memory device are formed on different substrates and then connected together by a packaging technology, the peripheral circuit is composed of an HVMOS device and an LVMOS device, the peripheral circuit is used for operating a memory cell, and the operation of the 3D NAND memory cell is a high voltage, so that a large number of capacitor devices are required in the peripheral circuit to boost the voltage, and a conventional capacitor structure generally needs to occupy a large area of a silicon chip or a metal trace, which is not favorable for improving the integration level of the chip.

Based on this, the present invention provides a 3D NAND comprising:

the semiconductor device includes a first semiconductor substrate including a first surface and a second surface oppositely arranged;

an insulating ring extending through the first semiconductor substrate;

a plurality of through holes which are positioned in the first semiconductor substrate surrounded by the insulating ring and penetrate through the first semiconductor substrate;

the dielectric layer is positioned on the inner wall of the through hole, and the conducting layer is filled in the through hole;

the metal layer is positioned on one side, away from the second surface, of the first surface of the first semiconductor substrate and comprises a first metal part and a second metal part which are mutually insulated;

a first contact portion electrically connecting the first semiconductor substrate and the first metal portion;

a second contact portion electrically connecting the conductive layer and the second metal portion;

the first metal part is a first polar plate, and the second metal part is a second polar plate.

In the 3D NAND provided by the invention, the first metal part in the metal layer is electrically connected with the first semiconductor substrate through the first metal part, and the second metal part in the metal layer is electrically connected with the conducting layer in the through hole through the second metal part, wherein a capacitor is formed among the conducting layer in the through hole, the dielectric layer and the first semiconductor substrate, so that the capacitor is positioned in the substrate and occupies an idle area of the first semiconductor substrate of the 3D NAND, thereby avoiding occupying a larger substrate area. Meanwhile, the first metal part is used as a first polar plate, the second metal part is used as a second polar plate, and an MOM capacitor can be formed between the first metal part and the second metal part, so that the capacity of the capacitor formed among the first metal part, the first semiconductor substrate, the dielectric layer, the conductive layer and the second metal part is increased.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Please refer to fig. 1 and fig. 2, wherein fig. 1 is a schematic diagram of a top view structure of a 3D NAND according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of the 3D NAND along line AA' in FIG. 1 according to the embodiment of the present invention; the 3D NAND provided by the embodiment of the present invention includes:

a first semiconductor substrate 1 including a first surface and a second surface which are oppositely disposed;

an insulating ring 2 penetrating the first semiconductor substrate 1;

a plurality of through holes which are positioned in the first semiconductor substrate 1 surrounded by the insulating ring 2 and penetrate through the first semiconductor substrate 1;

a dielectric layer 6 positioned on the inner wall of the through hole and a conductive layer 5 filling the through hole;

a metal layer 3 located on a side of the first surface of the first semiconductor substrate 1 facing away from the second surface, the metal layer including a first metal portion 31 and a second metal portion 32 insulated from each other;

a first contact 41 electrically connecting the first semiconductor substrate 1 and the first metal part 31;

a second contact portion 42 electrically connecting the conductive layer 5 and the second metal portion 32;

the first metal part 31 is a first plate, and the second metal part 32 is a second plate.

In the embodiment of the present application, an insulating ring 2 penetrating through a first semiconductor substrate 1 is formed in the first semiconductor substrate 1, the insulating ring 2 isolates the first semiconductor substrate 1 from surrounding substrates, the size of a capacitor structure is defined by the insulating ring 2, the first semiconductor substrate 1 is connected to a first plate 31 through a first contact portion 41, a dielectric layer 6 is formed on a sidewall of a through hole and filled with a conductive layer 5, and further connected to a second plate 32 through a second contact portion 42, and the dielectric layer 6 in the through hole is an insulating layer between the plates of two capacitor structures.

In the embodiment of the invention, the capacitor structure is formed by penetrating through the first semiconductor substrate, the polar plate adopts the metal layer carried in the 3D NAND structure, and the MOM capacitor is also formed between the first metal part and the second metal part of the metal layer, so that the capacitor has larger capacity, the capacitor structure with larger capacity can be formed on smaller chip area, and the integration level of the chip is effectively improved.

The insulating ring 2 is made of an insulating material capable of isolating different portions of the substrate, and the material of the insulating ring 2 may be one or more dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating ring 2 is a closed ring structure, and the insulating ring 2 plays a role of insulating isolation, so that the substrate inside the ring is isolated from the substrate outside the ring. The shape of the insulating ring 2, that is, the shape of the area where the capacitor structure is located, may be set according to specific needs, and the shape of the insulating ring 2 may be, for example, a square or a circle, where the square includes a square and a rectangle, and in this specific example, the shape of the insulating ring is a square, as shown in fig. 1.

In the embodiment of the present application, the first semiconductor substrate 1 In the insulating ring 2 serves As a conductive structure of the capacitor structure, and according to requirements, the first semiconductor substrate 1 may have a doping, such As an N-type or P-type doping, and the doping may be a doping that the substrate itself has, such As a P-type substrate, or a doping obtained by a doping process, where the N-type doped doping ions may be, for example, N, P, As, S, and the like, and the P-type doped doping particles may be, for example, B, Al, Ga, In, and the like.

The through holes are formed in the first semiconductor substrate 1, that is, the first semiconductor substrate in the insulating ring 2, and the number, arrangement and shape of the through holes may be set as required. The shape of the through hole can be round, square or other shapes, and the square comprises a square and a rectangle.

A dielectric layer 6 is formed on the sidewall of the through hole, the dielectric layer 6 is an insulating material layer between the plates of the capacitor structure, the dielectric layer 6 may be a single-layer or multi-layer structure, the material of the dielectric layer 6 may be, for example, one or more of silicon oxide or other high-k dielectric materials, the thickness of the dielectric layer 6 may be 100-.

When the first semiconductor substrate is a Si substrate, the through-hole formed in the first semiconductor substrate may be referred to as a through-silicon contact (TSC), which is widely used in the semiconductor industry. The TSC is a vertical electrical connection that passes completely through the silicon wafer or die. TSC technology is important in creating 3D packages and 3D integrated circuits. The TSC provides interconnection of vertically aligned electronic devices by internal wiring that significantly reduces the complexity and overall size of the multi-chip electronic circuit. TSC technology provides higher interconnect and device density and shorter connection lengths compared to conventional packaging techniques. When used in 3D NAND, the TSC enables electrical connection between the array circuit wafer of memory cells and the peripheral circuit wafer including the control circuitry.

In the 3D NAND manufacturing process provided in this embodiment, a part of the free area of the first semiconductor substrate is isolated by using an insulating ring and used for manufacturing the TSC, and in addition, the M1 metal layer and/or the M2 metal layer in the back-end manufacturing process are used to manufacture the first metal part and the second metal part, without introducing a particularly complicated manufacturing process.

Based on this, in the embodiment of the present invention, it is not limited whether the first metal portion and the second metal portion are located in the same metal layer, and it should be noted that when the first metal portion and the second metal portion are located in the same metal layer, MOM capacitance formed between them is relatively large. When the first metal part and the second metal part are located in different metal layers, the facing area between the first metal part and the second metal part is smaller, and the formed MOM capacitance is smaller, so that in order to increase the capacitance to the maximum extent, in an optional manner, in the embodiment of the invention, the first metal part and the second metal part are metal layers located in the same layer.

In the embodiment of the present invention, the shapes of the first metal portion and the second metal portion are not limited as long as the MOM capacitor is formed therebetween and the capacitance of the capacitor formed between the first semiconductor substrate and the conductive layer is increased. In order to further increase the MOM capacitance, in this embodiment, optionally, the first metal portion and the second metal portion are both comb-shaped structures. As shown in fig. 1, each of the first metal parts 31 and each of the second metal parts 32 are comb-shaped structures, and the comb teeth of the first metal parts 31 and the comb teeth of the second metal parts 32 are arranged to intersect with each other. Thus, the peripheries of the first metal portions 31 and the second metal portions 32 are the second metal portions 32, and the peripheries of the second metal portions 32 and the first metal portions 31 are the first metal portions 31, so that MOM capacitors can be formed therebetween.

In the embodiment of the present invention, an MOM capacitor existing between multiple metal layers may also be used, as shown in fig. 3, which is another schematic diagram of a 3D NAND structure provided in the embodiment of the present invention; the metal layers comprise a plurality of metal layers (3 and 3') which are insulated from each other and are arranged in a stacked mode, projections of the plurality of metal layers on the first semiconductor substrate are overlapped, and first metal parts which are projected and overlapped on the first semiconductor substrate in adjacent metal layers are electrically connected with each other; the second metal parts of the adjacent metal layers, which are projected and overlapped on the first semiconductor substrate, are electrically connected with each other, and the adjacent metal layers are electrically connected with each other through a contact part 4'.

Thus, an MOM capacitor can be formed between the first metal part and the second metal part between each metal layer, and the capacitance capacity of the 3D NAND structure is further increased. The capacitor structure only occupies the volume in the vertical direction of the chip, and the area of the chip is not increased. In addition, the spare area of the semiconductor substrate of the chip and the multilayer metal layer of the chip are used, so that the manufacturing cost is not increased.

It should be noted that the above description only describes the structure of the first semiconductor substrate inside the insulating ring, and in practical applications, the first semiconductor substrate includes a first region and a second region, the first region has a memory device formed on a first surface thereof, and the insulating ring is formed in the second region. The second area is an idle area of the semiconductor substrate, and the first area is a normal 3D NAND memory cell area.

The memory device comprises a stack layer formed by alternately stacking a gate layer and an insulating layer on the first surface, a memory cell string penetrating through the stack layer, and a memory cell interconnection structure in a dielectric layer above the memory cell string, wherein the memory cell string comprises a channel hole penetrating through the stack layer and a tunneling layer, a charge storage layer, a blocking layer and a channel layer sequentially formed on the side wall of the channel hole.

In addition, the 3D NAND may further include a second semiconductor substrate on which the MOS device and an interconnection structure of the MOS device are formed; the first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed; the memory unit interconnection structure and the first lead-out structure are respectively electrically connected with the interconnection structure of the MOS device.

In the 3D NAND provided by the invention, the first metal part in the metal layer is electrically connected with the first semiconductor substrate through the first metal part, and the second metal part in the metal layer is electrically connected with the conducting layer in the through hole through the second metal part, wherein a capacitor is formed among the conducting layer in the through hole, the dielectric layer and the first semiconductor substrate, so that the capacitor is positioned in the substrate and occupies an idle area of the first semiconductor substrate of the 3D NAND, thereby avoiding occupying a larger substrate area. Meanwhile, the first metal part is used as a first polar plate, the second metal part is used as a second polar plate, and an MOM capacitor can be formed between the first metal part and the second metal part, so that the capacity of the capacitor formed among the first metal part, the first semiconductor substrate, the dielectric layer, the conductive layer and the second metal part is increased.

The embodiment of the present invention further provides a 3D NAND manufacturing method, please refer to fig. 4, where the 3D NAND manufacturing method includes:

s101: providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a first surface and a second surface which are oppositely arranged;

s102: manufacturing and forming a metal layer on one side of the first surface of the first semiconductor substrate, which is far away from the second surface, wherein the metal layer comprises a first metal part and a second metal part which are insulated from each other, and the first metal part is electrically connected with the first semiconductor substrate;

s103: thinning the second surface of the first semiconductor substrate;

s104: forming an insulating ring from the second surface through the first semiconductor substrate;

s105: forming a through hole penetrating through the first semiconductor substrate in a region corresponding to the second metal portion on the first semiconductor substrate surrounded by the insulating ring;

s106: forming a dielectric layer on the inner wall of the through hole;

s107: and filling the through hole with a conductive material to form a conductive layer, wherein the conductive layer is electrically connected with the second metal part.

In the 3D NAND structure provided by the embodiment of the invention, in the current CMOS architecture, in the process of manufacturing a metal layer on a wafer, the metal layer is connected to a conductive layer of the TSC and the semiconductor substrate, and the first metal portions and the second metal portions in the metal layer are alternately arranged in a crossed manner to form the MOM capacitor. And then, thinning the back of the wafer, forming a circle of insulating ring outside the capacitor through an etching process, and separating the semiconductor substrate in the insulating ring from the external semiconductor substrate to avoid mutual interference with the external storage unit.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.