阅读说明：本技术 三维层叠式半导体存储器件 (Three-dimensional stacked semiconductor memory device ) 是由 金圣贤 于 2019-04-08 设计创作，主要内容包括：本发明公开了一种三维(3D)层叠式半导体存储器件。该半导体存储器件可以包括：多个行线,其在第一水平方向上彼此平行地延伸；多个列线叠层,其在垂直于第一水平方向的第二水平方向上彼此平行地延伸,其中多个列线叠层中的每个列线叠层在竖直方向上包括彼此平行地延伸的多个列线；以及多个单元柱,其竖直穿通列线叠层的列线,多个单元柱中的每个单元柱具有第一端和第二端,其中,多个单元柱的第一端电耦接到多个行线,以及多个单元柱的第二端被浮置。每个单元柱包括核和可变电阻存储层。(The invention discloses a three-dimensional (3D) stacked semiconductor memory device. The semiconductor memory device may include: a plurality of row lines extending parallel to each other in a first horizontal direction; a plurality of column line stacks extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extending parallel to each other in a vertical direction; and a plurality of cell pillars vertically penetrating the column lines of the column line stack, each of the plurality of cell pillars having a first end and a second end, wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, and the second ends of the plurality of cell pillars are floated. Each cell pillar includes a core and a variable resistance storage layer.)

1. A semiconductor memory device comprising:

a plurality of row lines extending parallel to each other in a first horizontal direction;

a plurality of column line stacks extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks comprises a plurality of column lines extending parallel to each other in a vertical direction; and

a plurality of cell pillars vertically penetrating the column line of the column line stack, each cell pillar of the plurality of cell pillars having a first end and a second end,

wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, an

Wherein the second ends of the plurality of cell pillars are floated.

2. The semiconductor memory device of claim 1, wherein the second ends of the plurality of cell pillars protrude from a lowermost column line of the plurality of column line stacks.

3. The semiconductor memory device of claim 1, wherein each of the plurality of cell pillars comprises:

a central core; and

a storage layer surrounding the central core.

4. The semiconductor memory device of claim 3, wherein the central core comprises at least one of a metal, a metal compound, and a metal silicide.

5. The semiconductor memory device of claim 4, wherein the central core comprises at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

6. The semiconductor memory device of claim 3, wherein the central core is directly connected to one of the plurality of row lines.

7. The semiconductor memory device according to claim 3, wherein the memory layer includes at least three variable resistance layers, and the variable resistance layers have different characteristics of at least one or more of an energy band gap, a chemical potential, an ion mobility, a conductive filament formation threshold voltage, a phase transition threshold voltage, and an atom transfer threshold voltage.

8. The semiconductor memory device according to claim 7, wherein each of the variable resistance layers comprises at least one of hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, and titanium oxide.

9. The semiconductor memory device of claim 1, wherein each of the plurality of column lines comprises at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

10. The semiconductor memory device of claim 1, wherein the plurality of row lines are buried in a substrate.

11. A semiconductor memory device comprising:

word lines extending in a first horizontal direction;

a bit line stack extending in a second horizontal direction perpendicular to the first horizontal direction; and

a cell pillar extending from the word line to vertically pass through the bit line stack,

wherein a first end of the cell pillar is electrically coupled to the word line, an

The second end of the cell pillar is floated.

12. The semiconductor memory device according to claim 11, wherein the bit line stack includes a plurality of bit lines which are stacked in a vertical direction and extend parallel to each other in the second horizontal direction.

13. The semiconductor memory device of claim 12, wherein the bit line comprises at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

14. The semiconductor memory device of claim 11, wherein the second terminal protrudes from a lowermost end of the bitline stack.

15. The semiconductor memory device of claim 11, wherein the cell pillar includes a central core and a memory layer surrounding the central core.

16. The semiconductor memory device according to claim 15, wherein the memory layer includes at least three variable resistance layers, and the variable resistance layers have different characteristics of at least one of an energy band gap, a chemical potential, an ion mobility, a conductive filament formation threshold voltage, a phase transition threshold voltage, and an atom transfer threshold voltage.

17. The semiconductor memory device according to claim 16, wherein the variable resistance layer comprises at least one of hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, and titanium oxide.

18. The semiconductor memory device of claim 11, wherein the word line comprises at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

19. A semiconductor memory device comprising:

a substrate;

a lower insulating layer disposed over the substrate;

a plurality of bit lines and a plurality of interlayer dielectric layers alternately stacked over the lower insulating layer, wherein the plurality of bit lines extend parallel to each other in a first horizontal direction;

an upper insulating layer disposed over the plurality of bit lines;

word lines disposed over the upper insulating layer and extending in a second horizontal direction perpendicular to the first horizontal direction; and

vertical pillars vertically extending from the word lines through the upper insulating layer, the plurality of interlayer dielectric layers, and the plurality of bit lines,

wherein the vertical column comprises a conductive core and at least three variable resistance layers surrounding the conductive core,

the upper end of the vertical pillar is directly connected to the word line; and

the lower end of the vertical pillar extends into the lower insulating layer without contacting the substrate.

20. The semiconductor memory device according to claim 19, wherein the variable resistance layer comprises at least one of hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide, and wherein the variable resistance layer has at least one of different characteristics of energy band gap, chemical potential, ion mobility, conductive filament formation threshold voltage, magnetization threshold voltage, phase transition threshold voltage, and atom transfer threshold voltage.

Technical Field

Exemplary embodiments of the present disclosure relate to a three-dimensional (3D) stacked semiconductor memory device.

Background

Recently, as part of next-generation semiconductor memory technologies, 3D stacked semiconductor memory technologies and cross-point variable resistance memory technologies have received much attention. In addition, there has been much attention paid to a neuromorphic computing technique (neuromorphic computing technology) which simulates the human brain for an artificial intelligence technique or the like. Neuromorphic devices based on neuromorphic techniques include a plurality of pre-synaptic neurons, a plurality of post-synaptic neurons, and a plurality of synapses. The neuromorphic device may have various resistance levels according to the learning state, and may output various voltages or currents according to the resistance levels.

Disclosure of Invention

Embodiments of the present disclosure include semiconductor memory devices and neuromorphic devices having multiple variable resistance layers to achieve multiple resistance levels.

Embodiments of the present disclosure include cross-point semiconductor memory devices and neuromorphic devices.

Embodiments of the present disclosure include a 3D stacked semiconductor memory device and a neuromorphic device.

Embodiments of the present disclosure include cross-point 3D stacked semiconductor memory devices and neuromorphic devices having multiple variable resistance layers.

In one embodiment, a semiconductor memory device may include: a plurality of row lines extending parallel to each other in a first horizontal direction; a plurality of column line stacks extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extending parallel to each other in a vertical direction; and a plurality of cell pillars vertically penetrating the column lines of the column line stack, each of the plurality of cell pillars having a first end and a second end. The first ends of the plurality of cell pillars may be electrically coupled to a plurality of row lines. The second ends of the plurality of cell pillars may be floated.

The second ends of the plurality of cell pillars may protrude from a lowermost column line of the plurality of column line stacks.

Each of the plurality of unit pillars may include: a central core; and a storage layer surrounding the central core.

The central core may include at least one of a metal, a metal compound, and a metal silicide.

The central core may include at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

The central core may be directly connected to one of the plurality of row lines.

The memory layer may comprise at least three resistive layers. The variable resistance layer may have at least one of different characteristics of an energy band gap, a chemical potential, an ion mobility, a conductive filament formation threshold voltage, a phase transition threshold voltage, and an atom transfer threshold voltage.

Each variable resistance layer may include at least one of a high dielectric constant (high-k) oxide or a metal oxide containing oxygen vacancies, including hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, and titanium oxide.

Each column line of the plurality of column lines may include at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

A plurality of row lines may be buried in the substrate.

In one embodiment, a semiconductor memory device may include: word lines extending in a first horizontal direction; a bit line stack extending in a second horizontal direction perpendicular to the first horizontal direction; and a cell pillar extending from the word line so as to vertically penetrate through the bit line stack, wherein a first end of the cell pillar is electrically coupled to the word line and a second end of the cell pillar is floated.

The bit line stack may include a plurality of bit lines stacked in a vertical direction and extending parallel to each other in a second horizontal direction.

The bit line may include at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

The second end may extend from a lowermost end of the column line stack.

The cell pillars may include a central core and a storage layer surrounding the central core.

The memory layer may include at least three variable resistance layers. The variable resistance layer may have at least one of different characteristics of an energy band gap, a chemical potential, an ion mobility, a conductive filament formation threshold voltage, a phase transition threshold voltage, and an atom transfer threshold voltage.

The variable resistance layer may include at least one of a high-k oxide or a metal oxide containing oxygen vacancies, including hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, and titanium oxide.

The word line may include at least one of a metal, a metal compound, a metal silicide, and ion-doped silicon.

In one embodiment, a semiconductor memory device may include: a substrate; a lower insulating layer disposed over the substrate; a plurality of bit lines and a plurality of interlayer dielectric layers alternately stacked over the lower insulating layer, wherein the plurality of bit lines extend parallel to each other in a first horizontal direction; an upper insulating layer disposed over the plurality of bit lines; word lines disposed over the upper insulating layer and extending in a second horizontal direction perpendicular to the first horizontal direction; and a vertical pillar vertically extending from the word line through the upper insulating layer, the plurality of interlayer dielectric layers, and the plurality of bit lines, wherein the vertical pillar includes a conductive core and three or more variable resistance layers surrounding the core, and an upper end of the vertical pillar is directly connected to the word line; and the lower end of the vertical pillar extends into the lower insulating layer without contacting the substrate.

The variable resistance layer may include a high-k oxide containing oxygen vacancies or at least one of various metal oxides including hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide. The variable resistance layer may have at least one of different characteristics among a band gap, a chemical potential, an ion mobility, a conductive filament formation threshold voltage, a magnetization threshold voltage, a phase transition threshold voltage, and an atom transfer threshold voltage.

Drawings

Fig. 1 is a block diagram schematically illustrating a cell array of a semiconductor memory device according to an embodiment.

Fig. 2 is a 3D perspective view schematically illustrating a cell array of a semiconductor memory device according to an embodiment.

Fig. 3A is a schematic cross-sectional view of the semiconductor memory device taken along line I-I' in fig. 2.

Fig. 3B is a schematic cross-sectional view of the semiconductor memory device taken along line II-II' in fig. 2.

Fig. 4A is an expanded view of the region "a" in fig. 3A.

Fig. 4B is a schematic cross-sectional view taken along line III-III' in fig. 4A.

Fig. 5A and 5B schematically illustrate the principle of a program operation of a semiconductor memory device.

Fig. 6 is a 3D perspective view schematically illustrating a cell array of a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 7A is a schematic cross-sectional view of the semiconductor memory device taken along line IV-IV' in fig. 6.

Fig. 7B is a schematic cross-sectional view of the semiconductor memory device taken along line V-V' in fig. 6.

Fig. 8A is a schematic cross-sectional view of the semiconductor memory device taken along line IV-IV' in fig. 6.

Fig. 8B is a schematic cross-sectional view of the semiconductor memory device taken along line V-V' in fig. 6.

Fig. 9 is a block diagram schematically illustrating a cell array of a semiconductor memory device according to an embodiment.

Fig. 10A and 10B are 3D perspective views schematically illustrating a cell array of a semiconductor memory device according to an embodiment.

Fig. 11 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment.

Fig. 12 is a block diagram schematically illustrating a pattern recognition system according to an embodiment.

Detailed Description

Advantages and features of the present disclosure and methods for achieving the same will be apparent by reference to the following embodiments in conjunction with the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The present disclosure is to be limited only by the scope of the following claims.

Like reference numerals refer to like elements throughout the specification. Thus, although the same or similar reference numbers may not be mentioned or described in the corresponding figures, they may be described with reference to other figures. Further, although elements are not denoted by reference numerals, the elements may be described with reference to other drawings.

Fig. 1 is a block diagram conceptually illustrating a cell array 100 of a semiconductor memory device according to an embodiment.

Referring to fig. 1, a cell array 100 of a semiconductor memory device may include a row driver RD, a column driver CD, a plurality of row lines R1 through Rn, a plurality of column lines C1 through Cm, and a plurality of memory cells MC. A plurality of row lines R1 through Rn may extend parallel to each other in a row direction from the row driver RD, a plurality of column lines C1 through Cm may extend parallel to each other in a column direction from the column driver CD, and a plurality of memory cells MC may be arranged at respective intersections between the row lines R1 through Rn and the column lines C1 through Cm. A plurality of row lines R1 through Rn may correspond to word lines and a plurality of column lines C1 through Cm may correspond to bit lines. The plurality of memory cells MC may include a variable resistance layer. The plurality of memory cells MC may include a first electrode electrically coupled to a respective row line R1 through Rn and a second electrode electrically coupled to a respective column line C1 through Cm.

The cell array 100 may have a cross-point connection structure. The semiconductor memory device may include a variable resistance memory device such as a resistive random access memory (ReRAM), a phase change ram (pcram), or a conductive bridge ram (cbram). In the present embodiment, row lines R1 through Rn may correspond to word lines, and column lines C1 through Cm may correspond to bit lines.

In another embodiment, the cell array 100 of the semiconductor memory device may correspond to an array of synapses of a neuromorphic device. For example, row driver RD may correspond to pre-synaptic neurons of a neuromorphic device, column driver CD may correspond to post-synaptic neurons of a neuromorphic device, row lines R1-Rn may correspond to pre-synaptic lines of a neuromorphic device, column lines C1-Cm may correspond to post-synaptic lines of a neuromorphic device, and memory cells MC may correspond to synapses of a neuromorphic device.

Fig. 2 is a 3D perspective view schematically illustrating a cell array 100A of a semiconductor memory device according to an embodiment.

Referring to fig. 2, a cell array 100A of a semiconductor memory device may include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. Word lines 30 may extend parallel to each other in a first direction D1. The first direction D1 may correspond to a horizontal row direction. The bit line 40 may be configured as a plurality of bit line stacks 40S extending in a second direction D2. That is, each bit line stack 40S may have a plurality of bit lines 40. The second direction D2 may correspond to a horizontal column direction. A plurality of cell pillars P may extend in the third direction D3 and pass through the bit line 40. The third direction D3 may correspond to a substantially vertical direction. That is, the plurality of cell pillars P may have a cylindrical shape and may extend substantially perpendicularly from the word line 30. The plurality of cell pillars P may be directly electrically coupled to the word line 30. Since the cell pillars P vertically penetrate the bit line stacks 40S, one of the bit line stacks 40S may be electrically coupled to a plurality of cell pillars P.

Word line 30 may be disposed over bit line stack 40S and cell pillar P. The upper ends of the plurality of cell pillars P may be electrically coupled to the corresponding word lines 30, and the lower ends of the plurality of cell pillars P may protrude downward from the lowermost bit line 40 of the bit line stack 40S and float from the word lines 30 and the bit lines 40. That is, the lower ends of the plurality of unit pillars P are not necessarily coupled with other conductive members.

Fig. 3A is a schematic cross-sectional view of the semiconductor memory device taken along line I-I 'in fig. 2, and fig. 3B is a schematic cross-sectional view of the semiconductor memory device taken along line II-II' in fig. 2.

Referring to fig. 3A and 3B, a cell array 100A of the semiconductor memory device according to the present embodiment may include a lower insulating layer 20 disposed on a substrate 10, a bit line stack 40S stacked on the lower insulating layer 20, a cell pillar P, and a word line 30. Each bit line stack 40S may have a plurality of bit lines 40 extending parallel to the horizontal direction. A plurality of interlayer dielectric layers 25 may be interposed between the respective stacked bit lines 40. Accordingly, the bit lines 40 and the interlayer dielectric layers 25 may be alternately stacked over the substrate 10 and the lower insulating layer 20. Between the bit line stack 40S and the word line 30, an upper insulating layer 26 may be disposed.

Substrate 10 may comprise a bulk semiconductor wafer such as monocrystalline silicon or a semiconductor layer such as epitaxially grown monocrystalline silicon.

The lower insulating layer 20 may include silicon oxide, silicon nitride, or a combination thereof. The lower insulating layer 20 may electrically insulate the substrate 10 from the bit line 40 and electrically insulate the substrate 10 from the cell pillar P.

The plurality of cell pillars P may extend in a substantially vertical direction to vertically penetrate the bit lines 40. The upper end of the cell pillar P may be directly electrically coupled to the corresponding word line 30, and the lower end of the cell pillar P may float. That is, the lower ends of the cell pillars P may not be electrically and physically coupled with the substrate 10 or other conductive components. The cell pillars P may penetrate the upper insulating layer 26 and the interlayer dielectric layer 25, and partially protrude into the lower insulating layer 20. The lower ends of the plurality of cell pillars P may protrude downward from the lowermost bit line 40 of the bit line stack 40S.

The word line 30 may be arranged on the cell pillar P to be electrically coupled to the cell pillar P. Word lines 30 may extend in a substantially horizontal direction substantially perpendicular to bit lines 40. For example, word lines 30 may extend in a first horizontal direction, while bit lines 40 may extend in a second substantially horizontal direction that is substantially perpendicular to the first horizontal direction. Word line 30 may include a conductor. For example, word line 30 may include one of: metals such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al); metallic compounds, such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO)₂) (ii) a Metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or ion-doped silicon.

The bit line 40 may include a conductor. For example, the bit line 40 may include one of: metals such as W, Ru or iridium (Ir); metallic compounds, such as WN, TiN, TaN or RuO₂(ii) a Gold (Au)A silicide such as WSi, TiSi, NiSi or CoSi; or ion-doped silicon.

The plurality of interlayer dielectric layers 25 may include an insulating material such as silicon oxide or silicon nitride to electrically insulate the bit line 40. The upper insulating layer 26 may include an insulating material such as silicon oxide or silicon nitride to electrically insulate the bit line stack 40S and the word line 30 from each other.

Fig. 4A is an expanded view of the region "a" in fig. 3A, and fig. 4B is a cross-sectional view taken along the line III-III' in fig. 4A. Referring to fig. 4A and 4B, the cell pillars P may include a central core 35 and a storage layer 60 surrounding the core 35. A portion of the central core 35 and a portion of the memory layer 60 may form one memory cell MC. For example, the cell pillar P may include a plurality of stacked memory cells MC, and each memory cell MC may include a central core 35 and a memory layer 60 surrounding the central core 35.

The central core 35 may be directly electrically coupled to word line 30. The central core 35 may include a conductor. For example, the core 35 may include one of: metals such as W, Ru, Cu, or Al; metallic compounds, such as WN, TiN, TaN or RuO₂(ii) a Metal silicides such as WSi, TiSi, NiSi, or CoSi; or ion-doped silicon.

The memory layer 60 may include three or more layers, for example, first to third variable resistance layers 61 to 63. The first to third variable resistance layers 61 to 63 may have one or more different characteristics among energy band gap, chemical potential, ion mobility, conductive filament formation threshold voltage, phase transition threshold voltage, and atom transfer threshold voltage. For example, the first variable resistance layer 61 may have a maximum energy band gap, chemical potential, conductive filament formation threshold voltage, phase transition threshold voltage, or atomic transfer threshold voltage, and the third variable resistance layer 63 may have a minimum energy band gap, chemical potential, conductive filament formation threshold voltage, phase transition threshold voltage, or atomic transfer threshold voltage. In another example, the first variable resistance layer 61 may have the lowest ion mobility, and the third variable resistance layer 63 may have the highest ion mobility. The resistance of the first variable-resistance layer 61 may be the most difficult to change, and the resistance of the third variable-resistance layer 63 may be the least difficult to change among the three layers. For example, when the semiconductor memory device is a ReRAM or CBRAM, the conductive filaments may be most difficult to form in the first variable-resistance layer 61 and least difficult to form in the third variable-resistance layer 63. In other words, first variable resistance layer 61 may have the highest conductive filament formation threshold voltage, third variable resistance layer 63 may have the lowest conductive filament formation threshold voltage, and second variable resistance layer 62 may have a conductive filament formation threshold voltage falling between the other two layers.

The first to third variable-resistance layers 61 to 63 may include various metal oxides containing oxygen vacancies, high dielectric constant (high-k) oxides, or a combination thereof. The various metal oxides may include hafnium oxide (HfO)₂) Alumina (Al)₂O₃) Lanthanum oxide (La)₂O₃) Tantalum oxide (Ta)₂O₅) Silicon oxide (SiO)₂) And titanium oxide (TiO)₂)。

Fig. 5A and 5B illustrate the principle of a program operation of a semiconductor memory device. For example, three memory cells MC1 through MC3 and three bit lines 40_1 through 40_3 will be described.

Referring to fig. 5A and 5B, a word line program voltage Vwp may be applied to a word line 30 (i.e., a core 35) of the semiconductor memory device, a first bit line program voltage Vbp1 may be applied to a first bit line 40_1, a second bit line program voltage Vbp2 may be applied to a second bit line 40_2, and a third bit line program voltage Vbp3 may be applied to a third bit line 40_3, so as to program memory cells MC1 to MC3 to have different data values (e.g., different resistance levels) during a program operation of the semiconductor memory device.

The following description may be based on the following assumptions: the difference between the word line programming voltage Vwp and the first bit line programming voltage Vbp1 is the largest, while the difference between the word line programming voltage Vwp and the third bit line programming voltage Vbp3 is the smallest. That is, for the purpose of illustration, a relationship of (| Vwp-Vbp1| > | Vwp-Vbp2| > | Vwp-Vbp3|) is assumed. For example, when all of the program voltages Vwp, Vbpp1, Vbp2, and Vbp3 have positive values (+), the first bit line program voltage Vbp1 may have the lowest value, and the third bit line program voltage Vbp3 may have the highest value.

The first conductive wire F1 having the largest size may be formed in the first memory cell MC1 to which the largest voltage difference is applied, the third conductive wire F3 having the smallest size may be formed in the third memory cell MC3 to which the smallest voltage difference is applied, and the second conductive wire F2 having an intermediate size, which is a size or value falling between the highest size or value and the lowest size or value, may be formed in the second memory cell MC2 to which the intermediate voltage difference is applied. In the present embodiment, it has been assumed and described that the memory cells MC1 to MC3 are memory cells of ReRAM or CBRAM. When the memory cells MC1 through MC3 are memory cells of PCRAM, the conductive filaments F1 through F3 may correspond to a phase change region.

As described above, when the first variable resistance layer 61 has the highest energy band gap, chemical potential, conductive filament formation threshold voltage, phase transition threshold voltage or atomic transfer threshold voltage, and the lowest ion mobility, and when the third variable resistance layer 63 has the lowest energy band gap, chemical potential, conductive filament formation threshold voltage, phase transition threshold voltage or atomic transfer threshold voltage, and the highest ion mobility, the first to third variable resistance layers 61 to 63 may form conductive filaments having different sizes at the same word line program voltage. Specifically, the conductive filaments formed in the first variable resistance layer 61 having the highest threshold voltage may have the smallest size, and the conductive filaments formed in the third variable resistance layer 63 having the lowest threshold voltage may have the largest size. Accordingly, during a read operation of the semiconductor memory device, the first memory cell MC1 may have the lowest resistance value, and the third memory cell MC3 may have the highest resistance value, and the second memory cell MC2 may have an intermediate resistance value between the lowest resistance value and the highest resistance value.

Referring to fig. 5B, in another example, the first conductive filament F1 may include conductive filaments formed in the first to third variable resistance layers 61 to 63 in the first memory cell MC1 to which the maximum voltage difference is applied, the second conductive filament F2 may include conductive filaments formed in the second and third variable resistance layers 62 and 63 in the second memory cell MC2 to which the intermediate voltage difference is applied, and the third conductive filament F3 may include conductive filaments formed only in the third variable resistance layer 63 in the third memory cell MC3 to which the minimum voltage difference is applied. In the first variable resistance layer 61 of the second memory cell MC2 and in the first and second variable resistance layers 61 and 62 of the third memory cell MC3, in which conductive filaments are not formed, electron tunneling may occur according to a voltage difference between read voltages applied to the central core 35 (i.e., the word line 30) and the bit lines 40_1 to 40_ 3. Accordingly, during a read operation of the semiconductor memory device, the first memory cell MC1 may have the lowest resistance value, and the third memory cell MC3 may have the highest resistance value, and the second memory cell MC2 may have an intermediate resistance value between the lowest resistance value and the highest resistance value.

According to an embodiment, the memory cells MC 1-MC 3 may have variable resistance levels according to a voltage difference between the word line programming voltage Vwp and the bit line programming voltages Vbp 1-Vbp 3. For example, in the case of a neuromorphic device, the memory cells MC 1-MC 3 may have variable levels of learning depending on the voltage difference between the word line programming voltage Vwp and the bit line programming voltages Vbp 1-Vbp 3.

In the present embodiment, it has been described that the memory layer 60 includes three variable resistance layers 61 to 63. However, the memory layer 60 may include four or more variable resistance layers. That is, the memory layer 60 may have at least three variable resistance layers, or three or more variable resistance levels, to provide additional resistance levels.

Fig. 6 is a 3D perspective view schematically illustrating a cell array 100B of a semiconductor memory device according to an embodiment. Referring to fig. 6, a cell array 100B of the semiconductor memory device may include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. In comparison with the cell array 100A of the semiconductor memory device shown in fig. 2, a plurality of word lines 30 may be arranged under a plurality of bit lines 40 and a plurality of cell pillars P. That is, the lower end of the cell pillar P may be electrically coupled to the corresponding word line 30, and the upper end of the cell pillar P may float.

Fig. 7A is a schematic cross-sectional view of the semiconductor memory device taken along line IV-IV 'in fig. 6, and fig. 7B is a schematic cross-sectional view of the semiconductor memory device taken along line V-V' in fig. 6.

Referring to fig. 7A and 7B, a cell array 100B of the semiconductor memory device according to the present embodiment may include a lower insulating layer 20 disposed on a substrate 10, a word line 30 disposed on or in the lower insulating layer 20, a cell pillar P, and a bit line stack 40S disposed over the word line 30. Between the respective stacked bit lines 40, a plurality of interlayer dielectric layers 25 may be interposed, and an upper insulating layer 26 is disposed on the uppermost bit line 40. In contrast to the cell array 100A of the semiconductor memory device shown in fig. 3A and 3B, the word line 30 may be disposed under the cell pillar P and the bit line stack 40S. The word line 30 may be insulated from the substrate 10 by the lower insulating layer 20. That is, the lower end of the cell pillar P may be electrically coupled to the word line 30, and the upper end of the cell pillar P may float.

Fig. 6 can also be used to schematically illustrate a 3D perspective view of the cell array 100C. Fig. 8A is a schematic cross-sectional view of the semiconductor memory device in the cell array 100C taken along a line IV-IV 'in fig. 6, and fig. 8B is a schematic cross-sectional view of the semiconductor memory device in the cell array 100C taken along a line V-V' in fig. 6.

Referring to fig. 8A and 8B, a cell array 100C of a semiconductor memory device according to an embodiment may include a word line 30 buried in a substrate 10, a lower insulating layer 20 disposed on the substrate 10, a cell pillar P disposed on the word line 30, and a bit line stack 40S. Between the respective stacked bit lines 40, a plurality of interlayer dielectric layers 25 may be interposed, and an upper interlayer insulating layer 26 is disposed on the uppermost bit line 40. In contrast to the cell array 100A of the semiconductor memory device shown in fig. 3A and 3B, the word line 30 may be disposed under the cell pillar P and the bit line stack 40S. The word line 30 may be buried in the substrate 10. The word line 30 may be an ion doped region in the substrate 10 or a metal line buried in the substrate 10. The word line 30 may be electrically insulated from the bulk region of the substrate 10 by an insulating region 12 disposed in the substrate 10. The insulating region 12 may comprise an insulating material comprising silicon oxide or silicon nitride. In another embodiment, the insulating region 12 may reflect an N-type ion or P-type ion doped region for forming a depletion region with any one of the word line 30 and the substrate 10.

Fig. 9 is a block diagram conceptually illustrating a cell array 200 of a semiconductor memory device according to an embodiment. Referring to fig. 9, the cell array 200 of the semiconductor memory device may include a row driver RD, a plurality of column drivers CD-1 to CD-m, a plurality of row lines R1 to Rn, a plurality of column line groups CS-1 to CS-m, and a plurality of memory cells MC. The plurality of row lines R1 to Rn may extend parallel to each other in a row direction from the row driver RD, the plurality of column line groups CS-1 to CS-m may include a plurality of column lines C11 to CmM extending parallel to each other in a column direction from the plurality of column drivers CD-1 to CD-m, and the plurality of memory cells MC may be arranged at respective intersections between the row lines R1 to Rn and the column lines C11 to CmM. One of the column drivers CD-1 to CD-m and one of the column line sets CS-1 to CS-m may be connected to form one of a plurality of memory blocks B1 to Bm.

Fig. 10A and 10B are 3D perspective views schematically illustrating cell arrays 200A and 200B of a semiconductor memory device according to an embodiment.

Referring to fig. 10A and 10B, cell arrays 200A and 200B of the semiconductor memory device may each include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. Word lines 30 may extend parallel to each other in a first direction D1. The first direction D1 may indicate a horizontal row direction. The bit line stack 40S may include a plurality of bit lines 40 and may extend in a second direction D2. The second direction D2 may indicate a horizontal column direction. Each bit line stack 40S may be included in the memory cell block B. A plurality of cell pillars P may extend in the third direction D3 and pass through the bit line 40. The third direction D3 may indicate a substantially vertical direction.

Referring to fig. 10A, the word line 30 may be disposed over the bit line stack 40S and the cell pillar P. Referring to fig. 10B, the word line 30 may be disposed under the bit line stack 40S and the cell pillar P. The cell arrays 200A and 200B illustrated in fig. 10A and 10B can be further understood with reference to the description of fig. 3A, 3B, 4A, 4B, 7A, 7B, 8A, and 8B.

In fig. 9, 10A, and 10B, one of the word lines 30 and the plurality of bit lines 40 may be electrically coupled to each other through one of the cell pillars P. Referring back to fig. 4A and 4B, each cell pillar P may have a plurality of memory cells MC in the crossing region between the word line 30 and the bit line 40. Accordingly, a plurality of memory cells MC corresponding to the crossing region between one word line 30 and the bit line stack 40S can output a plurality of data through the plurality of bit lines 40. The one word line 30 may also be electrically coupled to a plurality of memory blocks B. When a plurality of memory blocks B are driven at different voltage levels, respectively, the cell arrays 200A and 200B may operate using only one memory block B or a plurality of selected memory blocks B. Accordingly, driving efficiency and speed of the semiconductor memory device may be improved, and a plurality of data levels may be realized.

Fig. 11 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment.

Referring to fig. 11, the semiconductor memory device according to the embodiment may include a circuit cell 15 disposed on a substrate 10, a lower insulating layer 20, a bit line 40, an interlayer dielectric layer 25, a cell pillar P vertically penetrating or extending through the bit line 40 and the interlayer dielectric layer 25, a word line 30 disposed on the cell pillar P, and a via plug 45 for electrically coupling the bit line 40 to the circuit cell 15, wherein the bit line 40 and the interlayer dielectric layer 25 are stacked over the lower insulating layer 20.

The circuit unit 15 may include a plurality of transistors. For example, the circuit unit 15 may include a logic circuit, a pre-synaptic circuit and/or a post-synaptic circuit. The via plug 45 may include a conductor. For example, the via plug 45 may include a metal such as W, Ru, Cu, or Al. In other embodiments, the via plug 45 may include a metal compound (such as WN, TiN, TaN, or RuO)₂) A metal silicide (such as WSi, TiSi, NiSi or CoSi) or ion-doped silicon.

An active region for electrically coupling the transistor to the via plug 45 may be disposed in the substrate 10. For example, ion doped regions may be created.

Since the word line 30, the bit line 40, and the cell pillar P are located above the circuit cell 15, the integration degree can be improved. In addition, the vertically arranged cell array and circuit unit 15 can reduce the electrical signal path, thereby improving the operation speed.

Figure 12 is a block diagram conceptually illustrating a pattern recognition system 900, according to an embodiment. For example, the pattern recognition system 900 may include one of a voice recognition system, an image recognition system, a code recognition system, a signal recognition system, or a system for recognizing various patterns.

Referring to fig. 12, the pattern recognition system 900 according to the present embodiment may include a CPU 910, a storage 920, a communication control 930, a network 940, an output 950, an input 960, an analog-to-digital converter (ADC)970, a neuromorphic device 980, and/or a bus 990. The CPU 910 may generate and transmit various signals for a learning process of the neuromorphic device 980, and perform various processes and functions for recognizing patterns such as voice and images according to an output from the neuromorphic device 980.

The CPU 910 may be connected to the memory device 920, the communication control device 930, the output device 950, the ADC 970, and the neuromorphic device 980 through the bus 990.

The memory device 920 may store various pieces of information that need to be stored in the pattern recognition system 900. The storage 920 may include one or more of volatile memory such as DRAM or SRAM, non-volatile memory such as PRAM, MRAM, ReRAM, or NAND flash memory, and various storage devices such as a Hard Disk Drive (HDD) and a Solid State Drive (SSD).

The communication control device 930 may send and/or receive data (such as recognized voice and images) to and/or from a communication control device of another system through the network 940.

The output device 950 may output data such as recognized voice and image in various ways. For example, the output devices 950 may include a speaker, a printer, a monitor, a display panel (display panel), a beam projector (beamprojector), a holographic camera, or other various output devices.

The input device 960 may include one or more of a microphone, a camera, a scanner, a touch pad (touch pad), a keyboard, a mouse pen, and various sensors.

The ADC 970 may convert analog data input from the input device 960 into digital data.

The neuromorphic device 980 may perform learning or recognition using the data output from the ADC 970 and output data corresponding to the recognized pattern. The neuromorphic device 980 may include one or more of the neuromorphic devices according to various embodiments.

The semiconductor memory device and the neuromorphic device according to the present embodiment can have a high integration level.

The semiconductor memory device and the neuromorphic device according to the present embodiment can have a high operation speed and low power consumption.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.