阅读说明：本技术 一种面向粗粒度可重构阵列上的路由增强调度方法及装置 (Routing enhancement scheduling method and device for coarse-grained reconfigurable array ) 是由 刘大江 母松 于 2021-06-21 设计创作，主要内容包括：本发明提出一种面向粗粒度可重构阵列上的路由增强调度方法及装置,其中,方法包括：分析增强数据流图DFG中每个算子的可扩展机动性范围根据可扩展机动性范围定义整数线性规划模型的变量,根据变量构建整数线性规划模型中的约束条件,其中,整数线性规划模型的变量包括二进制变量和整数变量；根据变量构建整数线性规划模型中的约束条件以及构建的线性评估函数,获取全局最优解；根据全局最优解生成携式设备供电的嵌入式系统的调度方案。本申请提出的方法增强了数据流图的路由能力,提升了循环流水的性能。(The invention provides a routing enhancement scheduling method and device for a coarse-grained reconfigurable array, wherein the method comprises the following steps: analyzing an extensible mobility scope for each operator in a DFG of an enhanced dataflow graph According to an extensible mobility range Defining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables; construction of constraints and constructs in integer linear programming models from variablesA global optimal solution is obtained through the established linear evaluation function; and generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution. The method provided by the application enhances the routing capability of the data flow graph and improves the performance of the circulating flow.)

1. A routing enhancement scheduling method oriented to a coarse-grained reconfigurable array is characterized by comprising the following steps:

analyzing an extensible mobility scope for each operator in a DFG of an enhanced dataflow graph

According to the extensible mobility scopeDefining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables;

constructing a constraint condition in the integer linear programming model and a constructed linear evaluation function according to the variables to obtain a global optimal solution;

and generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

2. The estimation method of claim 1, characterized in that the extensible mobility scope of each operator in the analysis enhanced dataflow graph, DFGThe method comprises the following steps:

predefining parameters of an operator, the parameters comprising: earliest scheduled time step S_nScheduling time step L at latest_nTime step of the latest route

Performing extensible mobility analysis on operator nodes according to the parameters to obtain extensible mobility scope of each operatorWherein the content of the first and second substances,

3. the estimation method according to claim 2, characterized in that the variables of the integer linear programming model are defined as follows:

x_n,i,j，i∈[S_n,L_n]，scheduling operator node n at time step i, inserting one PE routing node at time step j, wherein j is more than or equal to i, and in the case that j is i, the operator n is scheduled at time step i, and j is scheduled at time step i>Under the condition of i, the insertion of the PE routing node is later than the scheduling time step i of the operator n;

y_n,i,j，i∈[S_n,L_n]，wherein, the data value of the operator n in the time step i is stored in a memory by adding a storage node in the time step j;

z_n,i,j，i∈[S_n,L_n]，loading the data value of the operator n pre-stored in the memory at the time step i by adding a data loading node at the time step j;

n_pewherein, under the condition, the total number of operators with the same mode scheduling time step should be less than or equal to n_pe。

4. The estimation method according to claim 3, wherein the constraints in the integer linear programming model include:

an operator scheduling time step uniqueness constraint, wherein the operator scheduling time step uniqueness constraint is expressed as:

wherein R represents a set of all mobility operators;

a routing node exclusivity constraint, said routing node exclusivity constraint represented as:

a storage node and load node concurrency constraint, the storage node and load node concurrency constraint being expressed as:

PE and memory route exclusivity constraints expressed as:

a dependency constraint represented as:

wherein E represents a set formed by all long dependent edges in the original DFG;

a PE resource restriction constraint, the PE resource restriction constraint represented as:

a memory chunk resource limit constraint, the memory chunk resource limit constraint represented as:

finding all solutions under the same target value, wherein all solutions under the same target value are expressed as:

wherein the content of the first and second substances,andis a binary cut set obtained under the condition that the target value is S;

a boundary constraint represented as:

O>O_lb

wherein O represents a target value obtained by the current integer linear programming model, O_lbThe target values obtained from the last solution are indicated.

5. The estimation method according to claim 4, further comprising:

evaluating a route enhanced scheduling algorithm according to a first factor and a second factor, wherein the first factor uses a variable n_peModeled into an integer linear program, the second factor is represented as:

where α is the weighting factor of the memory routing node.

6. The estimation method according to claim 5, characterized in that the objective function of the global optimal solution is represented as:

wherein beta is equal to n_insThe upper bound of (c).

7. A routing enhancement scheduling device oriented to a coarse-grained reconfigurable array is characterized by comprising:

an analysis module for analyzing the extensible mobility scope of each operator in the DFG

A building block for building a model of the extended mobility scopeDefining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables;

the acquisition module is used for constructing a constraint condition in the integer linear programming model and a constructed linear evaluation function according to the variables to acquire a global optimal solution;

and the scheduling module is used for generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

8. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the method of route enhancement scheduling on a coarse-grained reconfigurable array oriented as claimed in any one of claims 1 to 6.

Technical Field

The invention relates to the technical field of embedded systems, in particular to an operator scheduling algorithm facing a reconfigurable computing array.

Background

Today embedded systems powered by portable devices require high performance and high energy efficiency. Traditionally, in order for compute-intensive Application cores to meet the above requirements, Application hardware in the form of Application Specific Integrated Circuits (ASICs) has become an efficient solution. But have prompted designers to move to programmable solutions due to the convergence of different functions (e.g., voice/data communications, high definition video, etc.) on a single device, as well as the high temporary expense involved in designing ASICs. Coarse-grained reconfigurable arrays are becoming an attractive alternative because they provide high parallel computing power while achieving low cost/low power consumption requirements. Although reconfigurable computing arrays have energy efficient characteristics from a hardware perspective, the actual performance improvement relies heavily on software mapping tools. To improve loop execution performance, modulo scheduling is widely used on reconfigurable computational arrays to speed up loop execution by minimizing the start interval (II) between adjacent loop iterations. Firstly, after a loop is converted into a DFG, performing loop mapping on a reconfigurable computing array by adopting modulo scheduling generally includes 3 basic steps: the first step, operator scheduling, is to place an operator on which time control step to execute. Second, operator placement, i.e., placing an operator on which Processing Element (PE) in the array to execute. And thirdly, value routing, namely how to connect data channels among different PEs to realize the transmission of the operator value.

According to the coupling degree of scheduling and layout and wiring, the mode scheduling on the reconfigurable computing array can be divided into two categories: an integration method and a decomposition method. In the first type, in the integration method, firstly, a Modular Routing Resource Graph (MRRG) is constructed from the architecture description; then, the graph is used for constructing scheduling, operator layout and value routing so as to realize the tight coupling relation between scheduling and layout wiring; the result shows that the mapping quality of the method is good, but the compiling speed is slowed down by integrating scheduling, layout and routing, and the method is only suitable for small-sized DFGs. In the second category, in the decomposition method, scheduling or rescheduling is performed separately from layout and routing, and complex routing strategy exploration needs to be performed on long dependence (data dependence edge spanning multiple time steps) in the DFG in the scheduling stage before layout and routing; finally, value routing is predetermined before layout and wiring, so that higher compiling speed is obtained; since the DFGs of most programs in practical use are relatively large, technical studies have been made on the decomposition method.

In the mapping of the decomposition method, the scheduling stage determines the time step of an operator in the DFG in advance, so the routing strategy is usually studied outside the layout and routing. These decomposition methods can be further divided into scheduling phase route exploration and rescheduling phase route exploration according to the time of exploring the route strategy. In the method BufAware, in order to obtain high-performance and robust compiling, more attention needs to be paid to route exploration in a scheduling phase, and routability of an operator is comprehensively analyzed and explored at the phase so as to improve the success rate of layout and wiring. But the scheduling phase only produces one modified DFG, which will directly increase II once it fails to place and route. Therefore, the method omits rescheduled route exploration after the layout and routing fail. Most methods belong to rescheduling route exploration, and when the initial scheduling DFG is generated, only basic constraint conditions (dependence constraint and resource constraint) are considered and the route exploration of operators in long dependence is omitted, and after the layout and the routing fail, the routes of the unsuccessfully mapped operators are explored to different degrees. In the method EPIMap, rescheduling involves only PE routing node insertion and recalculation of unmapped nodes. In the method REGIMap, the rescheduling includes, in addition to the PE routing node insertion and the recalculation of unmapped nodes, the routing mode of the local register, where the long dependent routing is implicitly routed by the local register. In the method RAMP, the long dependent route exploration modes in the rescheduling stage are more, and the method comprises a local register, a PE routing node, a memory routing node and recalculation.

In summary, the following two main disadvantages exist in the current operator route exploration strategy in the mapping process: firstly, basic operator scheduling and graphic modification are carried out at the stage before layout and wiring, and the scheduling mode which only considers basic constraint but does not pay attention to the flexibility of layout and wiring obtains an initial scheduling scheme which is not beneficial to mapping, and finally results in longer compiling time and even mapping failure. Secondly, in a route searching mode after layout and wiring, the rescheduling process is only concentrated on nodes which are not mapped successfully last time, so that the nodes only support local route searching, and the scheduling mode of partial route searching enables operator mapping to be in local minimum and cannot obtain the best mapping quality.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.

Therefore, a first objective of the present invention is to provide a routing enhancement scheduling method for a coarse-grained reconfigurable array, so as to enhance the routing capability of a data flow graph, thereby improving the performance of circulating water.

The second purpose of the present invention is to provide a routing enhancement scheduling apparatus for a coarse-grained reconfigurable array.

A third object of the invention is to propose a non-transitory computer-readable storage medium.

To achieve the above object, an embodiment of a first aspect of the present invention provides a method for enhanced routing scheduling on a coarse-grained reconfigurable array, including the following steps:

analyzing an extensible mobility scope for each operator in a DFG of an enhanced dataflow graph

According to the extensible mobility scopeDefining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables;

constructing a constraint condition in the integer linear programming model and a constructed linear evaluation function according to the variables to obtain a global optimal solution;

and generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

Optionally, in an embodiment of the present application, specifically, the optimal solution of scheduling generates a new data flow graph, and after the new data flow graph is mapped, the software flow performance may be improved.

Optionally, in one embodiment of the present application, the extensible mobility scope of each operator in the enhanced dataflow graph DFG is analyzedThe method comprises the following steps:

predefining parameters of an operator, the parameters comprising: earliest scheduled time step S_nScheduling time step L at latest_nTime step of the latest route

Performing extensible mobility analysis on operator nodes according to the parameters to obtain extensible mobility scope of each operatorWherein the content of the first and second substances,

optionally, in an embodiment of the present application, the variables of the integer linear programming model are defined as follows:

x_n,i,j，i∈[S_n,L_n]，scheduling operator node n at time step i, inserting one PE routing node at time step j, wherein j is more than or equal to i, and in the case that j is i, the operator n is scheduled at time step i, and j is scheduled at time step i>Under the condition of i, the insertion of the PE routing node is later than the scheduling time step i of the operator n;

y_n,i,j，i∈[S_n,L_n]，wherein, the data value of the operator n in the time step i is stored in a memory by adding a storage node in the time step j;

z_n,i,j，i∈[S_n,L_n]，loading the data value of the operator n pre-stored in the memory at the time step i by adding a data loading node at the time step j;

n_pewherein, under the condition, the total number of operators with the same mode scheduling time step should be less than or equal to n_pe。

Optionally, in an embodiment of the present application, the constraint conditions in the integer linear programming model include:

an operator scheduling time step uniqueness constraint, wherein the operator scheduling time step uniqueness constraint is expressed as:

wherein R represents a set of all mobility operators;

a routing node exclusivity constraint, said routing node exclusivity constraint represented as:

a storage node and load node concurrency constraint, the storage node and load node concurrency constraint being expressed as:

PE and memory route exclusivity constraints expressed as:

a dependency constraint represented as:

wherein E represents a set formed by all long dependent edges in the original DFG;

a PE resource restriction constraint, the PE resource restriction constraint represented as:

a memory chunk resource limit constraint, the memory chunk resource limit constraint represented as:

finding all solutions under the same target value, wherein all solutions under the same target value are expressed as:

wherein the content of the first and second substances,andis a binary cut set obtained under the condition that the target value is S;

a boundary constraint represented as:

O>O_lb

wherein O represents a target value obtained by the current integer linear programming model, O_lbThe target values obtained from the last solution are indicated.

Optionally, in an embodiment of the present application, the method further includes:

evaluating a route enhanced scheduling algorithm according to a first factor and a second factor, wherein the first factor uses a variable n_peModeled into an integer linear program, the second factor is represented as:

where α is the weighting factor of the memory routing node.

Optionally, in an embodiment of the present application, the objective function of the global optimal solution is represented as:

wherein beta is equal to n_insThe upper bound of (c).

In order to achieve the above object, a second aspect of the present invention provides a routing enhancement scheduling apparatus for a coarse-grained reconfigurable array, including the following modules:

an analysis module for analyzing the extensible mobility scope of each operator in the DFG

A building block for building a model of the extended mobility scopeDefining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables;

the acquisition module is used for constructing a constraint condition in the integer linear programming model and a constructed linear evaluation function according to the variables to acquire a global optimal solution;

and the scheduling module is used for generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

Optionally, in an embodiment of the present application, specifically, the optimal solution of scheduling generates a new data flow graph, and after the new data flow graph is mapped, the software flow performance may be improved.

To achieve the above object, a non-transitory computer-readable storage medium is provided in an embodiment of a third aspect of the present application, and a computer program is stored on the non-transitory computer-readable storage medium, and when being executed by a processor, the computer program implements the method for enhanced routing scheduling on a coarse-grained reconfigurable array according to the embodiment of the first aspect of the present application.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic flowchart of a routing enhancement scheduling method for a coarse-grained reconfigurable array according to an embodiment of the present invention;

FIG. 2 is a flow chart of an integer linear programming algorithm of an embodiment of the present application;

FIG. 3 is a schematic diagram of a mobility analysis of a DFG graph in accordance with an embodiment of the present application;

FIG. 4 is a diagram illustrating variable definitions of operators according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a scheduled DFG according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a successful mapping of an embodiment of the present application;

fig. 7 is a schematic diagram of a module of a route enhancement scheduling system on a coarse-grained reconfigurable array according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The following describes a routing enhancement scheduling method on a coarse-grained reconfigurable array according to an embodiment of the present invention with reference to the accompanying drawings.

As shown in fig. 1 and fig. 2, to achieve the above object, an embodiment of a first aspect of the present invention provides a method for enhanced routing scheduling on a coarse-grained reconfigurable array, including the following steps:

step S10, analyzing the extensible mobility range of each operator in the enhanced data flow graph DFG

Step S20, expanding mobility scope according to theDefining variables of an integer linear programming model, and constructing constraint conditions in the integer linear programming model according to the variables, wherein the variables of the integer linear programming model comprise binary variables and integer variables;

s30, constructing constraint conditions in the integer linear programming model and a constructed linear evaluation function according to the variables to obtain a global optimal solution;

and step S40, generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

In an embodiment of the present application, further, specifically, the optimal solution of scheduling generates a new data flow graph, and after mapping, the new data flow graph can improve the software pipeline performance.

In one embodiment of the present application, further, the extensible mobility scope of each operator in the enhanced data flow graph DFG is analyzedThe method comprises the following steps:

predefining parameters of an operator, the parameters comprising: earliest scheduled time step S_nScheduling time step L at latest_nTime step of the latest route

Performing extensible mobility analysis on operator nodes according to the parameters to obtain extensible mobility scope of each operatorWherein the content of the first and second substances,

in an embodiment of the present application, further, the variables of the integer linear programming model are defined as follows:

x_n,i,j，i∈[S_n,L_n]，scheduling operator node n at time step i, and inserting a PE routing node at time step j, wherein j is more than or equal to iIn the case where j equals i, the operator n is scheduled at time step i, at j>Under the condition of i, the insertion of the PE routing node is later than the scheduling time step i of the operator n;

y_n,i,j，i∈[S_n,L_n]，wherein, the data value of the operator n in the time step i is stored in a memory by adding a storage node in the time step j;

z_n,i,j，i∈[S_n,L_n]，loading the data value of the operator n pre-stored in the memory at the time step i by adding a data loading node at the time step j;

n_pewherein, under the condition, the total number of operators with the same mode scheduling time step should be less than or equal to n_pe。

In an embodiment of the present application, further, the constraints in the integer linear programming model include:

an operator scheduling time step uniqueness constraint, wherein the operator scheduling time step uniqueness constraint is expressed as:

wherein R represents a set of all mobility operators;

a routing node exclusivity constraint, said routing node exclusivity constraint represented as:

a storage node and load node concurrency constraint, the storage node and load node concurrency constraint being expressed as:

PE and memory route exclusivity constraints expressed as:

a dependency constraint represented as:

wherein E represents a set formed by all long dependent edges in the original DFG;

a PE resource restriction constraint, the PE resource restriction constraint represented as:

a memory chunk resource limit constraint, the memory chunk resource limit constraint represented as:

finding all solutions under the same target value, wherein all solutions under the same target value are expressed as:

wherein the content of the first and second substances,andis a binary cut set obtained under the condition that the target value is S;

a boundary constraint represented as:

O>O_lb

wherein O represents a target value obtained by the current integer linear programming model, O_lbThe target values obtained from the last solution are indicated.

In an embodiment of the present application, specifically, all solutions under the same target value are found, since a scheduling result cannot completely guarantee successful layout and routing, we may need to generate multiple scheduling schemes, in order to obtain all optimal solutions of an integer linear programming problem, an integer cut is added to an original model to make the original solution infeasible, and then the model is solved to find another optimal solution, since the problem created by us only contains two binary variables of 0 to 1, we can use a binary cut method proposed by Balas and Jeroslow, which only involves one constraint condition, and does not need to add additional variables.

In an embodiment of the present application, specifically, the boundary constraint, performing multiple solutions under the above constraint conditions brings more and more additional constraints C8 to the integer linear programming problem, so that the whole solution process becomes more and more complex; therefore, when the target value obtained by the solution changes, additional constraints need to be introduced to simplify the subsequent solution process, in which case the additional constraint C8 previously added to obtain all solutions at the same target value may be removed.

In an embodiment of the present application, further, the method further includes:

evaluating a route enhanced scheduling algorithm according to a first factor and a second factor, wherein the first factor uses a variable n_peModeled into an integer linear program, the second factor is represented as:

where α is the weighting factor of the memory routing node.

In an embodiment of the present application, further, the objective function of the global optimal solution is expressed as:

wherein beta is equal to n_insThe upper bound of (c).

In one embodiment of the present application, specifically, for the evaluation of mapping flexibility, the maximum width and the long dependent number of the folded DFG are critical to both mapping capability and quality; therefore, we will evaluate the route enhanced scheduling algorithm from these two factors; the first factor can be easily approximated by the variable n_peModeling into integer linear programming; for the second factor, if the long dependency number in the scheduling process is directly built, especially in scheduling supporting graph modification, the solution cost is high and difficult. Therefore, we can use the number of inserted routing nodes to indirectly calculate the number of long dependencies, the more routing nodes inserted in a long dependency, the fewer the number of long dependencies in the DFG.

Since the memory access node will cut long dependencies and exclude more intervening PE routing nodes (constraint C4). Therefore, we give more weight to the memory access nodes, and experiments show that our approach will yield a good scheduling scheme when α is set to 10.

By traversing each long dependency in the original DFG, one canTo be obtained by simple calculation. The first term on the right hand side of the equation represents a reduction of n_peIs a primary task because it can save more PEs and improve routability of each level of folded DFG. The second term on the right hand side of the equation indicates that maximizing n can be used while maintaining the maximum width of the folded DFG_insIn order to reduce the number of long dependencies. Under this objective function and the above 8 constraints, we can use a complex integer linear programming solver, such as PULP [8 ]]To obtain a scheduling solution. By iteratively adding additional solution constraints in the equations, a series of candidate solutions at the current target value may be generated.

In an embodiment of the present application, specifically, a routing enhancement scheduling method for a coarse-grained reconfigurable array according to the present invention is described in detail with reference to the embodiment, and includes:

step 1: the DFG shown in fig. 3 contains 7 operator nodes. Since only operators 1, 4, and 5 have long dependent output edges in the graph, the routable operator set is defined as R ═ {1, 4, 5 }. For operators in R, mobility can be extendedDefining its variables, as shown in the bar graph of figure 3,for operators not in set R, we can directly define a constant for each operator and set its value to 1, since they have no routing nodes. Due to the scalable range of motion of the operators in the R-set,andare all less than T_mThere is no memory access variable y/z of the type in this variable set.

Step 2: mobility is expanded through all operators in the DFG graph in step 1After analysis, all relevant variables can be defined. As shown in fig. 4, the variable in black font represents the variable to be explored, and the variable in blue font is actually a constant set to 1. Set R according to the analysisThe variables defined are:

operator node 1: { x_1，0，0，x_1，0，1}

Operator node 4: { x_4，1，1，x_4，1，2，x_4，2，2}

Operator node 5: { x_5，2，2，x_5，2，3，x_5，3，3}

The remaining operator node variables without mobility: { x_2，1，1，x_3，2，2，x_6，3，3，x_7，4，4}

And step 3: according to all variables defined in step 2, all constraint conditions required in the integer linear programming solution model can be constructed, and the specific constraint is constructed as follows:

x_4，1，1+x_4，2，2＝1 (13a)

x_5，2，2+x_5，3，3＝1 (13b)

x_4，1，1+x_4，2，2≤1 (13c)

x_4，2，2++x_4，1，2≤1 (13d)

x_5，2，2+x_5，3，3≤1 (13e)

x_5，3，3+x_5，2，3≤1 (13f)

0×x_1，0，0-1×x_4，1，1+2x_4，2，2＜0 (13g)

1×x_1，0，1-1×x_4，1，1+2x_4，2，2＜0 (13h)

0×x_1，0，0-1×x_4，1，1+2x_4，2，2＜0 (13i)

1×x_4，1，1-1×x_5，2，2+2x_5，3，3＜0 (13j)

1×x_4，1，1-3×x_6，3，3＜0 (13k)

2×x_4，2，2-1×x_5，2，2+2x_5，3，3＜0 (131)

1×x_4，2，2-3×x_6，3，3＜0 (13m)

1×x_4，1，2-1×x_5，2，2+2x_5，3，3＜0 (13n)

2×x_5，2，2-4×x_7，4，4＜0 (13o)

2×x_5，2，3-4×x_7，4，4＜0 (13p)

x_1，0，0+x_4，1，2+x_5，2，2+x_3，2，2+x_7，4，4-n_pe≤0 (13q)

x_1，0，1+x_4，1，1+x_2，1，1+x_5，2，3+x_5，3，3+x_6，3，3-n_pe≤0 (13r)

constraints C1, C2, C5, and C6 are represented in the above formulas (13a) - (13b), (13C) - (13f), (13g) - (13p), and (13q) - (13r), respectively. Since no memory access variables are defined, the defined constraints C3, C4, and C7 are not included. At the same time, no solution has been obtained in the first round, and therefore also the defined constraints C8 and C9 are included.

And 4, step 4: all constraints of the model solution are constructed in step 3 in order to obtain an optimal scheduling scheme. It is necessary to construct a linearity evaluation function according to step 4 in the summary of the invention. The final objective function can thus be expressed as:

min 7×n_pe-x_1，0，1-x_4，1，1-x_4，1，2

-x_4，2，2-x_5，2，2-x_5，2，3-x_5，3，3

in the above formula, n_peHas a coefficient of7, equal to the total number of routable variables, such an arrangement gives the width of the DFG a higher weight. With a complex integer linear programming solver, we finally arrive at a solution as shown in FIG. 4, where the variable representation with blue cells is 1 and the variable representation with white cells is 0. With this solution a new DFG after scheduling is available (fig. 5), which can be easily mapped onto a 2 x 2 reconfigurable array with II ═ 2 (fig. 6).

The invention has the characteristics and effects that: by creating an integer linear programming model, complete route exploration supporting various routing modes in the scheduling and rescheduling stages is realized, so that a larger optimal solution space is obtained, and the efficiency of the whole mapping process and the mapping quality are finally improved; through the mapping evaluation function, the layout flexibility of the scheduling scheme can be evaluated, the scheduling scheme which is more beneficial to layout and wiring is generated, and finally the efficiency of the whole mapping process and the mapping quality are improved.

The technical effects of this application: the invention aims to provide a route enhancement scheduling method facing a reconfigurable computing array, which unifies traditional operator scheduling and graph modification by constructing an integer linear programming model, realizes complete route exploration in a scheduling stage and a rescheduling stage, reduces mapping time and improves mapping quality.

As shown in fig. 7, to achieve the above object, a second aspect of the present application provides a routing enhancement scheduling apparatus for a coarse-grained reconfigurable array according to the present invention, which includes the following modules:

an analysis module for analyzing the extensible mobility scope of each operator in the DFG

A building block for building a model of the extended mobility scopeDefining variables of an integer linear programming model, constructing from said variablesConstraints in the integer linear programming model, wherein variables of the integer linear programming model include binary variables and integer variables;

the acquisition module is used for constructing a constraint condition in the integer linear programming model and a constructed linear evaluation function according to the variables to acquire a global optimal solution;

and the scheduling module is used for generating a scheduling scheme of the embedded system for supplying power to the portable equipment according to the global optimal solution.

In an embodiment of the present application, further, specifically, the optimal solution of scheduling generates a new data flow graph, and after mapping, the new data flow graph can improve the software pipeline performance.

The technical effects of this application: the invention aims to provide a route enhancement scheduling method facing a reconfigurable computing array, which unifies traditional operator scheduling and graph modification by constructing an integer linear programming model, realizes complete route exploration in a scheduling stage and a rescheduling stage, reduces mapping time and improves mapping quality.

To achieve the above object, an embodiment of the present application further provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for enhanced routing scheduling on a coarse-grained reconfigurable array according to the first aspect of the present application.

Although the present application has been disclosed in detail with reference to the accompanying drawings, it is to be understood that such description is merely illustrative and not restrictive of the application of the present application. The scope of the present application is defined by the appended claims and may include various modifications, adaptations, and equivalents of the invention without departing from the scope and spirit of the application.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.