阅读说明：本技术 计时装置及其运行方法 (time-piece device and method for operating same ) 是由 沈忱 叶红亮 冯耀 于 2018-05-31 设计创作，主要内容包括：一种计时装置及其运行方法。计时装置包括：单芯片模块以及数字计时模块。单芯片模块配置成根据内部的至少两个内部中断信号进行事件处理。数字计时模块配置成进行计时,并于计时事件发生时,产生计时中断信号至单芯片模块；其中计时中断信号的优先层级高于至少两个内部中断信号,以使单芯片模块于接收到计时中断信号时优先处理执行对应计时中断信号的中断服务程序。(A timing device and a method of operating the same. The timing device includes: single-chip module and digital timing module. The single chip module is configured to perform event processing according to at least two internal interrupt signals inside. The digital timing module is configured to time and generate a timing interrupt signal to the single chip module when a timing event occurs; the priority level of the timing interrupt signal is higher than that of the at least two internal interrupt signals, so that the single chip module performs priority processing on the interrupt service program corresponding to the timing interrupt signal when receiving the timing interrupt signal.)

1. A time keeping device comprising:

A single chip module configured to perform event processing according to at least two internal interrupt signals inside; and

A digital timing module configured to perform timing and generate a timing interrupt signal to the single chip module when a timing event occurs, wherein a priority level of the timing interrupt signal is higher than the at least two internal interrupt signals, so that the single chip module preferentially processes and executes an interrupt service program corresponding to the timing interrupt signal when receiving the timing interrupt signal.

2. The timing device of claim 1, wherein the single chip module is further configured to configure the digital timing module to operate in an automatic reload mode.

3. The timing device according to claim 2, wherein the single chip module is further configured to set the digital timing module to generate the timing interrupt signal at regular intervals.

4. The timing device of claim 1, wherein the single chip module executes the interrupt service routine to accumulate a timing variable.

5. The timing device of claim 1, wherein the timing interrupt signal is a power fail interrupt signal.

6. the timing device of claim 1, wherein the single chip module is an 8051 chip.

7. A method of operating a timing device, comprising:

Making a single chip module perform event processing according to at least two internal interrupt signals inside;

A digital timing module is used for timing, and when a timing event occurs, a timing interrupt signal is generated to the single chip module, wherein the priority level of the timing interrupt signal is higher than that of the at least two internal interrupt signals; and

When the single chip module receives the timing interrupt signal, the single chip module is enabled to preferentially process and execute an interrupt service program corresponding to the timing interrupt signal.

8. the method of operating a timing device of claim 7, further comprising:

The single chip module is also configured to set the digital timing module to operate in an automatic reload mode.

9. the method of operating a timing device of claim 8, further comprising:

The single chip module is also configured to set the digital timing module to generate the timing interrupt signal at regular time intervals.

10. The method of operating a timing device of claim 7, further comprising:

The single chip module executes the interrupt service program to accumulate a timing variable.

Technical Field

The present invention relates to timing technology, and more particularly, to a timing device and a method for operating the same.

Background

a single chip module such as (but not limited to) an 8051 chip integrates various basic circuits into a single chip, and is widely applied to many electronic devices as a controller due to its small size. When the single chip module is used for processing data, the more urgent events can be processed according to the internal interrupt signals. However, as applications become more complex and more events need to be processed, when the priority level of the internal interrupt signal is not sufficient to distinguish more types of events, the internal module, such as (but not limited to) a timer, cannot notify the single-chip module of the occurrence of the event in time by the internal interrupt signal.

Therefore, how to design a new timing device and its operation method to solve the above-mentioned drawbacks is an urgent problem to be solved in the art.

Disclosure of Invention

An object of the present invention is to provide a timepiece including: single-chip module and digital timing module. The single chip module is configured to perform event processing according to at least two internal interrupt (interrupt) signals inside. The digital timing module is configured to time and generate a timing interrupt signal to the single chip module when a timing event occurs, wherein the priority level of the timing interrupt signal is higher than that of at least two internal interrupt signals, so that the single chip module preferentially processes and executes an interrupt service program corresponding to the timing interrupt signal when receiving the timing interrupt signal.

Another object of the present invention is to provide a method for operating a timepiece, including: enabling the single chip module to process events according to at least two internal interrupt signals inside; and enabling the digital timing module to time and generating a timing interrupt signal to the single chip module when a timing event occurs, wherein the priority level of the timing interrupt signal is higher than that of at least two internal interrupt signals; and enabling the single chip module to preferentially process and execute the interrupt service program corresponding to the timing interrupt signal when the timing interrupt signal is received.

The digital timing module can process timing events by priority through timing interrupt signals with priority levels higher than internal interrupt signals through the design of the timing device.

Drawings

FIG. 1 is a block diagram of a timing device according to an embodiment of the present invention; and

Fig. 2 is a flowchart illustrating a method for operating a timing device according to an embodiment of the invention.

Description of the symbols

1: the timer device 10: single chip module

100: the central processing unit 101: internal interrupt signal

102: the memory 103: setting signal

104: the timer 105: interrupt service routine

106: input/output interface 12: digital timing module

121: timer interrupt signal 200: method for operating a timing device

201-203: step (ii) of

Detailed Description

Please refer to fig. 1. Fig. 1 is a block diagram of a timing device 1 according to an embodiment of the present invention. The timepiece device 1 includes: a single chip module 10 and a digital timing module 12.

The single chip module 10 can be any microcomputer such as, but not limited to, a cpu 100, a memory 102, a timer 104, various i/o interfaces 106, etc. all integrated on one ic chip. In one embodiment, the CPU 100 may be electrically connected to and communicate with the memory 102, the timer 104, and the I/O interface 106 via a bus (not shown). In one embodiment, the single chip module 100 is, for example but not limited to, an 8051 chip.

The single chip module 10 can process and calculate various data through the cpu 100, and can process events according to the internal interrupt signal 101. For example, when the input/output interface 106 receives an external signal to be processed, an internal interrupt signal 101 is generated and transmitted to the cpu 100 through the bus. The cpu 100 temporarily stops processing data and preferentially processes the request of the internal interrupt signal 101.

The circuitry included in the single chip module 10 can generate at least two priority levels of internal interrupt signals 101. In one embodiment, the internal interrupt signal 101 may have two priority levels. Thus, the internal interrupt signal 101 will include a high priority level internal interrupt signal and a low priority level internal interrupt signal.

When an internal interrupt signal having a high priority level is generated, another internal interrupt signal having a low priority level may be forcibly stopped. When the internal interrupt signal of the low priority level is generated, it can be executed by the single chip module 10 only under the condition that no internal interrupt signal is running. For internal interrupts of high priority level, no internal interrupts of lower or same priority level can stop their operation.

The digital timing module 12 is a digital timing circuit disposed outside the single chip module 10 and configured to perform timing. In one embodiment, the cpu 100 of the single chip module 10 is further configured to set the digital timing module 12 by, for example (but not limited to), a setting signal 103.

In one embodiment, the single chip module 10 configures the digital timing module 12 to operate in, for example but not limited to, an auto reload (auto load) mode. That is, digital timing module 12 will auto-zero upon an overrun (overflow) parameter being timed. In one embodiment, it is the occurrence of a timing event for digital timing module 12 during a parameter overflow.

In one embodiment, the single chip module 10 can set the timing precision of the digital timing module 12.

The digital timing module 12 generates a timing interrupt signal 121 to the single chip module 10 when a timing event (such as, but not limited to, the parameter overflow) occurs. More specifically, the digital clock module 12 can generate a clock interrupt signal 121 to the cpu 100 of the single chip module 10. The priority level of the timer interrupt signal 121 is higher than the two internal interrupt signals, so that the single chip module 10 can preferentially process and execute the interrupt service routine 105 corresponding to the timer interrupt signal 121 when receiving the timer interrupt signal 121.

In one embodiment, the timer interrupt signal 121 is, for example but not limited to, a power fail (power fail) interrupt signal.

The interrupt service routine 105 may be stored, for example, but not limited to, in the memory 102. In one embodiment, the single chip module 10 executes the interrupt service routine 105 to accumulate the internal timing variables. In one embodiment, each time the single chip module 10 receives a timer interrupt signal 121, the interrupt service routine 105 is executed to add 1 to the timer variable, thereby achieving the technical effect of timing.

Since the single chip module 10 needs to handle a great variety of events in the current application, when the priority level of the internal interrupt signal is not enough to distinguish more types of events, the internal timer 104 cannot notify the single chip module 10 of the occurrence of the timing event in time by the internal interrupt signal. Therefore, by the design of the timing device 1, the digital timing module 12 can make the single chip module 10 process the timing event preferentially by the timing interrupt signal 121 with a higher priority level than the internal interrupt signal.

Please refer to fig. 2. FIG. 2 is a flow chart of a method 200 for operating a timing device according to an embodiment of the invention. Can be applied to the timing device 1 of fig. 1. The method 200 includes the following steps (it should be understood that the steps mentioned in the present embodiment, except for the sequence specifically mentioned, can be performed simultaneously or partially simultaneously according to the actual requirement.

In step 201, the single chip module 10 performs event processing according to at least two internal interrupt signals 101.

In step 202, the digital timing module 12 is enabled to perform timing and generate a timing interrupt signal 121 to the single chip module 10 when a timing event occurs, wherein the priority level of the timing interrupt signal 121 is higher than that of the at least two internal interrupt signals 101.

In step 203, the single chip module 10 preferentially processes and executes the interrupt service routine 105 corresponding to the timer interrupt signal 121 when receiving the timer interrupt signal 121.

the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit of the present invention are intended to be included within the scope of the present invention.