阅读说明：本技术 半导体器件的制造方法 (method for manufacturing semiconductor device ) 是由 朴寅洙 尹基准 李起洪 于 2019-02-15 设计创作，主要内容包括：半导体器件的制造方法。一种制造半导体器件的方法,该方法包括如下步骤：在包括有第一区域和第二区域的下部结构上形成第一蚀刻停止图案以暴露所述第二区域；在所述下部结构上堆叠多个堆叠结构以与所述第二区域和所述第一蚀刻停止图案交叠；通过蚀刻所述多个堆叠结构形成阶梯式堆叠结构以暴露所述第一蚀刻停止图案的端部；形成穿过所述阶梯式堆叠结构和所述第一蚀刻停止图案的狭缝；以及经由所述狭缝用导电图案替代所述第一蚀刻停止图案和所述多个堆叠结构的牺牲层。(a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region; stacking a plurality of stacked structures on the lower structure to overlap the second region and the first etch stop pattern; forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern; forming a slit through the stepped stack structure and the first etch stop pattern; and replacing the first etch stop pattern and the sacrificial layer of the plurality of stack structures with a conductive pattern via the slit.)

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

Forming a lower structure including a first region and a second region;

Forming a first etch stop pattern on the lower structure, wherein the first etch stop pattern exposes the second region;

Stacking a plurality of stacked structures on the lower structure to overlap the second region and the first etch stop pattern;

Forming a stepped stack structure by etching the plurality of stack structures, wherein the stepped stack structure exposes an end portion of the first etch stop pattern;

Forming a slit through the stepped stack structure and the first etch stop pattern; and

Replacing the first etch stop pattern and the sacrificial layer of the plurality of stack structures with a conductive pattern via the slit.

2. The method of claim 1, wherein the step of forming a stepped stack structure by etching the plurality of stack structures comprises the steps of: exposing the second region.

3. The method of claim 1, wherein each of the plurality of stack structures comprises the sacrificial layers and interlayer insulating layers alternately stacked, and

wherein the first etch stop pattern includes a material having a different etch rate from the sacrificial layer and the interlayer insulating layer.

4. the method of claim 3, wherein the sacrificial layer comprises a nitride layer,

Wherein the interlayer insulating layer includes an oxide layer, and

Wherein the first etch stop pattern comprises a metal.

5. The method of claim 3, wherein the sacrificial layer comprises a nitride layer,

Wherein the interlayer insulating layer includes an oxide layer, and

Wherein the first etch stop pattern comprises a titanium Ti compound.

6. The method of claim 3, wherein the sacrificial layer comprises a nitride layer,

Wherein the interlayer insulating layer includes an oxide layer, and

Wherein the first etch stop pattern comprises a titanium nitride (TiN) layer.

7. The method of claim 1, wherein the step of stacking the plurality of stacked structures comprises the steps of:

Forming a first stacked structure extending to overlap the first etch stop pattern and the second region;

Forming a first hole through the first stacked structure;

Forming a sacrificial post filling the first hole;

Forming a second stacked structure on the first stacked structure to cover the sacrificial post;

Forming a second hole through the second stack structure and exposing the sacrificial post;

Removing the sacrificial post through the second hole to open the first hole; and

Forming a channel layer in a channel hole defined by coupling the first hole and the second hole.

8. The method of claim 7, wherein the step of forming the sacrificial post comprises the steps of:

forming a protective oxide layer on a surface of the first hole;

forming a metal layer filling a portion of the first hole on the protective oxide layer; and

Forming a second etch stop pattern on the metal layer to fill an upper portion of the first hole.

9. the method of claim 1, wherein the stepped stack structure includes a stepped end portion formed by an end portion of the sacrificial layer and exposes an end portion of the first etch stop pattern,

Wherein the method further comprises the steps of: forming a sacrificial pad pattern on an end portion of the first etch stop pattern exposed by the stepped end portion and on an end portion of the sacrificial layer, and

Wherein the sacrificial pad pattern is replaced with the conductive pattern.

10. The method of claim 9, wherein the step of replacing the first etch stop pattern and the sacrificial layer with the conductive pattern comprises the steps of:

Selectively removing the first etch stop pattern through the slit;

Selectively removing the sacrificial layer and the sacrificial pad pattern via the slit; and

filling the first etch stop pattern, the sacrificial layer, and the sacrificial pad pattern in the removed region with a conductive material.

11. a method of manufacturing a semiconductor device, the method comprising the steps of:

forming a lower structure including a first region and a second region;

Forming a first etch stop pattern on the lower structure, wherein the first etch stop pattern exposes the second region;

forming a first stacked structure on the lower structure to overlap the second region and the first etch stop pattern;

forming a second etch stop pattern on the first stacked structure to expose the second region;

Forming a second stack structure on the second etch stop pattern, the second stack structure overlapping the first region and extending over the second region to overlap the second region;

Forming a stepped stack structure by etching the second stack structure, the second etch stop pattern, and the first stack structure, wherein the stepped stack structure exposes an end portion of the first etch stop pattern;

Forming a slit through the stepped stack structure and the first etch stop pattern; and

Replacing the first etch stop pattern, the second etch stop pattern, and the sacrificial layer of each of the first stack structure and the second stack structure with a conductive pattern via the slit.

12. The method of claim 11, wherein the step of forming a stepped stack structure by etching the second stack structure, the second etch stop pattern, and the first stack structure comprises the steps of: exposing the second region.

13. The method of claim 11, wherein each of the first and second stacked structures includes the sacrificial layers and interlayer insulating layers alternately stacked, and

Wherein each of the first and second etch stop patterns comprises a material having a different etch rate from the sacrificial layer and the interlayer insulating layer.

14. The method of claim 13, wherein the sacrificial layer comprises a nitride layer,

wherein the interlayer insulating layer includes an oxide layer, and

Wherein each of the first and second etch stop patterns comprises a metal.

15. The method of claim 13, wherein the sacrificial layer comprises a nitride layer,

Wherein the interlayer insulating layer includes an oxide layer, and

wherein each of the first and second etch stop patterns comprises a titanium Ti compound.

16. The method of claim 13, wherein the sacrificial layer comprises a nitride layer,

Wherein the interlayer insulating layer includes an oxide layer, and

wherein each of the first and second etch stop patterns comprises a titanium nitride (TiN) layer.

17. The method of claim 11, further comprising the steps of:

Forming a first hole through the first stacked structure;

Forming a protective oxide layer on a surface of the first hole;

forming a metal layer filling a portion of the first hole on the protective oxide layer before forming the second etch stop pattern;

forming a second hole aligned on the first hole by etching the second stack structure and the second etch stop pattern;

Removing the metal layer and the protective oxide layer through the second hole to open the first hole; and

Forming a channel layer in a channel hole defined by coupling the first hole and the second hole.

18. The method of claim 17, wherein the second etch stop pattern is formed on the metal layer to fill an upper portion of the first hole.

19. The method of claim 11, wherein the stepped stack structure includes a stepped end portion formed by an end portion of the sacrificial layer and an end portion of the second etch stop pattern of each of the first and second stack structures, the stepped end portion exposing an end portion of the first etch stop pattern,

Wherein the method further comprises the steps of: forming a sacrificial pad pattern on an end portion of the first etch stop pattern exposed by the stepped stack structure, an end portion of the sacrificial layer, and an end portion of the second etch stop pattern, and

Wherein the sacrificial pad pattern is replaced with the conductive pattern.

20. the method of claim 19, wherein the step of replacing the sacrificial layer, the first etch stop pattern, and the second etch stop pattern with the conductive pattern comprises the steps of:

selectively removing the first etch stop pattern and the second etch stop pattern via the slit;

Selectively removing the sacrificial layer and the sacrificial pad pattern via the slit; and

Filling the first and second etch stop patterns, the sacrificial layer, and the region where the sacrificial pad pattern is removed with a conductive material.

Technical Field

The present disclosure relates generally to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to three-dimensional semiconductor devices and methods of fabricating three-dimensional semiconductor devices.

Background

The semiconductor device may include a memory device capable of storing data. A three-dimensional semiconductor device for increasing the integration density of the semiconductor device has been proposed. The three-dimensional semiconductor device may include memory cells stacked on a substrate to be spaced apart from each other. The three-dimensional semiconductor device may include an interlayer insulating layer, conductive patterns, vertical channels passing through the interlayer insulating layer and the conductive patterns, and a data storage layer disposed between each of the conductive patterns and the vertical channel. A memory cell may be defined at the intersection of the vertical channel and the conductive pattern.

In order to increase the storage capacity of the three-dimensional semiconductor device, a large number of conductive patterns and interlayer insulating layers may be stacked. However, therefore, the difficulty of the manufacturing process may increase.

Disclosure of Invention

according to one embodiment, a method of manufacturing a semiconductor device may include: forming a lower structure including a first region and a second region; forming a first etch stop pattern on the lower structure to expose the second region; stacking a plurality of stacked structures on the lower structure to overlap the second region and the first etch stop pattern; forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern; forming a slit through the stepped stack structure and the first etch stop pattern; and replacing the first etch stop pattern and the sacrificial layer of the plurality of stack structures with a conductive pattern via the slit.

According to one embodiment, a method of manufacturing a semiconductor device may include: forming a lower structure including a first region and a second region; forming a first etch stop pattern on the lower structure to expose the second region; forming a first stacked structure on the lower structure to overlap the second region and the first etch stop pattern; forming a second etch stop pattern on the first stacked structure to expose the second region; forming a second stack structure on the second etch stop pattern, the second stack structure overlapping the first region and extending over the second region to overlap the second region; forming a stepped stack structure by etching the second stack structure, the second etch stop pattern, and the first stack structure to expose an end portion of the first etch stop pattern; forming a slit through the stepped stack structure and the first etch stop pattern; and replacing the sacrificial layer, the first etch stop pattern, and the second etch stop pattern of each of the first stack structure and the second stack structure with a conductive pattern via the slit.

Drawings

fig. 1 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure;

Fig. 2A to 2C are diagrams illustrating a structure of a memory block according to an embodiment of the present disclosure;

Fig. 3A to 3D are cross-sectional views illustrating various structures of a memory string according to an embodiment of the present disclosure;

Fig. 4A to 4C, 5A to 5F, 6A, 6B, and 7A to 7D are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

Fig. 8A to 8E are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

Fig. 9A to 9E are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 10 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure; and

Fig. 11 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

Detailed Description

The technical spirit of the present disclosure may be changed in various ways and may be implemented as an embodiment having various aspects. Hereinafter, the present disclosure will be described by a limited number of possible embodiments so that those skilled in the art can implement the present disclosure in practice.

Although the terms first and/or second may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to indicate a number or priority of elements. For example, a first element discussed below could be termed a second element, and a second element could be termed a first element, without departing from the teachings of the present disclosure.

When an element is referred to as being "coupled" or "connected" to another element, it may be directly coupled or connected to the other element or intervening elements may be present between the "coupled" or "connected" elements. And (3) a component. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present between the "directly coupled" or "directly connected" elements. Other expressions that describe the relationship between elements (such as "between", "directly between", "adjacent to", or "directly adjacent to") should be interpreted in the same manner.

When an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present between the one element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present between the element and the other element.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used in this specification, specify the presence of stated features, quantities, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and/or combinations thereof.

Embodiments of the present application are directed to a method of manufacturing a semiconductor device, which can reduce difficulty in a manufacturing process of a three-dimensional semiconductor device.

Fig. 1 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

referring to fig. 1, the semiconductor device according to the embodiment may include a substrate SUB, a peripheral circuit structure PC disposed on the substrate SUB, and memory blocks BLK1 through BLKn disposed on the peripheral circuit structure PC.

the substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a silicon germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method. The substrate SUB may include a first region a1 and a second region a 2. The first region a1 of the substrate SUB may overlap the memory blocks BLK1 through BLKn. The second region a2 of the substrate SUB may not overlap the respective memory blocks BLK1 through BLKn.

The peripheral circuit structure PC may include a row decoder, a column decoder, a page buffer, and a control circuit. The peripheral circuit structure PC may include n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors electrically coupled to the memory blocks BLK1 through BLKn, resistors, and capacitors. The peripheral circuit structure PC may overlap at least one of the first and second regions a1 and a2 of the substrate SUB.

The memory blocks BLK1 through BLKn may each include a plurality of cell strings electrically coupled to bit lines, impurity doped regions, word lines, and select lines. The memory blocks BLK1 through BLKn may overlap the first region a 1.

fig. 2A to 2C are diagrams illustrating a structure of a memory block according to an embodiment of the present disclosure.

Fig. 2A is a perspective view illustrating a three-dimensional arrangement of memory cells included in a memory block.

Referring to fig. 2A, a memory block according to an embodiment may include word lines WL parallel to a horizontal plane extending in first and second directions I and II. The first direction I may intersect the second direction II (intersector). The word line WL may be a conductive pattern coupled to a gate of the memory cell. Each word line WL may have a linear shape extending in the first direction I. Word lines WL adjacent to each other in the second direction II on the same plane may be separated from each other by a slit SI. The word lines WL may be stacked in a spaced apart manner from each other in the third direction III. The third direction III may vertically pass through a horizontal plane extending in the first direction I and the second direction II. Each word line WL may surround the vertical channel VCH.

Each vertical channel VCH may extend in the third direction III to pass through the word line WL. In order to increase the arrangement density of the vertical channels VCH, the vertical channels VCH may be arranged in a zigzag form. However, embodiments of the present disclosure may not be limited thereto. For example, the vertical channels VCH may be arranged in a matrix form.

each of the plurality of layers ML including the data storage layer may be disposed between each vertical channel VCH and each word line WL. Memory cells may be formed at intersections of word lines WL and respective vertical channels VCH. The gates of a plurality of memory cells disposed on the same horizontal plane may be commonly controlled by one of the word lines WL. Each vertical channel VCH may serve as a channel for a plurality of memory cells stacked in the third direction III.

fig. 2B is an enlarged cross-sectional view of the multilayer ML disposed between each vertical channel VCH and each word line WL as shown in fig. 2A.

Referring to fig. 2B, the vertical channel VCH may be surrounded by the plurality of layers ML. The multilayer ML may be disposed between the vertical channel VCH and the word line WL. The multilayer ML may include a tunnel insulating layer TI surrounding the vertical channel VCH, a data storage layer DL surrounding the tunnel insulating layer TI, and a blocking insulating layer BI surrounding the data storage layer DL. The data storage layer DL may store data changed using Fowler-Nordheim tunneling caused by a voltage difference between the word line WL and the vertical channel VCH. For this operation, the data storage layer DL may include various materials, for example, a nitride layer capable of trapping charges. In addition, the data storage layer DL may include silicon, phase change material, nanodots, and the like. The blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunnel insulating layer TI may include a silicon oxide layer capable of charge tunneling.

The vertical channel VCH may include a semiconductor layer. For example, the vertical channel VCH may include a silicon layer. The vertical channel VCH may have various structures. For example, the vertical channel VCH may have a ring shape defining the core region COA. The core area COA may be completely filled with the vertical channel VCH. In another example, the core region COA may be filled with at least one of an insulating layer and a doped semiconductor layer.

Fig. 2C is a sectional view illustrating an end of the word line WL shown in fig. 2A.

Referring to fig. 2C, word lines WL may be stacked in the third direction III to form a staircase structure. In other words, the word line WL may include a lower pattern and an upper pattern forming a staircase structure. The upper pattern may be defined as being disposed above the lower pattern. The end of the lower pattern may be longer than the upper pattern along the first direction I so as to be exposed without overlapping the upper pattern.

Each word line WL may be divided into a line portion LP and a pad portion PP. The pad part PP may extend from an end of the line part LP. The pad part PP may have a thickness thicker than the line part LP in the third direction III. In other words, the thickness D2 of the pad portion PP may be greater than the thickness D1 of the line portion LP. The pad part PP may be exposed through the stepped structure of the word line WL. An end portion of each word line WL may protrude in the third direction III through the pad portion PP. Each word line contact plug WCT may be coupled with the corresponding pad portion PP to extend in the third direction III. The thick pad part PP may prevent the phenomenon that the word line contact plug WCT crosses the word line WL.

the memory strings contained in the memory blocks may include the structures described in fig. 2A through 2C. The memory string according to the embodiments of the present disclosure may be implemented in various ways.

fig. 3A to 3D are sectional views illustrating various structures of a memory string according to an embodiment of the present disclosure.

referring to fig. 3A to 3D, the memory strings MSR may each include memory cells stacked along respective vertical channels VCH. The memory cells may be formed at intersections of the corresponding vertical channels VCH and word lines WL. As shown in fig. 3A to 3C, the vertical channel VCH may be coupled with the doped region SA disposed under the word line WL. Alternatively, as shown in fig. 3D, the vertical channel VCH may be coupled with the pipe channel PCH disposed under the word line WL.

Referring to fig. 3A to 3C, each vertical channel VCH may pass through a plurality of stack structures stacked on each other. The undercut UC may be defined at the boundary between the plurality of stacked structures. The undercut UC may be defined in the hole in which each vertical channel VCH is provided. Among the plurality of stack structures, the stack structure disposed at the lowermost layer may be defined as a first stack structure STA1, and the stack structure disposed at the uppermost layer may be defined as a second stack structure STA 2. The second stack structure STA2 may be covered by an upper insulation layer UIL. The vertical channel VCH may extend to pass through the upper insulating layer UIL.

The plurality of stack structures may be divided into two groups including a first stack structure STA1 and a second stack structure STA2, respectively. The present disclosure is not limited thereto, and the plurality of stack structures may further include one or more stack structures disposed between the first stack structure STA1 and the second stack structure STA2, and the first stack structure STA1 and the second stack structure STA 2.

Each of the plurality of stack structures may include interlayer insulating layers ILD and conductive patterns CP alternately stacked. Each interlayer insulating layer ILD may include an insulating material such as a silicon oxide layer. Each of the conductive patterns CP may include various conductive materials such as a doped silicon layer, a metal silicide layer, a barrier layer, etc., and may include two or more types of conductive materials. The interlayer insulating layer ILD and the conductive pattern CP may be penetrated by the slits SI.

The slit SI may be filled with a sidewall insulating layer SWI and a source contact structure SC as shown in fig. 3A, or may be filled with a slit insulating layer SIL as shown in fig. 3B and 3C.

Referring to fig. 3A and 3B, the conductive pattern CP may function as a source select line SSL, a word line WL, and a drain select line DSL. For example, the uppermost conductive pattern of the second stack structure STA2 may be used as the drain select line DSL, and the lowermost conductive pattern of the first stack structure STA1 may be used as the source select line SSL. The conductive pattern CP between the source select line SSL and the drain select line DSL may function as the word line WL described with reference to fig. 2A to 2C. The conductive pattern used as the drain select line DSL is not limited to the uppermost conductive pattern of the second stack structure STA 2. For example, each of one or more conductive patterns disposed successively below the uppermost conductive pattern of the second stack structure STA2 may serve as the drain select line DSL. The conductive pattern used as the source selection line SSL is not limited to the lowermost conductive pattern of the first stack structure STA 1. For example, each of one or more conductive patterns disposed continuously above the lowermost conductive pattern of the first stack structure STA1 may serve as the source selection line SSL.

each vertical channel VCH may include a semiconductor layer. For example, each vertical channel VCH may include a silicon layer. The vertical channel VCH may directly contact the doped region SA. The doped region SA may include a source dopant. For example, the doped region SA may be a doped silicon layer including n-type dopants.

Referring to fig. 3A, a doped region SA may be coupled to a sidewall of each vertical channel VCH. For example, the doped region SA may be disposed below the first stacked structure STA 1. The doped region SA may have a structure in which the first doped semiconductor layer SA1, the second doped semiconductor layer SA2, and the third doped semiconductor layer SA3 are stacked. The first, second, and third doped semiconductor layers SA1, SA2, and SA3 may include dopants of different conductivity types, respectively, or may include dopants of the same conductivity type. For example, each of the first, second, and third doped semiconductor layers SA1, SA2, and SA3 may include an n-type silicon layer containing n-type dopants. The third doped semiconductor layer SA3 disposed between the first and second doped semiconductor layers SA1 and SA2 may directly contact the sidewall of the vertical channel VCH.

Each of the vertical channels VCH may pass through the second and third doped semiconductor layers SA2 and SA3 to extend into the first doped semiconductor layer SA 1. The multilayer ML shown in fig. 2B may extend along the outer wall of each vertical channel VCH shown in fig. 3A, and may be divided into an upper pattern MLa and a lower pattern MLb by the third doped semiconductor layer SA 3.

a sidewall insulating layer SWI may be formed on the sidewalls of the slit SI. The slit SI and the sidewall insulating layer SWI may further pass through the third doped semiconductor layer SA 3. The source contact structure SC in the slit SI may be insulated from the conductive pattern CP by the sidewall insulating layer SWI. The source contact structure SC may contact the doped region SA. For example, the source contact structure SC may pass through the second and third doped semiconductor layers SA2 and SA3 to contact the first doped semiconductor layer SA 1. The source contact structure SC may include various conductive materials such as a doped silicon layer, a metal silicide layer, a barrier layer, etc., and may include two or more types of conductive materials. For example, the source contact structure SC may have a stacked structure of a doped silicon layer in contact with the first doped semiconductor layer SA1 and a metal layer formed on the doped silicon layer. The doped silicon layer may include n-type dopants and the metal layer may include a low resistance metal such as tungsten to reduce resistance. The core region of each vertical channel VCH may be filled with a core insulating layer CO and a doped semiconductor pattern CAP. The doped semiconductor pattern CAP may function as a drain junction.

referring to fig. 3B, the doped regions SA may be coupled to the bottom surface of each vertical channel VCH. For example, the doped region SA may be disposed below the first stacked structure STA1 and include an n-type silicon layer containing n-type dopants.

each vertical channel VCH may extend along the top surface of the doped region SA. The multilayer ML shown in fig. 2B may extend along sidewalls of the respective vertical channels VCH shown in fig. 3B, and the respective vertical channels VCH may pass through the multilayer ML to contact the doped region SA.

the core region of each vertical channel VCH may be filled with a core insulating layer CO and a doped semiconductor pattern CAP. The doped semiconductor pattern CAP may function as a drain junction.

Referring to fig. 3C, a lower stack structure LSTLST may be disposed between the first stack structure STA1 and the doping region SA. The lower stack structure LSTLST may include lower insulating layers LIL and source selection lines SSL alternately stacked. The source selection line SSL may be disposed at a single layer or at each of two or more layers.

Referring to fig. 3C, the conductive patterns CP included in the first and second stack structures STA1 and STA2 may serve as word lines WL and drain select lines DSL. The same conductive pattern as described with reference to fig. 3A and 3B may be used as the drain select line DSL. The conductive pattern CP disposed between the drain select line DSL and the source select line SSL may serve as a word line WL.

The lower stack structure LST may be penetrated by the lower channel LPC. The lower channels LPC may each be aligned under the vertical channel VCH and may each be coupled with the vertical channel VCH. The lower channel LPC may be formed by a growth method using an epitaxial process or the like or by a deposition method. The lower channel LPC may directly contact the doped region SA. Each vertical channel VCH may be electrically coupled with the doped region SA via a corresponding lower channel LPC. Each lower channel LPC may serve as a channel layer of a source select transistor coupled to a source select line SSL. Each lower channel LPC may be surrounded by a gate insulating layer GI. Each lower channel LPC may be a doped silicon layer doped with impurities. Each lower channel LPC may include an n-type dopant.

The multilayer ML having the structure shown in fig. 2B may extend along sidewalls of and surround the respective vertical channels VCH. Each vertical channel VCH may pass through the multilayer ML to be in direct contact with the corresponding lower channel LPC. The core region of each vertical channel VCH may be filled with a core insulating layer CO and a doped semiconductor pattern CAP. The core insulating layer CO may be disposed between the corresponding lower channel LPC and the doped semiconductor pattern CAP, and the doped semiconductor pattern CAP may serve as a drain junction.

According to the structures shown in fig. 3A to 3C, the memory string MSR may include memory cells and drain select transistors coupled in series along the respective vertical channels VCH. Memory cells may be formed at intersections of the respective vertical channels VCH and the word lines WL, and drain select transistors may be formed at intersections of the respective vertical channels VCH and the drain select lines DSL.

The memory string MSR may further include a source select transistor coupled in series with the memory cells. The source selection transistors may be formed at intersections of the source selection lines SSL and the respective vertical channels VCH under the memory cells (as shown in fig. 3A and 3B), or may be formed at intersections of the source selection lines SSL and the respective lower channels LPC under the memory cells (as shown in fig. 3C).

Referring to fig. 3D, a memory string MSR may be defined along the pipe channel PCH, and at least two vertical channels VCH1 and VCH2 may be coupled with the pipe channel PCH. Hereinafter, for convenience of explanation, an example of the memory string MSR defined as a U-shape including the first vertical channel VCH1 and the second vertical channel VCH2 coupled to the pipe channel PCH will be described.

The first vertical channel VCH1 may cross the drain-side stacked structure STAD and the second vertical channel VCH2 may cross the source-side stacked structure STAS. The drain-side stack structure STAD and the source-side stack structure STAS may be the same layer and disposed on the same horizontal plane with each other. The drain side stacked structure STAD may be spaced apart from the source side stacked structure STAS by the slit SI and the slit insulating layer SIL filling the slit SI.

The drain-side stack structure STAD and the source-side stack structure STAS may include a plurality of stack structures respectively stacked thereon. Undercut UC may be defined between respective boundaries of the plurality of stacked structures. The undercut UC may be defined in a hole in which each of the first vertical channel VCH1 and the second vertical channel VCH2 is disposed.

Each of the plurality of stack structures may include interlayer insulating layers ILD and conductive patterns CP alternately stacked. The interlayer insulating layer ILD and the conductive pattern CP may include the same material as described with reference to fig. 3A to 3C. As defined in fig. 3A to 3C, among the plurality of stack structures, the stack structure disposed at the lowermost layer may be defined as a first stack structure STA1, and the stack structure disposed at the uppermost layer may be defined as a second stack structure STA 2.

the second stack structure STA2 may be covered by an upper insulation layer UIL. Each of the first vertical channel VCH1 and the second vertical channel VCH2 may extend to pass through the upper insulating layer UIL.

the conductive pattern CP of the drain-side stacked structure STAD may function as a drain select line DSL and a drain-side word line WLD. The conductive pattern CP of the source side stack structure STAS may serve as a source selection line SSL and a source side word line WLS.

the drain select line DSL may be an uppermost conductive pattern of the second stack structure STA2 constituting the drain-side stack structure STAD. In another example, each of the uppermost conductive pattern and one or more conductive patterns disposed continuously under the uppermost conductive pattern may further serve as the drain select line DSL. The drain-side word line WLD may be a conductive pattern disposed under the drain select line DSL.

The source selection line SSL may be an uppermost conductive pattern of the second stack structure STA2 constituting the source side stack structure STAS. In another example, each of the uppermost conductive pattern and one or more conductive patterns disposed continuously under the uppermost conductive pattern may serve as the source selection line SSL. The source side word line WLS may be a conductive pattern disposed under the source selection line SSL.

The pipe channel PCH may be embedded in a pipe gate PG disposed below the drain-side stacked structure STAD and the source-side stacked structure STAS. The pipe grid PG may include various conductive materials. For example, the pipe gate PG may include doped silicon layers stacked as multiple layers. The pipe gate PG may extend to overlap the slit SI and the slit insulating layer SIL.

The pipe channel PCH may be integrated with the first vertical channel VCH1 and the second vertical channel VCH2 and serves as a channel for the memory string MSR. The channel layer including the pipe channel PCH, the first vertical channel VCH1 and the second vertical channel VCH2 may include a semiconductor layer such as silicon.

The multilayer ML may extend along an outer wall of a channel layer including the pipe channel PCH, the first vertical channel VCH1, and the second vertical channel VCH 2. The multilayer ML may include the same material layers as described with reference to fig. 2B. The core region of each of the pipe channel PCH, the first vertical channel VCH1 and the second vertical channel VCH2 may be filled with a core insulating layer CO. The core insulating layer CO may have a lower height than the first vertical channel VCH1 and the second vertical channel VCH 2. The first and second doped semiconductor patterns CAP1 and CAP2 may be disposed on opposite ends of the core insulating layer CO, respectively. The first doped semiconductor pattern CAP1 may be surrounded by the first vertical channel VCH1 and serve as a drain junction. The second doped semiconductor pattern CAP2 may be surrounded by the second vertical channel VCH2 and serve as a source junction.

Each of the first and second doped semiconductor patterns CAP1 and CAP2 may include a doped silicon layer.

According to the structure shown in fig. 3D, a drain select transistor may be formed at an intersection of the first vertical channel VCH1 and the drain select line DSL, and a drain-side memory cell may be formed at an intersection of the first vertical channel VCH1 and the drain-side word line WLD. The drain-side memory cell and the drain select transistor may be coupled in series by a first vertical channel VCH 1.

In addition, a source select transistor may be formed at an intersection of the second vertical channel VCH2 and the source select line SSL, and a source side memory cell may be formed at an intersection of the second vertical channel VCH2 and the source side word line WLS. The source side memory cell and the source select transistor may be coupled in series by a second vertical channel VCH 2.

The source side memory cell and the drain side memory cell may be coupled in series by a pipe transistor formed at an intersection of the pipe channel PCH and the pipe gate PG.

As a result, the memory string MSR shown in fig. 3D may include a drain select transistor, a drain-side memory cell, a pipe transistor, a source-side memory cell, and a source select transistor coupled in series by a channel layer including the pipe channel PCH, the first vertical channel VCH1, and the second vertical channel VCH 2.

In order to increase the integration density of the memory string MSR described with reference to fig. 3A to 3D, the number of memory cells to be stacked may be increased. Hereinafter, various manufacturing methods of a semiconductor device will be described, by which process stability can be increased and process difficulty can be reduced even if the number of memory cells to be stacked is increased.

Fig. 4A to 4C, 5A to 5F, 6A, 6B, and 7A to 7D are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 4A to 4C are sectional views illustrating a process of forming a lower etch stop structure.

Referring to fig. 4A, a first etch stop pattern 103 may be formed on the lower structure 101 including the first and second regions a1 and a 2. The lower structure 101 may include the substrate SUB and the peripheral circuit structure PC shown in fig. 1. The lower structure 101 may also include various structures depending on the structure of the memory string to be formed. For example, the lower structure 101 may further include a doped region SA shown in fig. 3B, a lower stack structure LST shown in fig. 3C, or a pipe gate shown in fig. 3D. The insulating layer may be disposed on the uppermost layer of the lower structure 101.

The first and second regions a1 and a2 of the lower structure 101 may correspond to the first and second regions a1 and a2 shown in fig. 1. The first area a1 of the lower structure 101 may be divided into a cell array area CA and a contact area CTA. The cell array area CA may overlap the vertical channel VCH shown in fig. 2A, and the contact area CTA may overlap the pad portion PP shown in fig. 2C. The second region a2 of the lower structure 101 may not overlap the word line WL, the drain select line DSL, and the source select line SSL shown in fig. 3A to 3D.

The first etch stop pattern 103 may include a material layer having an etch rate different from that of a material layer constituting a plurality of stacked structures to be formed later. The first etch stop pattern 103 may include a material layer having a significantly different etch rate from the stacked structure in order to reduce a slope of an etch surface of a hole or slit during a process of subsequently forming the hole or slit through the stacked structure. For example, the first etch stop pattern 103 may include a material layer having a significantly different etch rate from an oxide layer and a nitride layer compared to a polysilicon layer. In consideration of these etch rates, the first etch stop pattern 103 may include a metal. For example, the first etch stop pattern 103 may include a titanium (Ti) compound, for example, a titanium nitride (TiN) layer.

The first etch stop pattern 103 may be formed to cover the first area a1 of the lower structure 101 and expose the second area a2 of the lower structure 101. According to an embodiment of the present disclosure, the first etch stop pattern 103 including the metal may not remain in the second region a2 and the first etch stop pattern 103 may be formed before forming the stepped stack structure. Accordingly, even if a contact plug (not shown) is disposed at the second region a2, it is possible to prevent a phenomenon in which the contact plug disposed at the second region a2 is electrically coupled to the first etch stop pattern 103 to cause defects in the semiconductor device.

Subsequently, the insulating layer 105 may be formed to cover the second region a2 of the lower structure 101 and the first etch stop pattern 103. The insulating layer 105 may include an oxide layer.

Referring to fig. 4B, in order to planarize the surface of the insulating layer 105 shown in fig. 4A, a planarization process such as Chemical Mechanical Polishing (CMP) may be performed. Accordingly, the surface of the first etch stop pattern 103 may be exposed, and the insulating pattern 105P covering the second area a2 and having a flat surface may be formed.

referring to fig. 4C, an insulating layer 107 covering the first etch stop pattern 103 and the insulating pattern 105P may be further deposited. The insulating layer 107 may include an oxide layer. The insulating pattern 105P and the insulating layer 107 may serve as the first interlayer insulating layer 109. The first interlayer insulating layer 109 may cover the second area a2 of the lower structure 101 and the first etch stop pattern 103, and may have a flat surface.

Through the process described in fig. 4A to 4C, the lower etch stop structure ES including the first etch stop pattern 103 and the first interlayer insulating layer 109 may be formed on the lower structure 101.

Fig. 5A to 5F are sectional views illustrating a process of forming a plurality of stacked structures penetrated by a vertical channel on the lower etch stop structure ES.

referring to fig. 5A, a first stack structure MS1 may be formed on the lower etch stop structure ES. The first stacked structure MS1 may be formed by alternately stacking the first sacrificial layer 111 and the first interlayer insulating layer 113 on the lower etch stop structure ES. The first sacrificial layer 111 and the first interlayer insulating layer 113 may extend to overlap the first etch stop pattern 103 and the second region a 2. The first sacrificial layer 111 and the first interlayer insulating layer 113 may include different materials.

the first interlayer insulating layer 113 may insulate the conductive patterns from each other, and may have high etch resistance with respect to an etching material during an etching process for selectively removing the first sacrificial layer 111. For example, the first interlayer insulating layer 113 may include an oxide layer such as a silicon oxide layer, and the first sacrificial layer 111 may include a nitride layer such as a silicon nitride layer.

Subsequently, a first hole H1 may be formed through the first stacked structure MS1 on the cell array area CA. The first hole H1 may extend to further pass through the first etch stop pattern 103. The width of the lower end of the first hole H1 may be increased using an etch rate difference between the first etch stop pattern 103 and the first sacrificial layer 111 and the first interlayer insulating layer 113 of the first stacked structure MS 1. Therefore, the difference in width between the upper and lower ends of the first hole H1 can be reduced. Since the first etch stop pattern 103 includes a metal, the first etch stop pattern 103 may have high etch resistance with respect to an etching material that etches the first stack structure MS 1. Therefore, the difficulty of the etching process for forming the first hole H1 may be reduced, and the etching process may be stably performed.

referring to fig. 5B, the sacrificial post 120 may be formed in the first hole H1. The process for forming the sacrificial post 120 may include: forming a protective oxide layer 115 on the surface of the first hole H1; forming a metal layer 117 filling a portion of the first hole H1 on the protective oxide layer 115; and a second etch stop layer pattern 119 filling an upper portion of the first hole H1 is formed on the metal layer 117. The metal layer 117 may include a metal having a strength capable of withstanding a process stress, such as tungsten (W). The second etch stop pattern 119 may include the same material as the first etch stop pattern 103.

Referring to fig. 5C, a second stack structure MS2 may be formed on the first stack structure MS1 to cover the sacrificial post 120. The second stack structure MS2 may be formed by alternately stacking the second sacrificial layer 131 and the second interlayer insulating layer 133 on the first stack structure MS 1. The second sacrificial layer 131 and the second interlayer insulating layer 133 may extend to overlap the first etch stop pattern 103 and the second region a 2. The second sacrificial layer 131 may include the same material as the first sacrificial layer 111, and the second interlayer insulating layer 133 may include the same material as the first interlayer insulating layer 113.

subsequently, a mask layer 135 may be formed on the second stack structure MS 2. The mask layer 135 may include a nitride layer such as a silicon nitride layer.

referring to fig. 5D, a mask pattern 135P may be formed by patterning the mask layer 135 illustrated in fig. 5C using a photolithography process. Thereafter, the second hole H2 exposing the second etch stop pattern 119 may be formed by etching the second stack structure MS2 exposed by the mask pattern 135P.

The second etch stop pattern 119 may serve as an etch stop layer during an etching process for forming the second hole H2. The width of the lower end of the second hole H2 may be increased using an etch rate difference between the second etch stop pattern 119 and the second interlayer insulating layer 133 and the second sacrificial layer 131 of the second stack structure MS 2. Therefore, the difference in width between the upper and lower ends of the second hole H2 can be reduced. Since the second etch stop pattern 119 includes a metal, the second etch stop pattern 119 may have a high etch resistance with respect to an etching material that etches the second stack structure MS 2. Therefore, the difficulty of the etching process for forming the second hole H2 may be reduced, and the etching process may be stably performed.

Referring to fig. 5E, the first hole H1 may be opened by removing the sacrificial post through the second hole H2. Accordingly, the first hole H1 and the second hole H2 may be coupled to each other to define the channel hole CH.

Referring to fig. 5F, a multi-layer 141 may be formed on the surface of the channel hole CH. The multi-layer 141 may have a structure consistent with the embodiment described with reference to fig. 2B. Thereafter, a channel layer 143 may be formed on the multilayer 141. The channel layer 143 may function as a vertical channel layer. The channel layer 143 may include a semiconductor layer. Thereafter, a doped semiconductor pattern 147 filling a central region of the channel hole CH and a core insulating layer 145 may be formed on the channel layer 143. The doped semiconductor pattern 147 may fill a central region of the channel hole CH on the core insulating layer 145.

although fig. 5A to 5F illustrate an embodiment of forming the channel layer 143 through the first and second stack structures MS1 and MS2, embodiments of the present disclosure are not limited thereto. For example, one or more stack structures may be further disposed between the first stack structure MS1 and the second stack structure MS 2.

Fig. 6A and 6B are sectional views illustrating a process of forming a stepped stack structure and a process of forming a sacrifice pad pattern.

Referring to fig. 6A, the second stack structure MS2 and the first stack structure MS1 may be patterned (e.g., etched) to have stepped ends SWS disposed on the contact regions CTA. After the stepped end portions SWS are formed, the mask pattern 135P shown in fig. 5F may be removed.

The stepped end portion SWS may expose an end portion of the first etch stop pattern 103. The stepped end portion SWS may be defined as an end portion of the first sacrificial layer 111 of the first stack structure MS1 and an end portion of the second sacrificial layer 131 of the second stack structure MS 2. When the first and second stack structures MS1 and MS2 are patterned (e.g., etched) to form a stepped stack structure, the first and second stack structures MS1 and MS2 may be removed from the second region a 2. In one embodiment, removing (e.g., by etching) the first stacked structure MS1 and the second structure MS2 from the second region a2 may expose the second region a 2. In one embodiment, removing (e.g., by etching) the first stacked structure MS1, the second structure MS2, and the insulating layer 107 from the second region a2 may expose the insulating pattern 105P on the second region a 2.

Referring to fig. 6B, a sacrificial pad pattern 151 may be formed on an end portion of the first etch stop pattern 103 exposed through the stepped stack structure and on an end portion of the first sacrificial layer 111 and an end portion of the second sacrificial layer 131 patterned to have a stepped shape.

The process for forming the sacrificial pad pattern 151 may include: forming a sacrificial pad layer, a first sacrificial layer 111, and a second sacrificial layer 131 deposited on the first etch stop pattern 103 exposed by the stepped stack structure; and etching a portion of the sacrificial pad layer. The sacrificial pad layer may include the same nitride layer as the first sacrificial layer 111 and the second sacrificial layer 131. The sacrificial layer may be etched by a wet etching process using phosphoric acid, and may be divided into a plurality of sacrificial pad patterns 151 by an etching process of the sacrificial pad layer.

during the etching process for forming the sacrificial pad pattern 151, a structure disposed under the first etch stop pattern 103 may be protected with respect to the first etch stop pattern 103 including a material having high etch resistance with respect to the etching process (as described above) for forming the sacrificial pad pattern 151.

subsequently, an upper insulating layer 155 covering the sacrifice pad pattern 151 and the stepped stack structure may be formed. The surface of the upper insulating layer 155 may be planarized.

Fig. 7A to 7D are sectional views illustrating an alternative process via a slit.

Referring to fig. 7A, a first slit SI1 passing through the first and second stack structures MS1 and MS2 on the cell array region CA may be formed. The first slit SI1 may further pass through the upper insulating layer 155. The first etch stop pattern 103 of the lower etch stop structure ES may serve as an etch stop layer during the first etch process for forming the first slit SI 1. In one embodiment, the first slit SI1 may further penetrate through the insulating layer 107 of the lower etch stop structure ES. With a large difference in etch rate between the material layers of the first and second stack structures MS1 and MS2 etched during the first etch process and the first etch stop pattern 103 including metal, a difference in width between the lower end of the first slit SI1 and the upper end of the first slit SI1 may be reduced.

Referring to fig. 7B, the second slit SI2 may be formed by etching the first etch stop pattern exposed by the first slit SI1 in a second etching process. Thereby, the slits SI including the first slits SI1 and the second slits SI2 may be defined.

Subsequently, the first horizontal opening HOP1 may be formed by selectively removing the first etch stop pattern through the slit SI.

referring to fig. 7C, the first sacrificial layer of the first stack structure and the second sacrificial layer of the second stack structure may be selectively removed via the slit SI. A region of the first stack structure where the first sacrificial layer is removed may be defined as the second horizontal opening HOP2, and a region of the second stack structure where the second sacrificial layer is removed may be defined as the third horizontal opening HOP 3. When the first sacrificial layer and the second sacrificial layer are removed, a sacrificial pad pattern including the same material as the first sacrificial layer and the second sacrificial layer may be removed. The removed region of the sacrifice pad pattern may be divided into a first vertical opening VOP1, a second vertical opening VOP2, and a third vertical opening VOP 3.

The first vertical opening VOP1 may be coupled to an end of a first horizontal opening HOP1 on the contact region CTA; the second vertical openings VOP2 may each be coupled to an end of a second horizontal opening HOP2 on the contact area CTA; and the third vertical openings VOPs 3 may each be coupled to an end of a third horizontal opening HOP3 on the contact region CTA.

referring to fig. 7D, after the first, second, and third vertical openings VOP1, VOP2, and VOP3 and the first, second, and third horizontal openings HOP1, HOP2, and HOP3 shown in fig. 7C are filled with a conductive material, the conductive pattern may be divided into a plurality of conductive patterns CP via the slits SI.

each of the conductive patterns CP may include at least one of a doped silicon layer, a metal silicide layer, and a metal layer. A low-resistance metal such as tungsten may be used for each conductive pattern CP for the low-resistance wiring. Each conductive pattern CP may further include a barrier layer such as a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, or the like. Each conductive pattern CP may include a line portion LP extending from the cell array region CA to the contact region CTA, and a pad portion PP extending from an end of the line portion LP and having a thickness thicker than the line portion LP.

The conductive pattern CP may correspond to the conductive pattern CP illustrated in fig. 3A to 3D.

The memory strings illustrated in fig. 3A to 3D may be formed using the above-described method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 8A to 8E are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. For example, fig. 8A to 8E may be sectional views illustrating a method for forming the memory string shown in fig. 3A. Hereinafter, a detailed description of any repetitive process described above will be omitted.

Referring to fig. 8A, a lower structure 201 including a first region a1 and a second region a2 is formed. The lower structure 201 may include a stacked structure of a first doped semiconductor layer 281, a first protective layer 283, a source sacrificial layer 285, a second protective layer 287, a second doped semiconductor layer 289, and an interlayer insulating layer 291. The doped semiconductor layer 281 and the second doped semiconductor layer 289 may include a doped silicon layer. The first and second protective layers 283 and 287 may include oxide layers. The source sacrificial layer 285 may include an undoped semiconductor layer (e.g., an undoped silicon layer).

The first doped semiconductor layer 281, the first protective layer 283, the source sacrificial layer 285, the second protective layer 287, and the second doped semiconductor layer 289 may be penetrated by the isolation layer 290.

The lower etch stop structure ES may be formed on the lower structure 201 shown in fig. 8A using the process described with reference to fig. 4A to 4C.

Thereafter, the first stack structure MS1 may be formed on the lower etch stop structure ES by the same process as described with reference to fig. 5A. Subsequently, a first hole H1' may be formed through the first stacked structure MS 1. The first hole H1' may further pass through the interlayer insulating layer 291, the second doped semiconductor layer 289, the second protective layer 287, the source sacrificial layer 285, and the first protective layer 283, which are disposed under the lower etch stop structure ES at the cell array region CA, to extend into the first doped semiconductor layer 281.

Referring to fig. 8B, a plurality of stacked structures penetrated by the channel hole CH 'may be formed, and the multi-layer 241 and the channel layer 243 may be formed on the surface of the channel hole CH' by using the process described with reference to fig. 5D to 5F. Thereafter, a core insulating layer 245 and a doped semiconductor pattern 247 may be formed, the core insulating layer 245 and the doped semiconductor pattern 247 being disposed on the channel layer 243 and filling a central region of the channel hole CH'.

each of the channel hole CH', the core insulating layer 245, the channel layer 243, and the multi-layer 241 may extend into the first doped semiconductor layer 281 through the second doped semiconductor layer 289, the second protective layer 287, the source sacrificial layer 285, and the first protective layer 283.

Subsequently, a stepped stack structure having stepped ends may be formed on the contact region CTA, and the sacrifice pad pattern 251 may be formed on the stepped ends and the ends of the first etch stop pattern 203 by using the process described with reference to fig. 6A and 6B. The stepped end portion may be defined by an end portion of the first sacrificial layer 211 of the stack structure MS1 and an end portion of the second sacrificial layer 231 of the second stack structure MS 2. Subsequently, an upper insulating layer 255 may be formed.

Thereafter, the slit SI' may be formed using the process described with reference to fig. 7A and 7B. The slit SI' may pass through the upper insulating layer 255, the second stack structure MS2, the first stack structure MS1, and the lower etch stop structure ES. In addition to this, the slit SI' may also pass through the interlayer insulating layer 291 and the second doped semiconductor layer 289 to expose the second protective layer 287.

Referring to fig. 8C, the second protective layer exposed by the slit S1' may be etched to expose the source sacrificial layer, and then the source sacrificial layer may be removed. The multi-layer surrounding a portion of the sidewall of the channel layer 243 may be exposed through the removed region of the source sacrificial layer. The horizontal opening HSP may be formed by removing the exposed multilayers. The multi-layer may be divided into an upper pattern 241a and a lower pattern 241b, and sidewalls of the channel layer 243 may be exposed through the horizontal opening HSP. When the horizontal opening HSP is formed, the first protective layer and the second protective layer may be removed to expose the first doped semiconductor layer 281 and the second doped semiconductor layer 289.

Referring to fig. 8D, a third doped semiconductor layer 295 may be formed in the horizontal opening HSP shown in fig. 8C. The third doped semiconductor layer 295 may be in contact with the channel layer 243, the first doped semiconductor layer 281, and the second doped semiconductor layer 289. The third doped semiconductor layer 295 may be formed by a growth method or a chemical vapor deposition method using the channel layer 243, the first doped semiconductor layer 281, and the second doped semiconductor layer 289 as a seed layer.

Referring to fig. 8E, the first and second sacrificial layers, the first etch stop pattern, and the sacrificial pad pattern may be replaced with a conductive pattern CP by using the process described with respect to fig. 7A to 7D.

Subsequently, a sidewall insulating layer SWI may be formed on the sidewalls of the slit SI'. Thereafter, the source contact structure SC filling the slit SI' may be formed. The source contact structure SC may pass through the sidewall insulating layer SWI to contact the first doped semiconductor layer 281.

Thereafter, a contact plug CT contacting the conductive pattern CP by passing through the upper insulating layer 255 may be formed.

Fig. 9A to 9E are sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, a detailed description of any repetitive process described above will be omitted.

referring to fig. 9A, a lower etch stop structure ES1 may be formed on a lower structure 301 including a first region a1 and a second region a 2.

The lower structure 301 may include the substrate SUB and the peripheral circuit structure PC shown in fig. 1. The lower structure 301 may also include various structures depending on the structure of the memory string to be formed. For example, the lower structure 301 may include the first doped semiconductor layer 281, the first protective layer 283, the source sacrificial layer 285, the second protective layer 287, the second doped semiconductor layer 289, and the interlayer insulating layer 291 described with reference to fig. 8A. Alternatively, the lower structure 301 may further include the doped region SA described with reference to fig. 3B, the lower stack structure LST described with reference to fig. 3C, or the pipe gate PG described with reference to fig. 3D.

The lower etch stop structure ES1 may be formed using the process described with reference to fig. 4A through 4C.

Subsequently, a first stacked structure MS1 may be formed on the lower etch stop structure ES1 by using the process described with reference to fig. 5A. Thereafter, a first hole H1 ″ may be formed through the first stack structure MS1, and the protective oxide layer 315 may be formed on the surface of the first hole H1 ″. Subsequently, a metal layer 317 filling a portion of the first hole H1 ″ may be formed on the protective oxide layer 315. The metal layer 317 may include a metal having strength to withstand process stress, such as tungsten (W).

Thereafter, the first hole H1 ″ on the filling metal layer 317 may be formed and extended to cover the second etch stop pattern 319 of the first stacked structure MS 1. The second etch stop pattern 319 may be patterned not to overlap the second area a 2. The second etch stop pattern 319 may include a first portion 319A filling the first hole H1 ″ and a second portion 319B extending to cover the first stacked structure MS1 on the first portion 319A. The process for forming the second etch stop pattern 319 may include: forming a first portion 319A filling the first hole H1 "; forming an etch stop layer overlying first portion 319A and first stacked structure MS 1; and a second portion 319B is formed by patterning the etch stop layer.

The first and second portions 319A and 319B of the second etch stop pattern 319 may include the same material layer. The first and second portions 319A and 319B of the second etch stop pattern 319 may include the same material as the first etch stop pattern 303 of the lower etch stop structure ES 1. The first and second etch stop patterns 303 and 319 may be selected in consideration of etch rates of material layers constituting the first and second stack structures MS1 and MS 2.

the first and second etch stop patterns 303 and 319 may include a material layer having a significantly different etch rate than the oxide layer and the nitride layer compared to the polysilicon layer in order to reduce the slope of the etched surface of the trench hole or slit (as described with reference to fig. 4A). In other words, the first and second etch stop patterns 303 and 319 may include a metal. For example, the first and second etch stop patterns 303 and 319 may include a titanium (Ti) compound, such as a titanium nitride (TiN) layer.

The first and second etch stop patterns 303 and 319 may be patterned to cover the first region a1 of the lower structure 301 and expose the second region a2 of the lower structure 301, so that it may be possible to prevent a phenomenon in which the contact plug disposed at the second region a2 is electrically coupled to the first and second etch stop patterns 303 and 319, as described with reference to fig. 4A, to cause defects in the semiconductor device.

The second etch stop pattern 319 may be covered by the interlayer insulating layer 329. The interlayer insulating layer 329 may include a first insulating layer 323 and a second insulating layer 325. The first insulating layer 323 may be formed using the same process as the process for forming the insulating pattern 105P described with reference to fig. 4A and 4B. The second insulating layer 325 may be formed using the same process as the process for forming the insulating layer 107 described with reference to fig. 4C. Hereinafter, a stacked structure of the second portion 319B of the second etch stop pattern 319 and the interlayer insulating layer 329 may be defined as an interlayer etch stop structure ES 2.

After forming the interlayer etch stop structure ES2, a second stack structure MS2 may be formed on the interlayer etch stop structure ES2 by using the process described with reference to fig. 5C. The second stack structure MS2 may extend to overlap the first and second etch stop patterns 303 and 319 and the second region a 2.

subsequently, a mask layer 335 may be formed on the second stack structure MS 2. Masking layer 335 may include a nitride layer such as a silicon nitride layer.

referring to fig. 9B, a photolithography process may be used to pattern the mask layer 335 shown in fig. 9A. Thereby, a mask pattern 335P may be formed. Thereafter, the second hole H2 ″ exposing the first portion 319A of the second etch stop pattern 319 may be formed by etching the second stack structure MS2 and the interlayer etch stop structure ES2 exposed through the mask pattern 335P.

The second etch stop pattern 319 may serve as an etch stop layer during an etching process for forming the second hole H2 ″. The width of the lower end of the second hole H2 ″ may be increased using an etch rate difference between the second etch stop pattern 319 and the second interlayer insulating layer 333 and the second sacrificial layer 331 of the second stack structure MS 2. Thereby, the difference in width between the upper end of the second hole H2 "and the lower end of the second hole H2" can be reduced. The second hole H2 "may be aligned over the first hole H1".

Referring to fig. 9C, the first hole H1 "may be opened by removing the first portion 319A of the second etch stop pattern 319, the metal layer 317, and the protective oxide layer 315 through the second hole H2" shown in fig. 9B. Thus, a channel hole CH may be defined to which the first hole H1 "and the second hole H2" are coupled.

Thereafter, the multilayer 341, the channel layer 343, the core insulating layer 345, and the doped semiconductor pattern 347 may be formed in the channel hole CH by using the process described with reference to fig. 5F.

Subsequently, a stepped stack structure having stepped ends may be formed on the contact region CTA, and the sacrifice pad pattern 351 may be formed using the process described with reference to fig. 6A and 6B. In one embodiment, the process of forming the stepped stack structure may further include etching an interlayer insulating layer (329 of fig. 9A) covering the second portion 319B of the second etch stop pattern 319; etching the interlayer insulating layer (329 of fig. 9A) may expose an end portion of the second portion 319B of the second etch stop pattern 319. The stepped end portion may be defined by an end portion of the second sacrificial layer 331 of the second stack structure MS2, an end portion of the first sacrificial layer 311 of the first stack structure MS1, and an end portion of the second portion 319B of the second etch stop pattern 319. The sacrificial pad patterns 351 may be formed on an end portion of the first etch stop pattern 303 and an end portion of the first sacrificial layer 311, an end portion of the second portion 319B of the second etch stop pattern 319, and an end portion of the second sacrificial layer 331 defining stepped end portions, respectively. Thereafter, an upper insulating layer 355 may be formed.

thereafter, a first slit SI1 ″ passing through the upper insulating layer 355 and the second stack structure MS2 and exposing the second portion 319B of the second etch stop pattern 319 may be formed. The second portion 319B of the second etch stop pattern 319 may serve as an etch stop layer during the process of the first etch for forming the first slit SI1 ″. In one embodiment, the first slit SI1 ″ may further pass through the second insulating layer (325 of fig. 9A) of the interlayer insulating layers (329 of fig. 9A).

Etching the second portion 319B of the second etch stop pattern 319 exposed by the first slit SI1 ″ shown in fig. 9C, etching the first stacked structure MS1, and etching the first etch stop pattern 303 may be sequentially performed. Thus, a second slit SI2 "(shown in fig. 9D) coupled to the first slit SI 1" and extending to pass through the lower structure 301 may be formed. Hereinafter, the connection structure of the first slit SI1 "and the second slit SI 2" may be defined as a slit SI ".

referring to fig. 9D, the lower structure 301, the first etch stop pattern 303, the interlayer insulating layers 307, 313, and 333, the second portion 319B of the second etch stop pattern 319, and the first and second sacrificial layers 311 and 331 may be exposed through sidewalls of the slit SI ″. In one embodiment, the second insulating layer 325 of the interlayer insulating layer (329 of fig. 9A) may also be exposed through the sidewalls of the slit SI ″.

Subsequently, the second portions 319B of the first and second etch stop patterns 303 and 319 may be selectively removed via the slits SI ″. Thereafter, the first and second sacrificial layers 311 and 331 and the sacrificial pad pattern 351 may be removed via the slit SI ″.

Referring to fig. 9E, the regions where the first etch stop pattern 303, the second portions 319B of the second etch stop pattern 319, the first and second sacrificial layers 311 and 331, and the sacrificial pad pattern 351 are removed may be filled with the conductive pattern CP. Thereafter, the sidewall insulating layer SWI, the source contact structure SC, and the contact plug CT may be formed using the process described with reference to fig. 8E.

The memory strings illustrated in fig. 3A to 3D may be formed using a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

According to the embodiments of the present disclosure, the difficulty of the etching process for forming the holes and slits by using the etch stop pattern may be reduced.

According to the embodiments of the present disclosure, it is possible to reduce the difficulty of the process of forming the pad portion of the conductive pattern by using the etch stop pattern so that the pad portion may have a thick thickness (e.g., a thickness thicker than the line portion).

Since the etch stop pattern according to the embodiment of the present disclosure includes a material having an etch rate significantly different from that of the stacked structure of the penetration holes and the slits, the widths of the holes and the slits may be uniform.

Since the etch stop pattern according to the embodiments of the present disclosure is patterned before the stepped stack structure is formed, a defect rate of the semiconductor device may be reduced.

Fig. 10 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

Referring to fig. 10, a memory system 1100 according to an embodiment of the present disclosure may include a memory device 1120 and a memory controller 1110.

The memory device 1120 may be a multi-chip package formed of a plurality of flash memory chips.

The memory controller 1110 may be configured to control the memory device 1120 and include a Static Random Access Memory (SRAM)1111, a CPU 1112, a host interface 1113, an Error Correction Code (ECC)1114, and a memory interface. The SRAM 1111 can be used as an operation memory of the CPU 1112. The CPU 1112 can perform overall control operations for data exchange of the memory controller 1110. The host interface 1113 may include data exchange protocols for a host connected to the memory system 1100. The ECC1114 can detect and correct errors included in data read from the memory device 1120. The memory interface 1115 may perform an interface with the memory device 1120. In addition, the memory controller 1110 may further include a Read Only Memory (ROM) for storing code data interfacing with a host.

In one embodiment, the memory system 1100 may be a memory card or a Solid State Disk (SSD) equipped with a memory device 1120 and a memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external device (e.g., a host) via one of various interface protocols including a Universal Serial Bus (USB) protocol, a multi-media card (MMC) protocol, a peripheral component interconnect-express (PCI-E) protocol, a Serial Advanced Technology Attachment (SATA) protocol, a Parallel Advanced Technology Attachment (PATA) protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and so forth.

Fig. 11 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

Referring to FIG. 11, a computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, Random Access Memory (RAM)1230, user interface 1240, modem 1250, and memory system 1210 electrically coupled to a system bus 1260. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may also be further included.

the memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

The above-described embodiments are provided for the purpose of conveying understanding of the technical spirit of the present disclosure. The scope of the present disclosure should not be limited to the above-described embodiments. It is apparent to those skilled in the art to which the present disclosure pertains that other modifications besides the above-described embodiments can be made based on the technical spirit of the present disclosure.

unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Unless otherwise defined in this disclosure, these terms should not be construed as ideal or overly formal.

Cross Reference to Related Applications

This application claims priority to korean patent application No. 10-2018-0065609, filed on 7.6.2018 to the korean intellectual property office, the entire disclosure of which is incorporated herein by reference.