阅读说明：本技术 半导体装置和存储系统 (Semiconductor device and storage system ) 是由 朴珉秀 丘泳埈 于 2015-04-01 设计创作，主要内容包括：一种半导体装置包括：多个存储体,其被配置成响应于地址计数值和行激活信号来执行刷新操作；刷新控制块,其被配置成响应于刷新命令和存储体地址来更新刷新存储体信息,所述刷新存储体信息限定被指定以执行刷新操作的存储体,以及响应于刷新存储体信息来激活计数控制信号；以及计数器,其被配置成响应于计数控制信号的激活来改变地址计数值。(A kind of semiconductor device includes: multiple memory banks, is configured in response to address counter value and row active signal to execute refresh operation；Refresh control block, it is configured in response to refresh command and bank-address to update refresh bank information, the refresh bank information limits is designated to execute the memory bank of refresh operation, and activates counting controling signal in response to refresh bank information；And counter, the activation of counting controling signal is configured in response to change address counter value.)

1. a kind of storage system, comprising:

Memory Controller is configured to: being directed to refresh operation, is provided row address using as specifying among multiple memory banks The information for the regulation memory bank to be refreshed, and refresh command is provided in company with the row address；And

Semiconductor device is configured to: being directed to corresponding with the row address and is designated based on the refresh command At least one memory bank for executing the refresh operation executes the refresh operation.

2. storage system as described in claim 1, wherein the Memory Controller is configured to: for normal operating, to The semiconductor device provides bank-address using as specifying the address of the regulation memory bank among multiple memory banks, with And the row address is provided using as the address for specifying the regulation wordline of the regulation memory bank.

3. storage system as described in claim 1, wherein the Memory Controller have the memory bank to be refreshed with One-to-one mapping between the row address.

4. storage system as claimed in claim 3, wherein by selectively setting the signal position of the row address to One level specifies the multiple memory banks to be refreshed.

5. storage system as claimed in claim 3, wherein by setting the signal position of the row address to the first level or Second electrical level will be designated all as refreshing in the multiple memory bank.

6. a kind of refresh control block, comprising:

Storage element is configured to: when the corresponding memory bank in multiple memory banks is refreshed, setting refreshes by turn Bank information,

Wherein, the bit of the refresh bank information matches with the multiple memory bank by turn.

7. refresh control block according to claim 6, further includes:

Logic circuit is configured to: when whole bits of the refresh bank information are set, activation counts control Signal processed.

8. refresh control block according to claim 7, wherein the storage element is configured to: when the tally control When signal is activated, the refresh bank information is resetted.

9. refresh control block according to claim 7, wherein the refresh bank information indicating finger is deposited to the multiple Store up the specified completion of the refresh operation of each of body.

10. refresh control block according to claim 7, further includes:

Decoder is configured to: being decoded to single bank refresh order and bank-address, and based on decoded Single bank refresh order and bank-address generate decoded signal；And

Control unit is stored, is configured to: the decoded signal and whole bank refresh orders being combined, and base Output signal is generated with whole bank refresh orders in combined decoded signal.

11. refresh control block according to claim 10,

Wherein, the storage element is configured to that the refreshing is arranged based on the output signal of the storage control unit Bank information, and

Wherein, the logic circuit is AND logic circuit, and the AND logic circuit is configured to: being believed the refresh bank Breath executes AND operation, and the counting controling signal is activated based on the AND operation.

12. a kind of semiconductor device, comprising:

Multiple memory banks are configured to execute refresh operation；

Refresh control block, is configured to: when the corresponding memory bank in the multiple memory bank is refreshed, setting by turn Refresh bank information is set, and when whole bits of the refresh bank information are set, activates tally control Signal, wherein the bit of the refresh bank information matches with the multiple memory bank by turn；And

Counter is configured to increase address counter value when the counting controling signal is activated.

13. semiconductor device according to claim 12,

Wherein, the memory bank executes refresh operation based on row active signal and the address counter value.

14. a kind of for refreshing the method for multiple memory banks, which comprises

Refresh operation is executed to multiple memory banks；

Update refresh bank information, brush of the refresh bank information indicating finger to each of the multiple memory bank The specified completion newly operated；And

According to the refresh bank information, only change row address when the multiple memory bank is all refreshed,

Wherein, the bit of the refresh bank information matches with the multiple memory bank by turn.

15. according to the method for claim 14,

Wherein, the refresh operation is based on row active signal and address counter value, and

Wherein, change the row address by changing the address counter value.

16. according to the method for claim 15, wherein deposited based on the refresh bank information indicating finger to the multiple The specified completion of the refresh operation of body is stored up to activate counting controling signal.

17. according to the method for claim 16, wherein change the address based on the activation of the counting controling signal Count value.

Technical field

Various embodiments are usually directed to a kind of semiconductor device, espespecially a kind of semiconductor device that can prevent from refreshing mistake And a kind of storage system using the semiconductor device.

Background technique

A kind of semiconductor device may include multiple memory blocks, such as multiple memory banks (hereinafter referred to as " are deposited Store up body ").

Semiconductor device can execute refresh operation to multiple memory banks according to the control of external equipment, and external equipment is for example It is Memory Controller (for example, CPU, GPU etc.).

Controller provides whole bank refresh orders or single bank refresh order to semiconductor device, wherein complete Portion's bank refresh order is used to be carried out refresh operation to all multiple memory banks, single bank refresh order for pair Any one of multiple memory banks memory bank executes refresh operation.

Summary of the invention

In one embodiment, a kind of semiconductor device may include multiple memory banks, be configured in response to address meter Numerical value and row active signal execute refresh operation.Semiconductor device can also include refresh control block, be configured to respond to Refresh bank information is updated in refresh command and bank-address, and the refresh bank information limits is designated to execute The memory bank of refresh operation, and counting controling signal is activated in response to refresh bank information.In addition, semiconductor device is also It may include counter, be configured in response to the activation of counting controling signal to change address counter value.

In one embodiment, a kind of storage system may include Memory Controller, be configured to provide row address with Refresh command is provided as the information for limiting the memory bank to be refreshed, and together with row address.In addition, storage system may include Semiconductor device, be configured in response to refresh command at least one memory bank execute refresh operation, described at least one A memory bank corresponds to the row address and is designated to execute refresh operation.

In one embodiment, a kind of storage system may include Memory Controller, be configured to provide row address to make For limit the memory bank to be refreshed information, and together with row address provide refresh command.Storage system can also include partly leading Body device, be configured in response to refresh command at least one memory bank execute refresh operation, it is described at least one deposit Storage body corresponds to the row address to execute refresh operation, and when completing for multiple bank refresh are specified, changes and use In the address counter value of the specified wordline to be refreshed.

In one embodiment, a kind of storage system may include Memory Controller, be configured to provide row address with Refresh command is provided as the information for limiting the memory bank to be refreshed, and together with row address.Storage system can also include half Conductor device is configured in response to refresh command and is directed at least one memory bank execution refreshing behaviour for corresponding to row address Make, wherein one or more memory banks are independently increased the address counter value for memory bank, and for for memory bank The corresponding wordline of address counter value executes refresh operation.

Detailed description of the invention

Fig. 1 is the block diagram that can prevent from refreshing the semiconductor device of mistake according to an embodiment.

Fig. 2 is the block diagram for showing the inside configuration of refresh control block shown in Fig. 1.

Fig. 3 is the block diagram according to the storage system of an embodiment.

Fig. 4 is the row address mapping table according to Fig. 3.

Fig. 5 is the block diagram for showing the inside configuration of refresh control block shown in Fig. 3.

Fig. 6 is the block diagram according to the storage system of an embodiment.

Fig. 7 is the circuit diagram of refresh control block shown in Fig. 6.

Specific embodiment

The semiconductor device that can prevent from refreshing mistake and use are described by various embodiments below with reference to attached drawing The storage system of the semiconductor device.Controller can be promoted by repeatedly providing single bank refresh order to all Multiple memory banks execute refresh operation.During repeatedly providing single bank refresh order, controller should also be according to Predesigned order provides the address for selecting corresponding memory bank, i.e. bank-address.However, wrong in the operation due to controller In the case where the reasons such as mistake, communication mistake provide wrong bank-address, it has to the refresh operation of corresponding memory bank is skipped, As a result it is likely to cause the damage of storage data.Be described herein one kind can be avoided refreshing mistake it is steady to multiple memory banks to allow Surely and freely carry out refresh operation semiconductor device and a kind of storage system using the semiconductor device.

With reference to Fig. 1, semiconductor device 100 may include multiple memory banks (hereinafter referred to as " memory bank ") BK0 Block 500, selection block 600 and command decoder 700 are generated to BK7, counter 300, refresh control block 400, activation signal.

Multiple memory bank BK0 to BK7 may be configured in response to row active signal RACT<0:7>and internal row address RAi executes refresh operation to the memory cell with the regulation wordline electric coupling for choosing memory bank BKi (i is one of 0 to n).

In multiple memory bank BK0 into BK7, it is specified that wordline can be selected in response to internal row address RAi.

In multiple memory bank BK0 into BK7, it can activate and the signal that is activated among row active signal RACT<0:7> The regulation wordline of the corresponding memory bank in position or the regulation wordline of all memory bank BK0 to BK7.

Counter 300 may be configured to increase internal address counting value ADD_ in response to counting controling signal C_UP CNT。

Refresh control block 400 may be configured in response to single bank refresh order SBKREF and bank-address BA <0:m>detects the specified completion to the refresh operation of all multiple memory bank BK0 to BK7.Refresh control block 400 can be with Activate counting controling signal C_UP.

Refresh control block 400 may be configured in response to single bank refresh order SBKREF and bank-address BA <0:m>, to be stored in the information for the memory bank being completely refreshed among multiple memory bank BK0 to BK7.Refresh control block 400 is also The specified completion of the refresh operation to all multiple memory bank BK0 to BK7 can be detected based on the information of storage, and is swashed Counting controling signal C_UP living.

Refresh control block 400 may be configured to activate tally control to believe in response to whole bank refresh order REF Number C_UP and it is unrelated with bank-address BA<0:m>.

Activation signal generates block 500 and may be configured to according to activation command ACT, single bank refresh order SBKREF, whole bank refresh order REF and bank-address BA<0:m>are generated row active signal RACT<0:7>.

When inputting activation command ACT, activation signal generate block 500 may be configured to generate row active signal RACT < 0:7>to activate memory bank corresponding with bank-address BA<0:m>.

When inputting single bank refresh order SBKREF, activation signal generates block 500 and may be configured to generate row Activation signal RACT<0:7>is to activate memory bank corresponding with bank-address BA<0:m>.

For example, if having input activation command ACT or single bank refresh order SBKREF, and bank-address BA <0:m>has the value for being used to specify memory bank BK0, then activation signal generation block 500 only can be defeated by row active signal RACT<0> Out to logically high.

If having input whole bank refresh order REF, activation signal generates block 500 can be by all line activatings Signal RACT<0:7>is exported to logically high and unrelated with bank-address BA<0:m>.

Selection block 600 may be configured in response to single bank refresh order SBKREF or whole bank refresh lives REF is enabled to select address counter value ADD_CNT.Selection block 600 can also export internal row address RAi.

Selection block 600 may be configured to select in response to activation command ACT row address RA<0:n>, and in output Portion row address RAi.

Command decoder 700 may be configured to the life provided from the Memory Controller outside semiconductor device 100 CMD is enabled to be decoded.Command decoder 700 can also generate activation command ACT, single bank refresh order SBKREF and complete Portion's bank refresh order REF.

Row address RA<0:n>and bank-address BA<0:m>can be from the Memory Controller outside semiconductor device 100 It provides.

With reference to Fig. 2, refresh control block 400 may include decoder 410, storage control unit 420, storage element 430 and AND logic 440.

Decoder 410 may be configured to single bank refresh order SBKREF and bank-address BA<0:m>into Row decoding, and generate decoded signal DEC<0:7>.

When inputting single bank refresh order SBKREF, decoder 410 solves bank-address BA<0:m> Code.Decoder 410 also activates corresponding decoded signal DEC<0:7>.

Storage control unit 420 may be configured to decoded signal DEC<0:7>and whole bank refresh order REF Phase or (OR), and export gained signal.

Storage control unit 420 may include multiple NOR gate, and NOR gate receives whole bank refresh order REF and decoding The corresponding signal position of signal DEC<0:7>.Storing control unit 420 can also include multiple phase inverters, and phase inverter is by multiple NOR The corresponding output reverse phase of door.

Storage element 430 may be configured to the output signal in response to storing control unit 420 and refresh storage to set Body information REF_B<0:7>.

Storage element 430 may be configured to be resetted according to counting controling signal C_UP refresh bank information REF_B < 0:7>。

Storage element 430 may include trigger F/F, and number corresponds to the letter of refresh bank information REF_B<0:7> Number bits number.

Multiple trigger F/F are entered the output signal of storage control unit 420 via its set terminal S.Multiple triggerings Device F/F is commonly input into counting controling signal C_UP via its reseting terminal R.

AND logic 440 may be configured to by the refresh bank information REF_B<0:7>of storage element 430 mutually with (AND), and counting controling signal C_UP is exported.

It is explained below such as above-mentioned configuration, according to the refresh operation of the semiconductor device 100 of an embodiment.

For example, it is assumed that providing single bank refresh life from the Memory Controller outside semiconductor device 100 SBKREF is enabled, and provides bank-address BA<0:m>, multiple memory bank BK0 to BK7 are sequentially specified.

If have input single bank refresh order SBKREF and be used to specify the bank-address BA of memory bank BK0 < 0:m>, then one of decoded signal DEC<0:7>, such as decoded signal DEC<0>are output into activation level, such as high level.

Since decoded signal DEC<0>is high level, so the refreshing of one of multiple trigger F/F of storage element 430 is deposited Storage body information REF_B<0>is configured to high level.

At this point, since remaining refresh bank information REF_B<1:n>is low level, so counting controling signal C_UP It is output into and deactivates level or low level.

If be used to specify multiple memory bank BK0 to BK7 all bank-address BA<0:m>and single bank refresh Order SBKREF is entered together with regular turn, then all refresh bank information REF_B<0:7>of storage element 430 All become high level.

Since all refresh bank information REF_B<0:7>are high level, so counting controling signal C_UP is defeated Out at high level.

When counting controling signal C_UP is output into high level, all refresh bank information of storage element 430 REF_B<0:7>is reset to low level.

Since counting controling signal C_UP is output into high level, so counter 300 increases address counter value ADD_ CNT。

It can be assumed the memory bank for missing or being incorrectly entered for sequentially specifying multiple memory bank BK0 to BK7 The bank-address BA<0:m>of some storage body is used to specify among address BA<0:m>.

Memory Controller can generally provide bank-address BA<0:m>, and determine and be directed to all multiple storages Body BK0 to BK7 refresh operation corresponding with inside row address RAi is completed, wherein internal row address RAi is produced by counter 300 It is raw.

However, due to missing and be used to specify the bank-address BA<0:m>of some memory bank, so and some The corresponding refresh operation of inside row address RAi of memory bank is not yet performed.

The bank-address BA<0:m>of some memory bank is used to specify due to missing, so the refreshing of storage element 430 Any one of bank information REF_B<0:7>is maintained at low level.

Since any one of refresh bank information REF_B<0:7>is low level, so counting controling signal C_UP It is output into low level.

Since counting controling signal C_UP is output into low level, so counter 300 does not increase address counter value ADD_ CNT.Counter 300 also maintains the current value of address counter value ADD_CNT.

Hereafter, not yet appointed memory bank is used to specify having input together with single bank refresh order SBKREF Bank-address BA<0:m>when, all refresh bank information REF_B<0:7>become high level.Therefore, control is counted Signal C_UP processed is output into high level.

Since counting controling signal C_UP is output into high level, so counter 300 increases address counter value ADD_ CNT。

If having input whole bank refresh order REF, all refresh bank information REF_B<0:7>become It is unrelated with bank-address BA<0:m>for high level, therefore counting controling signal C_UP is output into high level.

Since counting controling signal C_UP is output into high level, so counter 300 increases address counter value ADD_ CNT。

With reference to Fig. 3, storage system 101 may include semiconductor device 110 and Memory Controller 901.

Memory Controller 901 may be configured to provide order CMD, row address RA<0:n>and bank-address BA<0: M > to semiconductor device 110.

In normal operating, Memory Controller 901 may be configured to provide row address RA<0:n>and bank-address BA<0:m>is to semiconductor device 110, and wherein row address RA<0:n>is the address for being used to specify particular word line, bank-address BA <0:m>is the address for being used to specify the particular bank among multiple memory bank BK0 to BK7.

In refresh operation, Memory Controller 901 may be configured to not provide bank-address BA<0:m>but mention For row address RA<0:n>using as being used to limit the address of the memory bank to be refreshed.

Although row address RA<0:n>is the address for selecting wordline, in refresh operation, row address RA is not used <0:n>selects wordline, but uses count internal address.

Since row address RA<0:n>is unnecessary in refresh operation, so Memory Controller 901 can will be brushed The information MAP of new memory bank then can provide row address RA<0:n>to semiconductor device in row address RA<0:n> 110。

Semiconductor device 110 may include multiple memory bank BK0 to BK7, counter 301, refresh control block 401, activation Signal generation block 501, selection block 601 and command decoder 701.

Multiple memory bank BK0 to BK7 may be configured in response to row active signal RACT<0:7>and internal row address RAi refreshes behaviour to execute to the memory cell with the regulation wordline electric coupling for choosing memory bank BKi (i is 0 one into n) Make.

In multiple memory bank BK0 into BK7, the regulation wordline among whole wordline can be in response to internal row address RAi To select.

In multiple memory bank BK0 into BK7, with the signal position that is activated among row active signal RACT<0:7>or multiple Signal position is one corresponding, multiple or all memory bank BK0 to BK7 regulation wordline or multiple regulation wordline can be swashed It is living.

Counter 301 may be configured to increase internal address counting value ADD_ in response to counting controling signal C_UP CNT。

Refresh control block 401 may be configured to be directed in response to refresh command NREF and row address RA<0:n>to detect All multiple memory bank BK0 to BK7 refresh operation specified completion.Refresh control block 401 can also activate tally control to believe Number C_UP.

Refresh command NREF is used as freely refreshing the refreshing life of the new type of multiple memory bank BK0 to BK7 It enables, and it is unrelated with the number for the memory bank to be refreshed and order, it is any into BK7 unlike being used to refresh multiple memory bank BK0 The single bank refresh order SBKREF of memory bank stores for refreshing the whole of all multiple memory bank BK0 to BK7 Body refresh command REF.

Refresh control block 401 may be configured to multiple to store in response to refresh command NREF and row address RA<0:n> The information for the memory bank being completely refreshed among memory bank BK0 to BK7.Refresh control block 401 is also based on the information of storage Specified completion of the detection for all multiple memory bank BK0 to BK7 refresh operation.Refresh control block 401 can also activate meter Number control signal C_UP.

The information MAP of the row address RA<0:n>and the memory bank to be refreshed that are there is provided in refresh operation.

Therefore, refresh control block 401 can store among multiple memory bank BK0 to BK7 in response to row address RA<0:n> The information of the memory bank refreshed completely.

Activation signal generates block 501 and may be configured to according to activation command ACT, refresh command NREF, row address RA < 0: N>and bank-address BA<0:m>is generated row active signal RACT<0:7>.

When inputting activation command ACT, activation signal generate block 501 may be configured to generate row active signal RACT < 0:7>, to activate the memory bank for corresponding to bank-address BA<0:m>.

When inputting refresh command NREF, activation signal generate block 501 may be configured to generate row active signal RACT < 0:7>, to activate memory bank corresponding with row address RA<0:n>of the information MAP for the memory bank to be refreshed.

For example, being used to specify memory bank BK0 if having input activation command ACT and bank-address BA<0:m>and having Value, then activation signal generate block 501 only by among row active signal RACT<0:7>row active signal RACT<0>output extremely It is logically high.

Multiple memory bank BK0 to BK7 are used to specify if having input refresh command NREF and row address RA<0:n>and having Among a memory bank BK2 value, then activation signal generate block 501 can only will be among row active signal RACT<0:7> Row active signal RACT<2>is exported to logically high.

Multiple memory bank BK0 to BK7 are used to specify if having input refresh command NREF and row address RA<0:n>and having Among part memory bank BK0, BK2 and BK5 value, then activation signal generate block 501 can be by row active signal RACT<0:7> Among row active signal RACT<0,2,5>output to logically high.

All multiple memory banks are used to specify if having input refresh command NREF and row address RA<0:n>and having The value of BK0 to BK7, then activation signal generates block 501 and can export all row active signal RACT<0:7>to logically high.

Selection block 601 may be configured to select address counter value ADD_CNT in response to refresh command NREF.Selection block 601 can also export internal row address RAi.

Selection block 601 may be configured to select row address RA<0:n>according to activation command ACT, and export inside Row address RAi.

Command decoder 701 may be configured to decode the order CMD provided from Memory Controller 901.Order decoding Device 701 can also generate activation command ACT and refresh command NREF.

With reference to Fig. 4, the memory bank to be refreshed can be mapped for the n+1 corresponding signal position of row address RA<0:n>.

For example, the memory bank to be refreshed can be used among row address RA<0:n>among multiple memory bank BK0 to BK7 Row address RA<0:7>maps.

If only row address RA<0>is set to high level among row address RA<0:n>, may specify to refresh it is multiple Memory bank BK0 among memory bank BK0 to BK7.

If the row address RA<0:5>among row address RA<0:n>is set to high level, may specify to refresh it is more Memory bank BK0 to BK5 among a memory bank BK0 to BK7.

If row address RA<0 among row address RA<0:n>, 2,4>be set to high level, then may specify will refresh Memory bank BK0, BK2 and BK4.

It, may if whole row address RA<0:7>among row address RA<0:n>are set to high level or low level It is specified to refresh all multiple memory bank BK0 to BK7.

It can be easily recognized that can be wanted in refresh operation by using row address RA<0:n>freely to specify Refresh multiple memory bank BK0 to BK7 and unrelated with the number for the memory bank to be refreshed and order.

By limiting the rule between Memory Controller 901 and semiconductor device 110, semiconductor device 110 can be The row address RA<0:n>provided from Memory Controller 901 is identified as to the information for selecting memory bank in refresh operation.

With reference to Fig. 4 and Fig. 5, refresh control block 401 includes storage control unit 421, storage element 431 and AND logic 441。

Storage control unit 421 may be configured to by refresh command NREF and row address RA<0:7>mutually with (AND), and And output gained signal.

Storage control unit 421 may include multiple NAND gates, and NAND gate receives refresh command NREF and row address RA < 0: 7 > corresponding signal position.Storing control unit 421 can also include multiple phase inverters, and phase inverter keeps the corresponding output of NAND gate anti- Phase.

Storage element 431 may be configured to the output signal in response to storing control unit 421 and refresh storage to set Body information REF_B<0:7>.

Storage element 431 may be configured in response to counting controling signal C_UP by refresh bank information REF_B < 0:7 > reset.

Storage element 431 may include trigger F/F, and number corresponds to the letter of refresh bank information REF_B<0:7> Number bits number.

Multiple trigger F/F are entered the output signal of storage control unit 421 via its set terminal S.Multiple triggerings Device F/F is commonly input into counting controling signal C_UP via its reseting terminal R.

AND logic 441 may be configured to will by the refresh bank information REF_B<0:7>of storage element 431 mutually with (AND), and counting controling signal C_UP is exported.

The refresh operation of such as storage system 101 of above-mentioned configuration explained below.

Refresh command NREF is provided from Memory Controller 901, and provides and is used to specify multiple memory bank BK0 to BK7 In one, the row address RA<0:7>of part or all of memory bank.

In the case where being used to specify row address RA<0:7>an of memory bank according to each refresh command NREF input, All refresh bank information REF_B<0:7>can be stored into high level by 8 refresh operations.

When all refresh bank information REF_B<0:7>are high level, counting controling signal C_UP is output into Activation level, i.e. high level.

When counting controling signal C_UP is output into high level, all refresh bank information of storage element 431 REF_B<0:7>is reset to low level.

Since counting controling signal C_UP is output into high level, so counter 301 increases address counter value ADD_ CNT。

It can be assumed omission or be incorrectly entered and multiple memory bank BK0 are used to specify extremely according to refresh command NREF One in BK7, one or a part in the row address RA<0:7>of part or all of memory bank.

Memory Controller 901 can generally provide row address RA<0:7>, and determine and be directed to all multiple memory banks BK0 to BK7 refresh operation corresponding with inside row address RAi is completed, wherein internal row address RAi is generated by counter 301.

However, due to the mistake for the row address RA<0:7>for being used to specify one or a part of the memory bank BK0 into BK7 The reason of input, so not yet executing refresh operation for the inside row address of corresponding memory bank or multiple corresponding memory banks.

Due to being used to specify the row address RA<0:7>of one or a part of the memory bank BK0 into BK7 by mistakenly defeated Enter, so any one of refresh bank information REF_B<0:7>of storage element 431 or a part are maintained at low electricity It is flat.

Since any one of refresh bank information REF_B<0:7>or a part are low level, so tally control Signal C_UP is output into low level.In addition, counter 301 does not increase address counter value ADD_CNT, and maintain Address count The current value of value ADD_CNT.

Hereafter, due to having input the memory bank BK0 for being used to specify omission one into BK7 together with refresh command NREF Or the row address RA<0:7>of a part, so being counted when all refresh bank information REF_B<0:7>become high level Control signal C_UP is output into high level.

Since counting controling signal C_UP is output into high level, so counter 301 increases address counter value ADD_ CNT。

In embodiment as described above, refresh operation can be by using the letter at least one to be refreshed memory bank The row address RA<0:7>for ceasing mapping, via freely specifying, multiple memory bank BK0 one into BK7, part or all comes It executes.

Multiple memory bank BK0 to BK7 can using in corresponding refresh operation repeat select a memory bank by the way of and Be designated, such as use memory bank BK0+BK1, memory bank BK1+BK2 ... and the BK6+BK7 of memory bank library.

Multiple memory bank BK0 to BK7 can using in corresponding refresh operation repeat select two memory banks by the way of and Be designated, such as using memory bank BK0+BK1+BK2, memory bank BK1+BK2+BK3 ... and memory bank BK5+BK6+BK7 that Sample.

Multiple memory bank BK0 to BK7 can using for even stored body BK0, BK2 ... and BK6 is sequentially performed Refresh operation, then for odd number memory bank BK1, BK3 ... and BK7 is sequentially performed the mode of refresh operation and is referred to It is fixed.

Multiple memory bank BK0 to BK7 can be handed over using two odd number memory banks are then directed to for two even stored bodies It alternately executes the mode of refresh operation and is designated, such as use memory bank BK0+BK2, memory bank BK1+BK3, memory bank BK4+ BK6 and memory bank BK5+BK7 are such.

In addition to these examples, multiple memory bank BK0 to BK7 can be adopted in various manners to select, and then execute refreshing Operation.

With reference to Fig. 6, storage system 102 may include semiconductor device 120 and Memory Controller 902.

Memory Controller 902 may be configured to provide order CMD, row address RA<0:n>and bank-address BA<0: M > to semiconductor device 120.

In normal operating, Memory Controller 902 may be configured to provide row address RA<0:n>and bank-address BA<0:m>is to semiconductor device 120, and wherein row address RA<0:n>is the address for being used to specify particular word line, bank-address BA <0:m>is the address for being used to specify the particular bank among multiple memory bank BK0 to BK7.

In refresh operation, Memory Controller 902 may be configured to not provide bank-address BA<0:m>, but Row address RA<0:n>as the address for being used to limit the memory bank to be refreshed is provided.

The information MAP for the memory bank that Memory Controller 902 can will refresh then may be used in row address RA<0:n> To provide row address RA<0:n>to semiconductor device 120 (see Fig. 4).

Semiconductor device 120 may include multiple memory bank BK0 to BK7, multiple counters 302, refresh control block 402, Activation signal generates block 502, multiple selection blocks 602 and command decoder 702.

Multiple memory bank BK0 to BK7 may be configured to the inside row address RAi_BK<0:7>in response to being directed to memory bank Independent refresh operation is executed with row active signal RACT<0:7>.

Multiple memory bank BK0 can be distributed to one to one extremely for the inside row address RAi_BK<0:7>of memory bank BK7。

More specifically, internal row address RAi_BK<0>can be assigned to memory bank BK0, RAi_BK<1>and be assigned to BK1, RAi_BK<2>be assigned to BK2 ... and RAi_BK<7>is assigned to BK7.

Among multiple memory bank BK0 to BK7, according to selected by the signal position activated among row active signal RACT<0:7> One among memory bank BK0 to BK7 selecting, multiple or whole memory banks, can be in response to being directed to the respective inner of memory bank Row address RAi_BK<0:7>to execute refresh operation to from the memory cell of different wordline electric couplings.It is being provided to storage Selected one among body BK0 to BK7, multiple or whole memory banks inside row address RAi_BK < 0:7 for memory bank > have in the case where identical value, refresh operation can be executed for the memory cell of same word line electric coupling.

Multiple counters 302 can be respectively configured to according to the counting controling signal C_UP_BK<0:7>for being directed to memory bank It is independently increased the address counter value ADD_CNT_BK<0:7>for memory bank.

Multiple counters 302 can be independently stored in for the address counter value ADD_CNT_BK<0:7>of memory bank In.

In other words, address counter value ADD_CNT_BK<0>can be stored in counter Counter_BK0, address is counted Numerical value ADD_CNT_BK<1>can be stored in counter Counter_BK1, address counter value ADD_CNT_BK<2>can be with Be stored in counter Counter_BK2 ... and address counter value ADD_CNT_BK<7>can be stored in counter In Counter_BK7.

Multiple counters can be distributed to one to one for the counting controling signal C_UP_BK<0:7>of memory bank 302。

In other words, counting controling signal C_UP_BK<0>can be assigned to counter Counter_BK0, tally control letter Number C_UP_BK<1>can be assigned to counter Counter_BK1, counting controling signal C_UP_BK<2>can be assigned to Counter Counter_BK2 ... and counting controling signal C_UP_BK<7>can be assigned to counter Counter_BK7.

Refresh control block 402 may be configured to the corresponding signal position according to refresh command NREF and row address RA<0:n> Independently activation is directed to the counting controling signal C_UP_BK<0:7>of memory bank.

Refresh command NREF is used as freely refreshing the refreshing of the new type of multiple memory bank BK0 to BK7 Order, and it is unrelated with the number for the memory bank to be refreshed and order, unlike for refreshing multiple memory bank BK0 appointing into BK7 The single bank refresh order SBKREF of what memory bank or for refreshing the complete of all multiple memory bank BK0 to BK7 Portion's bank refresh order REF.

Activation signal generates block 502 and may be configured to according to activation command ACT, refresh command NREF, row address RA < 0: N>and bank-address BA<0:m>is generated row active signal RACT<0:7>.

When having input activation command ACT, activation signal generates block 502 and may be configured to generate row active signal RACT <0:7>, to activate the memory bank for corresponding to bank-address BA<0:m>.

When having input refresh command NREF, activation signal generates block 502 and may be configured to generate row active signal RACT<0:7>corresponds to the memory bank of row address RA<0:n>to activate, wherein row address RA<0:n>and the memory bank to be refreshed Information MAP.

For example, if having input activation command ACT, and bank-address BA<0:m>has and is used to specify memory bank BK0 Value, then activation signal generate block 502 only by among row active signal RACT<0:7>row active signal RACT<0>output extremely It is logically high.

If have input refresh command NREF, and row address RA<0:n>have be used to specify a memory bank BK2's Value, then activation signal generates block 502 and can only export row active signal RACT<2>to logically high.

If have input refresh command NREF, and row address RA<0:n>have be used to specify part memory bank BK0, BK2 With the value of BK5, then activation signal generate block 502 can be by row active signal RACT<0,2,5>output is to logically high.

If have input refresh command NREF, and row address RA<0:n>have be used to specify all multiple memory banks The value of BK0 to BK7, then activation signal generates block 502 and can export all row active signal RACT<0:7>to logically high.

When inputting refresh command NREF, selection block 602 may be configured to selection and the Address count for being directed to memory bank The corresponding value of address counter value among value ADD_CNT_BK<0:7>, and export the inside row address for being directed to memory bank RAi_BK<0:7>。

That is, selection block Selection Block_BK0 can choose address counter value ADD_CNT_BK<0>, and And export internal row address RAi_BK<0>.Selection block Selection Block_BK1 can choose address counter value ADD_CNT_ BK<1>, and export internal row address RAi_BK<1>.As such, selection block Selection Block_BK7 can choose address Count value ADD_CNT_BK<7>, and export internal row address RAi_BK<7>.

When inputting activation command ACT, selection block 602 may be configured to output row address RA<0:n>, using as being directed to The inside row address RAi_BK<0:7>of memory bank.

If having input activation command ACT, can have for the respective inner row address RAi_BK<0:7>of memory bank The value of identical row address RA<0:n>.

Command decoder 702 may be configured to decode the order CMD provided from Memory Controller 902, and generate Activation command ACT and refresh command NREF.

With reference to Fig. 7, refresh control block 402 may include multiple AND logics, and AND logic is by refresh command NREF and row The corresponding signal position phase of location RA<0:n>and (AND), and export the counting controling signal C_UP_BK<0:7>for being directed to memory bank.

Multiple AND logics may include multiple NAND gates and multiple phase inverters, and phase inverter makes the corresponding defeated of multiple NAND gates Reverse phase out.

Refresh command NREF is commonly input into an input terminal into two input terminals of multiple NAND gates.Separately Outside, the signal position of row address RA<0:n>is separately input into other input terminals.

The refresh operation of the storage system 102 according to an embodiment explained below configured as described above.

Refresh command NREF is provided from Memory Controller 902.Additionally, it is provided for specifying multiple memory bank BK0 extremely One in BK7, the row address RA<0:7>of part or all of memory bank.

First, it is assumed that row address RA<0>is provided as high level together with refresh command NREF, it is used to specify multiple memory banks Memory bank BK0 among BK0 to BK7.

Since the row address RA<0>among row address RA<0:7>is high level, so counting controling signal C_UP_BK<0: 7>among counting controling signal C_UP_BK<0>be output into high level.

According to counting controling signal C_UP_BK<0>, counter Counter_BK0 increase address counter value ADD_CNT_BK< 0>。

Due to having input refresh command NREF, so multiple selection blocks 602 select the Address count for memory bank respectively Value ADD_CNT_BK<0:7>.In addition, multiple selection blocks 602 export inside row address RAi_BK < 0:7 for memory bank respectively >。

For address counter value ADD_CNT_BK<0>quilt among the address counter value ADD_CNT_BK<0:7>of memory bank Increase.In addition, remaining maintains preceding value for the address counter value ADD_CNT_BK<1:7>of memory bank.

To among the wordline of memory bank BK0 correspond to increased address counter value ADD_CNT_BK<0>wordline thermocouple The memory cell connect executes refresh operation.

Assuming that row address RA<1:7>is sequentially provided by high level with predetermined time interval together with refresh command NREF, with It is sequentially designated remaining memory bank BK1 to BK7.

Due to row address RA<1>to RA<7>by Sequential output at high level, so counting controling signal C_UP_BK<1>is extremely C_UP_BK<7>is then by Sequential output at high level.

According to Sequential output at the counting controling signal C_UP_BK<1>to C_UP_BK<7>of high level, counter Counter_BK1 to Counter_BK7 increases the address counter value ADD_CNT_BK<1:7>for being directed to memory bank.

At this time, it is assumed that during providing row address RA<1:7>to be sequentially designated remaining memory bank BK1 to BK7 Miss row address RA<6>.

Due to missing row address RA<6>, that is, row address RA<6>is not converted to high level, so counting controling signal C_ UP_BK<6>is not also converted to high level.Therefore, address counter value ADD_CNT_BK<6>maintains original state.

Therefore, even if Memory Controller 902, which does not identify, misses row address RA<6>and without implementing to be directed to The refreshing of corresponding memory bank, but the normal refresh of wordline corresponding with address counter value ADD_CNT_BK<6>may be next In a refresh operation.

In an example, it can be assumed that row address RA<1:5>is mentioned together with refresh command NREF from Memory Controller 902 For at high level, to specify the memory bank BK1 to BK5 among multiple memory bank BK0 to BK7.

Since the row address RA<1:5>among row address RA<0:7>is high level, so counting controling signal C_UP_BK< 0:7>among counting controling signal C_UP_BK<1:5>be output into high level.

According to counting controling signal C_UP_BK<1:5>, counter Counter_BK1 to Counter_BK5, which increases to be directed to, to be deposited Store up the address counter value ADD_CNT_BK<1:5>of body.

Due to having input refresh command NREF, so multiple selection blocks 602 select the Address count for memory bank respectively Value ADD_CNT_BK<0:7>.In addition, multiple selection blocks 602 export inside row address RAi_BK < 0:7 for memory bank respectively >。

For the address counter value ADD_ for memory bank among the address counter value ADD_CNT_BK<0:7>of memory bank CNT_BK<1:5>is increased.In addition, for remaining address counter value ADD_CNT_BK<0 of memory bank, 6,7>maintenance is previous Value.

To among the wordline of respective banks BK1 to BK5 correspond to for memory bank the address counter value being increased The memory cell of the wordline electric coupling of ADD_CNT_BK<1:5>executes refresh operation.

In one example, it is assumed that row address RA<0:7>is provided as together with refresh command NREF from Memory Controller 902 High level, to specify all multiple memory bank BK0 to BK7.

Since all row address RA<0:7>are high level, so all counting controling signal C_UP_BK<0:7> All it is output into high level.

According to counting controling signal C_UP_BK<0:7>, counter Counter_BK0 to Counter_BK7, which increases to be directed to, to be deposited Store up the address counter value ADD_CNT_BK<0:7>of body.

Due to having input refresh command NREF, so selection block 602 selects the address counter value for memory bank respectively ADD_CNT_BK<0:7>.Multiple selection blocks 602 also respectively inside row address RAi_BK<0:7>of the output for memory bank.

To among the wordline of multiple respective banks BK0 to BK7 with correspond to for memory bank the address being increased The memory cell of the wordline electric coupling of count value ADD_CNT_BK<0:7>executes refresh operation.

It, can be by using the information MAP at least one to be refreshed memory bank in embodiment as described above Row address RA<0:7>is held via multiple memory bank BK0 one into BK7, part or all of memory bank is freely specified Row refresh operation.

Multiple memory bank BK0 to BK7 can be deposited by the way of a storage body using repeating selection in corresponding refresh operation and Be designated, such as use memory bank BK0+BK1, memory bank BK1+BK2 ... and memory bank BK6+BK7.

Multiple memory bank BK0 to BK7 can using in corresponding refresh operation repeat select two memory banks by the way of and Be designated, such as using memory bank BK0+BK1+BK2, memory bank BK1+BK2+BK3 ... and memory bank BK5+BK6+BK7 that Sample.

Multiple memory bank BK0 to BK7 can using for even stored body BK0, BK2 ... and BK6 is sequentially performed Refresh operation, then for odd number memory bank BK1, BK3 ... and BK7 is sequentially performed the mode of refresh operation and is referred to It is fixed.

Multiple memory bank BK0 to BK7 can be handed over using two odd number memory banks are then directed to for two even stored bodies It alternately executes the mode of refresh operation and is designated, such as use memory bank BK0+BK2, memory bank BK1+BK3, memory bank BK4+ BK6 and memory bank BK5+BK7 are such.

Other than previous example, multiple memory bank BK0 to BK7 can be selected using various ways, then execute brush New operation.

Although it have been described that various embodiments, it will be appreciated, however, by one skilled in the art that described embodiment is only It is to illustrate.Therefore, should not be limited based on described embodiment it is described herein can prevent refresh mistake Semiconductor device and the storage system for using the semiconductor device.

Embodiment through the invention can be seen that the present invention provides following technical solutions:

1. a kind of semiconductor device, comprising:

Multiple memory banks are configured in response to address counter value and row active signal to execute refresh operation；

Refresh control block is configured in response to refresh command and bank-address and is designated to execute to update restriction The refresh bank information of the memory bank of the refresh operation, and controlled in response to the refresh bank information to activate to count Signal processed；And

Counter is configured in response to the activation of the counting controling signal to change the address counter value.

2. semiconductor device as described in technical solution 1, wherein when the refresh bank information is defined for all Multiple bank refresh operation specified completion when, the refresh control block is configured to activate the refresh control signal.

3. semiconductor device as described in technical solution 1, wherein the refresh command includes for only refreshing multiple storages The single bank refresh order of any one of body memory bank is stored for refreshing the whole of all multiple memory banks Body refresh command.

4. semiconductor device as described in technical solution 3, wherein the refresh control block is configured to described complete when inputting The counting controling signal is activated when portion's bank refresh order and unrelated with the bank-address.

5. semiconductor device as described in technical solution 1, wherein the refresh control block is configured in response to the meter The activation of number control signal resets the refresh bank information.

6. semiconductor device as described in technical solution 1, wherein the refresh control block includes:

Decoder is configured to be decoded the single bank refresh order and the bank-address, and And generate decoded signal；

Control unit is stored, is configured to the decoded signal and whole bank refresh orders carrying out group It closes, and output signal is exported；

Storage element is configured in response to the output signal of the storage control unit to set the refreshing storage Body information；And

AND logic, be configured to by the refresh bank information phase with and export the counting controling signal.

7. semiconductor device as described in technical solution 6, wherein the storage element is configured in response to the counting Signal is controlled to reset the refresh bank information.

8. semiconductor device as described in technical solution 1, wherein the address counter value is for selecting the multiple deposit Store up the value of the regulation wordline of body.

9. semiconductor device as described in technical solution 1, wherein in normal operating, among the multiple memory bank Any one memory bank is selected by the bank-address and the wordline of selected memory bank is selected by row address It selects.

10. a kind of storage system, comprising:

Memory Controller is configured to provide row address using the information as the restriction memory bank to be refreshed, and Refresh command is provided together with the row address；And

Semiconductor device is configured in response to the refresh command, for it is corresponding with the row address and by It is specified that refresh operation is executed at least one memory bank for executing the refresh operation.

11. storage system as described in technical solution 10, wherein the Memory Controller is configured to: normally grasping Bank-address is provided using as the regulation memory bank being used to specify among multiple memory banks to the semiconductor device in work Address, and the row address is provided using the address as the regulation wordline for specifying the regulation memory bank.

12. storage system as described in technical solution 10, wherein phase of the memory bank to be refreshed relative to the row address Induction signal position one-to-one mapping.

13. the storage system as described in technical solution 12, wherein the multiple memory banks to be refreshed are by by the row address Signal position selectively set to the first level and specify.

14. the storage system as described in technical solution 12, wherein by the way that the signal position of the row address is set as first Level or second electrical level specify all multiple memory banks to refresh.

15. a kind of storage system, comprising:

Memory Controller is configured to provide row address using the information as the restriction memory bank to be refreshed, and Refresh command is provided together with the row address；And

Semiconductor device is configured in response to the refresh command at least one memory bank and executes refreshing behaviour Make, wherein at least one described memory bank is designated to execute refresh operation according to the row address, and is deposited when for multiple When storage body refreshes specified complete, change the address counter value for being used for the specified wordline to be refreshed.

16. the storage system as described in technical solution 15, wherein the Memory Controller is configured to, and is normally being grasped Bank-address is provided using as the regulation memory bank being used to specify among multiple memory banks to the semiconductor device in work Address, and the row address is provided using the address as the regulation wordline for being used to specify the regulation memory bank.

17. the storage system as described in technical solution 15, wherein phase of the memory bank to be refreshed relative to the row address Induction signal position is by one-to-one mapping.

18. the storage system as described in technical solution 15, wherein the semiconductor device includes:

Multiple memory banks are configured in response to the address counter value and row active signal to execute the refreshing behaviour Make；

Refresh control block is configured in response to the refresh command and the row address to update refresh bank letter Breath, the refresh bank information limit among the multiple memory bank be designated with execute the refresh operation at least one Memory bank and the refresh control block are configured in response to the refresh bank information to activate counting controling signal； And

Counter is configured in response to the activation of the counting controling signal to change the address counter value.

19. the storage system as described in technical solution 18, wherein the refresh control block is configured in response to the meter Number controls the activation of signal to reset the refresh bank information.

20. the storage system as described in technical solution 18, wherein the refresh control block includes:

Store control unit, be configured to the refresh command and the row address phase and, and by output signal Output；

Storage element is configured in response to the output signal of the storage control unit to set the refreshing storage Body information；And

AND logic, be configured to by the refresh bank information phase with and export the counting controling signal.

21. the storage system as described in technical solution 20, wherein the storage element is configured in response to the counting Signal is controlled to reset the refresh bank information.

22. the storage system as described in technical solution 15, wherein the address counter value is for selecting the multiple deposit Store up the value of the regulation wordline of body.

23. a kind of storage system, comprising:

Memory Controller is configured to provide row address using the information as the restriction memory bank to be refreshed, and Refresh command is provided together with the row address；And

Semiconductor device is configured in response to the refresh command and is designated for according to row address to execute refreshing One or more memory banks of operation execute the refresh operation, wherein one or more of memory banks are independently increased The brush is executed for the address counter value of memory bank, and for wordline corresponding with the address counter value of memory bank is directed to New operation.

24. the storage system as described in technical solution 23, wherein the Memory Controller is configured to, and is normally being grasped Bank-address is provided using as the regulation memory bank being used to specify among multiple memory banks to the semiconductor device in work Address, and the row address is provided using the address as the regulation wordline for being used to specify the regulation memory bank.

25. the storage system as described in technical solution 23, wherein phase of the memory bank to be refreshed relative to the row address Induction signal position one-to-one mapping.

26. the storage system as described in technical solution 23, wherein the semiconductor device includes:

Multiple memory banks, be configured in response to row active signal and for memory bank address counter value to execute State refresh operation；

Refresh control block is configured in response to the corresponding signal position of the refresh command and the row address independently Activation is directed to the counting controling signal of memory bank；And

Multiple counters are configured in response to separately increase needle for the counting controling signal of memory bank To the address counter value of memory bank.