阅读说明：本技术 包括支撑物的3d半导体器件及其形成方法 (3D semiconductor devices including supporter and forming method thereof ) 是由 洪祥准 金利柱 申重植 于 2019-04-04 设计创作，主要内容包括：一种半导体器件包括在衬底上的下导电层。导电线在下导电层上。提供在导电线中的掩埋沟槽。提供在导电线上并在掩埋沟槽中延伸的支撑物。包括交替堆叠的多个绝缘层和多个导电层的堆叠结构在支撑物上。提供穿过堆叠结构、支撑物和导电线的沟道结构。提供穿过堆叠结构、支撑物和导电线的隔离沟槽。(A kind of semiconductor devices includes lower conductiving layer on substrate.Conductor wire is on lower conductiving layer.Burial groove in conductor wire is provided.The supporter for providing on conductor wire and extending in burying groove.Stacked structure including the multiple insulating layers and multiple conductive layers that are alternately stacked is on a support.Channel structure across stacked structure, supporter and conductor wire is provided.Isolated groove across stacked structure, supporter and conductor wire is provided.)

1. a kind of semiconductor devices, comprising:

Lower conductiving layer on substrate；

Conductor wire on the lower conductiving layer；

Burial groove in the conductor wire；

The supporter extended on the conductor wire and in the burial groove；

Stacked structure, including the multiple insulating layers and multiple conductive layers being alternately stacked on above support；

Channel structure passes through the stacked structure, above support and the conductor wire；With

Isolated groove passes through the stacked structure, above support and the conductor wire.

2. semiconductor devices according to claim 1, wherein above support includes:

Support plate on the conductor wire；With

The support pattern connecting in the burial groove and with the support plate.

3. semiconductor devices according to claim 2, wherein the isolated groove passes through the support pattern.

4. semiconductor devices according to claim 2, wherein the support pattern includes material identical with the support plate Material.

5. semiconductor devices according to claim 2, wherein the support pattern and the support plate include polysilicon.

6. semiconductor devices according to claim 2, wherein the lower end of the support pattern and the lower conductiving layer are direct Contact.

7. semiconductor devices according to claim 2, wherein the conductor wire and the lower conductiving layer and the support plate Directly contact.

8. semiconductor devices according to claim 2 further includes between the support pattern and the lower conductiving layer Lower mold layer.

9. semiconductor devices according to claim 1, wherein the channel structure includes:

Core pattern；

Channel pattern on the outside of the core pattern；With

Information on the outside of the channel pattern stores pattern,

Wherein the conductor wire passes through information storage pattern directly to contact with the side surface of the channel pattern.

10. a kind of semiconductor devices, comprising:

Substrate, including unit area and welding disking area；

Lower conductiving layer, over the substrate；

Mold layer, in the welding disking area on the lower conductiving layer；

Conductor wire, in the unit area on the lower conductiving layer and at the level essentially identical with the mold layer；

Multiple burial grooves, in the conductor wire and the mold layer；

Supporter extends on the conductor wire and the mold layer and in the multiple burial groove；

Stacked structure, including the multiple insulating layers and multiple conductive layers being alternately stacked on above support；

Cell channel structure passes through the stacked structure, above support and the conductor wire；

Illusory channel structure passes through the stacked structure, above support and the mold layer；With

Multiple isolated grooves pass through the stacked structure, above support and the conductor wire.

11. semiconductor devices according to claim 10, wherein above support includes:

Support plate；

Pattern is supported, is connect in the multiple burial groove in the unit area and with the support plate；With

Support bar is connect in the multiple burial groove in the welding disking area and with the support plate.

12. semiconductor devices according to claim 11, wherein at least one of the multiple isolated groove passes through institute State support pattern and the support bar.

13. a kind of semiconductor devices, comprising:

Substrate, including unit area and the welding disking area adjacent with the unit area；

Lower conductiving layer, over the substrate；

Mold layer, in the welding disking area on the lower conductiving layer；

Conductor wire, in the unit area on the lower conductiving layer and at the level essentially identical with the mold layer；

First extends burial groove, in the mold layer；

Second extends burial groove, extends burial groove with described first and is spaced apart and in the mold layer；

Supporter on the conductor wire and the mold layer and extends mask trench and described second described first and extends mask Extend in groove；

Stacked structure, including the multiple insulating layers and multiple conductive layers being alternately stacked on above support；

Multiple cell channel structures pass through the stacked structure, above support and the conductor wire；

Multiple illusory channel structures are buried groove and the second extension burial groove across extending described first The stacked structure, above support and the mold layer；With

Multiple isolated grooves pass through the stacked structure, above support and the conductor wire.

14. semiconductor devices according to claim 13, wherein above support includes:

Support plate, on the conductor wire and the mold layer；

First extends support bar, extends described first and buries in groove and connect with the support plate；With

Second extends support bar, extends described second and buries in groove and connect with the support plate.

15. semiconductor devices according to claim 14, further includes:

Third, which extends, buries groove, extends burial groove and described second described first and extends the mould buried between groove In layer；With

Third extends support bar, extends in the third and buries in groove and connect with the support plate.

16. semiconductor devices according to claim 15, further includes:

4th extends burial groove, extends burial groove described first and the third extends the mould buried between groove In layer；

4th extends support bar, extends the described 4th and buries in groove and connect with the support plate；

5th extends burial groove, extends burial groove described second and the third extends the mould buried between groove In layer；With

5th extends support bar, extends the described 5th and buries in groove and connect with the support plate,

Wherein, the described 4th extends burial groove and the 5th extension burial groove and the unit area and the pad area Boundary between domain is adjacent.

17. semiconductor devices according to claim 16, in which:

4th extension buries groove and is connected to the first extension burial groove and third extension burial groove；And

5th extension buries groove and is connected to the second extension burial groove and third extension burial groove.

18. semiconductor devices according to claim 16, further includes:

6th extends burial groove, extends burial groove described first and the third extends the mould buried between groove In layer；

6th extends support bar, extends the described 6th and buries in groove and connect with the support plate；

7th extends burial groove, extends burial groove described second and the third extends the mould buried between groove In layer；With

7th extends support bar, extends the described 7th and buries in groove and connect with the support plate,

Wherein it is opposite with the 4th extension burial groove to bury groove for the 6th extension, and the described 7th extends burial ditch Slot is opposite with the 5th extension burial groove.

19. semiconductor devices according to claim 18, in which:

6th extension buries groove and is connected to the first extension burial groove and third extension burial groove；And

7th extension buries groove and is connected to the second extension burial groove and third extension burial groove.

20. semiconductor devices according to claim 15, further includes:

Multiple first units bury groove, and it is right on the extended line for burying groove to extend in the conductor wire and described first Together；

Multiple first units support pattern, bury in groove in the multiple first unit and connect with the support plate；

Multiple second units bury groove, and it is right on the extended line for burying groove to extend in the conductor wire and described second Together；With

Multiple second units support pattern, bury in groove in the multiple second unit and connect with the support plate.

21. a kind of semiconductor devices, comprising:

Lower conductiving layer on substrate；

Conductor wire on the lower conductiving layer；

Burial groove in the conductor wire；

The supporter extended on the conductor wire and in the burial groove；

Stacked structure, including the multiple insulating layers and multiple conductive layers being alternately stacked on above support；

Channel structure passes through the stacked structure, above support and the conductor wire；With

Isolated groove passes through the stacked structure, above support and the conductor wire,

Wherein the burial groove is spaced apart with the isolated groove.

22. semiconductor devices according to claim 21, wherein above support includes:

Support plate on the conductor wire；With

The support bar connecting in the burial groove and with the support plate.

23. semiconductor devices according to claim 22, wherein the isolated groove is spaced apart with the support bar.

24. a kind of method for forming semiconductor devices, comprising:

Lower conductiving layer is formed on the substrate；

Mold layer is formed on the lower conductiving layer；

Groove is formed in the mold layer；

It is formed in the supporter extended in the mold layer and in the trench；

The primary stacked structure of the multiple insulating layers and multiple sacrificial layers including being alternately stacked is formed on above support；

Form the channel structure across the primary stacked structure, above support and the mold layer；

Form the isolated groove across the primary stacked structure, above support and the mold layer；

The mold layer is removed to form cavity；

Conductor wire is formed in the cavity；

The multiple sacrificial layer is removed to form multiple gap areas；With

Multiple conductive layers are formed in the multiple gap area,

The multiple insulating layer being wherein alternately stacked on above support and the multiple conductive layer constitute stacked structure.

25. it is according to claim 24 formed semiconductor devices method, wherein above support include:

Support plate on the conductor wire；With

In the trench and it is configured to the support pattern connecting with the support plate.

Technical field

It is related to including that the three-dimensional (3D) of supporter is partly led according to the Apparatus and method for of the example embodiment of present inventive concept Body device and forming method thereof.

Background technique

Partially due to the benefit of the high integration in semiconductor devices, has studied depositing using three-dimensional stacking structure Memory device.In such a configuration, sacrificial layer and stacked structure can be sequentially formed on substrate.It can be sacrificed by removal Layer forms gap area.Displacement electrode can be formed in gap area.It may occur during forming gap area All difficulties, such as the collapsing of stacked structure.

Summary of the invention

The example embodiment of present inventive concept is directed to a kind of method for providing 3D semiconductor devices and forming it, the 3D Semiconductor devices, which has, utilizes the rock-steady structure for simplifying technique.

The example embodiment conceived according to the present invention provides a kind of semiconductor devices, which is included in lining Lower conductiving layer on bottom.Conductor wire is on lower conductiving layer.Burial groove in conductor wire is provided.There is provided on conductor wire and Bury the supporter extended in groove.Stacked structure including the multiple insulating layers and multiple conductive layers that are alternately stacked is in supporter On.Channel structure across stacked structure, supporter and conductor wire is provided.It provides across stacked structure, supporter and conductor wire Isolated groove.

The example embodiment conceived according to the present invention provides a kind of semiconductor devices, which includes having The substrate of unit area and welding disking area.Lower conductiving layer is on substrate.Mold layer in welding disking area on lower conductiving layer is provided. There is provided in unit area on lower conductiving layer and with the essentially identical level of mold layer at conductor wire.There is provided in conductor wire and Multiple burial grooves in mold layer.The supporter for providing on conductor wire and mold layer and extending in the multiple burial groove. Stacked structure including the multiple insulating layers and multiple conductive layers that are alternately stacked is on a support.It provides across stacked structure, branch Support the cell channel structure of object and conductor wire.Illusory channel structure across stacked structure, supporter and mold layer is provided.Offer is worn Cross multiple isolated grooves of stacked structure, supporter and conductor wire.

The example embodiment conceived according to the present invention provides a kind of semiconductor devices, which includes having The substrate of unit area and the welding disking area adjacent with unit area.Lower conductiving layer is on substrate.There is provided in welding disking area Mold layer on lower conductiving layer.Conduction in unit area on lower conductiving layer and at the level essentially identical with mold layer is provided Line.It provides first in mold layer and extends burial groove.There is provided with first extend burial groove be spaced apart and in mold layer the Two extend burial groove.Supporter is provided, which extends mask trench and second on conductor wire and mold layer and first Extend and extends in mask trench.Stacked structure is provided, which includes the multiple insulating layers being alternately stacked on supporter With multiple conductive layers.Multiple cell channel structures across stacked structure, supporter and conductor wire are provided.Offer is prolonged across first Stretch bury groove and second extend bury groove between stacked structure, supporter and mold layer multiple illusory channel structures.It mentions For multiple isolated grooves across stacked structure, supporter and conductor wire.

The example embodiment conceived according to the present invention, a kind of semiconductor devices may include: lower conduction on substrate Layer；Conductor wire on lower conductiving layer；Burial groove in conductor wire；The branch extended on conductor wire and in burying groove Support object；Stacked structure, including the multiple insulating layers and multiple conductive layers being alternately stacked on supporter；Channel structure passes through heap Stack structure, supporter and conductor wire；And isolated groove, pass through stacked structure, supporter and conductor wire.Bury groove can with every It is spaced apart from groove.

The example embodiment conceived according to the present invention, provides a kind of method for forming semiconductor devices, and this method includes Lower conductiving layer is formed on the substrate.Mold layer is formed on lower conductiving layer.Groove is formed in mold layer.It is formed in mold layer and in ditch The supporter extended in slot.Formed on a support includes that the multiple insulating layers being alternately stacked and the primary of multiple sacrificial layers stack Structure.Form the channel structure across primary stacked structure, supporter and mold layer.It is formed across primary stacked structure, supporter With the isolated groove of mold layer.Cavity is formed by removal mold layer.Conductor wire is formed in the cavities.By removing the multiple sacrifice Layer forms multiple gap areas.Multiple conductive layers are formed in the multiple gap area.The institute being alternately stacked on a support It states multiple insulating layers and the multiple conductive layer constitutes stacked structure.

Detailed description of the invention

Fig. 1 is the layout of the 3D semiconductor devices of the example embodiment for describing to conceive according to the present invention.

Fig. 2 and Fig. 3 is the cross-sectional view of the 3D semiconductor devices of the example embodiment for describing to conceive according to the present invention, Fig. 4 to Figure 11 is the enlarged drawing that a part of Fig. 2 is shown in detail.

Figure 12 is the 3D semiconductor of example embodiment for describing to conceive according to the present invention to Figure 14, Figure 16 and Figure 18 The layout of device.

Figure 15, Figure 17 and Figure 19 are the 3D semiconductor of example embodiment for describing to conceive according to the present invention to Figure 22 The cross-sectional view of device.

Figure 23 to 25, Figure 28 are the example embodiment party for describing to conceive according to the present invention to Figure 35 and Figure 42 to Figure 46 The cross-sectional view of the method for the formation 3D semiconductor devices of formula.

Figure 26 and Figure 27 is the enlarged drawing that a part of Figure 25 is shown in detail, and Figure 36 is that Figure 35 is shown in detail to Figure 41 A part enlarged drawing.

Specific embodiment

Fig. 1 is the layout of the 3D semiconductor devices of the example embodiment for describing to conceive according to the present invention, Fig. 2 With the cross-sectional view that Fig. 3 is for describing 3D semiconductor devices.Fig. 2 is line I-I', II-II', III-III' and IV- along Fig. 1 The cross-sectional view of IV' interception, Fig. 3 are the cross-sectional views intercepted along the line V-V' of Fig. 1.Fig. 4 and Fig. 5 is the part that Fig. 2 is shown in detail The enlarged drawing of E3, Fig. 6, Fig. 8 and Figure 10 are the enlarged drawings that the part E1 of Fig. 2 is shown in detail, and Fig. 7, Fig. 9 and Figure 11 are in detail Show the enlarged drawing of the part E2 of Fig. 2.The 3D semiconductor devices for the example embodiment conceived according to the present invention may include all Such as vertical NAND (VNAND) or the nonvolatile memory of 3D flash memory.

With reference to Fig. 1, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, multiple Bury groove 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47, support pattern 31P, 31AP, 32P and 32AP, branch Stay 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B, multiple cell channel structure 69C, multiple illusory channel structure 69D, The first transistor 81, second transistor 82 and multiple isolated grooves 88,89 and 90.

Multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47 may include multiple first single Member bury groove 31, first tie up bury groove 31A, multiple second units bury groove 32, second tie up bury groove 32A, Third unit buries the extension burial extension burial of groove 41, second of groove 33, first groove 42, third extends burial groove 43, 4th, which extends the burial extension burial extension of groove the 45, the 6th of groove the 44, the 5th, buries groove 46 and the 7th extension burial groove 47.

Support pattern 31P, 31AP, 32P and 32AP may include that multiple first units support pattern 31P, first to tie up branch Support pattern 31AP, multiple second units support pattern 32P and second tie up support pattern 32AP.Support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include third unit support bar 33B, the first extension support bar 41B, the second extension support Article 42B, third extend support bar 43B, the 4th extend support bar 44B, the 5th extend support bar 45B, the 6th extend support bar 46B Extend support bar 47B with the 7th.

Multiple isolated grooves 88,89 and 90 may include the first isolated groove 88, the second isolated groove 89 and third isolation Groove 90.

With reference to Fig. 2, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include substrate 21, first Trap 23, the second trap 24, lower conductiving layer 25, mold layer 29, multiple burial grooves 31,31A, 32,32A, 33,41,42 and 43, supporter 50,31P, 32P, 33B, 41B, 42B and 43B, device isolation layer 53, gap filling layer 54, stacked structure 60, multiple cell channels Structure 69C, multiple illusory channel structure 69D, the first transistor 81, second transistor 82, etching stopping layer 83, the first interlayer are exhausted Edge layer 85, multiple isolated grooves 88,89 and 90, the second interlayer insulating film 87, displacement conductor wire 93, impurity range 97, insulation gap It is object 103, groove buried layer 105, third interlayer insulating film 106, selection line partition pattern 107, the 4th interlayer insulating film 108, more Insulating layer 121, multiple plugs 123 and bit line 125 between height position plug 113, a plurality of sub-bit-line 115, layer 5.

Supporter 50,31P, 32P, 33B, 41B, 42B and 43B may include support plate 50, support pattern 31P and 32P with And support bar 33B, 41B, 42B and 43B.Stacked structure 60 may include the multiple insulating layers 61 and multiple conductive layers being alternately stacked 95.Each of multiple cell channel structure 69C and multiple illusory channel structure 69D may include information storage pattern 64, ditch Road pattern 65, core pattern 66 and the first pad 67.Channel pattern 65 can be on the outside of core pattern 66 (for example, surrounding core figure The outside of case 66).Information stores pattern 64 can be on the outside of channel pattern 65 (for example, around the outer of channel pattern 65 Side).As shown in Figure 1, substrate 21 may include unit area CEL, adjacent unit region CEL (for example, with unit area CEL Side surface is continuous) welding disking area EXT and the peripheral region PERI that is arranged in outside unit area CEL and welding disking area EXT.

With reference to Fig. 3, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include substrate 21, under lead It is electric layer 25, mold layer 29, multiple burial grooves 41,42 and 43, supporter 50,41B, 42B and 43B, stacked structure 60, multiple illusory Channel structure 69D, the first interlayer insulating film 85, multiple isolated grooves 88 and 89, the second interlayer insulating film 87, impurity range 97, absolutely Pattern 107, the 4th interlayer insulating film is isolated in insulating divider 103, groove buried layer 105, third interlayer insulating film 106, selection line Insulating layer 121 between 108 and layer 5.

With reference to Fig. 4, each of multiple cell channel structure 69C and multiple illusory channel structure 69D may include information Store pattern 64, channel pattern 65 and core pattern 66.It may include tunnel insulation layer 64T, charge storage that information, which stores pattern 64, Layer 64E, the first barrier layer 64B and the second barrier layer 64B2.

With reference to Fig. 5, in some embodiments, it may include tunnel insulation layer 64T, charge storage that information, which stores pattern 64, Layer 64E and the first barrier layer 64B, but can be omitted the second barrier layer 64B2.

With reference to Fig. 6, multiple second units, which bury groove 32, can pass through displacement conductor wire 93.Multiple second unit support figures Case 32P can be formed in multiple second units and bury in groove 32.Second isolated groove 89 can pass through multiple insulating layers 61, Gap filled layer 54 and multiple second units support pattern 32P.The lower end of multiple second unit support pattern 32P can be with lower conduction Layer 25 directly contacts.Multiple second unit support pattern 32P can be continuous with support plate 50 (for example, integral).Impurity range 97 It can be set below the second isolated groove 89.Impurity range 97 can be formed in lower conductiving layer 25.Replacing conductor wire 93 can be with Across information storage pattern 64 directly to be contacted with the side surface of channel pattern 65.Replacing conductor wire 93 can be in 50 He of support plate Extend between channel pattern 65 and between lower conductiving layer 25 and channel pattern 65.Although referred to as displacement conductor wire 93, but Term " displacement " is only used for identifying purpose, it is no intended to it is required that any specific feature of conductor wire.Replacing conductor wire 93 can also be with Referred to as conductor wire.

With reference to Fig. 7, second, which extends burial groove 42, can pass through mold layer 29.Second extension support bar 42B can be formed in Second extends in burial groove 42.The lower end of second extension support bar 42B can directly be contacted with lower conductiving layer 25.Mold layer 29 can To be retained between lower conductiving layer 25 and support plate 50.Mold layer 29 may include lower mold layer 29A, centre mold layer 29M and upper mold layer 29C。

Referring again to Fig. 1 to Fig. 7, in some embodiments, lower conductiving layer 25 can be set in substrate 21 or substrate On 21.Lower conductiving layer 25 can be formed in unit area CEL and welding disking area EXT.Displacement conductor wire 93 can be set in list On lower conductiving layer 25 in first region CEL.Mold layer 29 can be set on the lower conductiving layer 25 in welding disking area EXT.Displacement is led Electric wire 93 can be formed in the level essentially identical with mold layer 29.Multiple burial grooves 31,31A, 32,32A, 33,41,42,43, 44,45,46 and 47 displacement conductor wire 93 and mold layer 29 can be passed through.Supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be formed in displacement conductor wire 93 and mold layer 29 on, and can multiple burial grooves 31, Extend in 31A, 32,32A, 33,41,42,43,44,45,46 and 47.Due to supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be in multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47 Middle extension, thus they be shown in Figure 1 for it is associated with identical indicator.

The stacked structure 60 that plurality of insulating layer 61 and multiple conductive layers 95 are alternately stacked can be set supporter 50, On 31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.Multiple cell channel structure 69C can be passed through and be stacked knot At least some of structure 60, supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B and displacement are led Electric wire 93.Multiple illusory channel structure 69D can pass through stacked structure 60, supporter 50,31P, 32P, 33B, 41B, 42B, At least some of 43B, 44B, 45B, 46B and 47B and mold layer 29.Multiple isolated grooves 88,89 and 90 can be set to wear Cross stacked structure 60, supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B, displacement 93 and of conductor wire Mold layer 29.In some embodiments, each of multiple cell channel structure 69C can be interpreted channel structure.

Multiple first units bury grooves 31, first tie up bury groove 31A, multiple second units bury groove 32, the Two, which tie up burial groove 32A and third unit burial groove 33, can be formed in the CEL of unit area.First extends burial groove 41, groove 42 is buried in the second extension, third extension buries the extension burial groove the 44, the 5th of groove the 43, the 4th and extends burial groove 45, groove 46 is buried in the 6th extension and the 7th extension is buried groove 47 and can be formed in welding disking area EXT.

Multiple first units bury grooves 31 and can be separated from each other and each other (for example, linearly) right in the row direction It is quasi-.First ties up to bury groove 31A and can be formed in multiple first units and buries between some in grooves 31.First ties up and covers (for example, in the row direction) width of buried channel slot 31A can be greater than multiple first units and bury width in each of groove 31 Degree.Multiple second units bury groove 32 and can be spaced apart with multiple first units burial groove 31 and be parallel to multiple first Unit buries groove 31.Multiple second units bury groove 32 and can be separated from each other and in the row direction each other (for example, line Property) alignment.The second unit that second, which ties up burial groove 32A, can be formed in multiple second units burial grooves 32 is buried Between groove 32.Third unit burial groove 33 can be formed in multiple first units burial grooves 31 and multiple second units are covered Between buried channel slot 32.In some embodiments, third unit, which buries groove 33, can bury groove 31 in multiple first units And multiple second units are buried between groove 32, and in some embodiments, bury 31 He of groove in multiple first units Multiple second units are buried placed in the middle between groove 32.Third unit, which buries groove 33, can have bar shaped or groove shapes.

First extends the burial extension burial of groove 41, second groove 42, the extension burial of groove the 43, the 4th is buried in third extension Groove the 44, the 5th extend bury groove the 45, the 6th extend bury groove 46 and the 7th extend bury each of groove 47 can be with With bar shaped or groove shapes.First, which extends burial groove 41, to exist in the row direction with multiple first units burial groove 31 It is aligned on identical extension line.Second, which extends burial groove 42, to exist in the row direction with multiple second units burial groove 32 It is aligned on identical extension line.Second extends to bury groove 42 and can extend with first and buries groove 41 and be spaced apart and be parallel to the One extends burial groove 41.Third, which extends burial groove 43, can be formed in the first extension burial groove 41 and the second extension burial Between groove 42.In some embodiments, third, which extends burial groove 43, can extend burial groove 41 and second first Extend and bury between groove 42, and in some embodiments, extends burial groove 41 first and ditch is buried in the second extension It is placed in the middle between slot 42.Third extends burial groove 43 can bury groove 33 in identical extension with third unit in the row direction It is aligned on line.Third, which extends burial groove 43, can bury the connection of groove 33 (for example, connection) with third unit.

Groove 44 is buried in 4th extension and the 5th extension burial groove 45 can be with unit area CEL and welding disking area EXT Between boundary be adjacent to be formed.4th, which extends burial groove 44, can be formed in the first extension burial groove 41 and third extension It buries between groove 43.4th, which extends burial groove 44, can bury groove 43 with the first extension burial groove 41 and third extension Connection (for example, connection).5th, which extends burial groove 45, can be formed in the second extension burial groove 42 and third extension burial Between groove 43.5th extension is buried groove 45 and can be connected to the second extension burial groove 42 and third extension burial groove 43 (for example, connection).

Groove 46 is buried in 6th extension and the 7th extension burial groove 47 can landform adjacent with the edge of welding disking area EXT At.In some embodiments, groove 46 is buried in the 6th extension and the 7th extension burial groove 47 can be with welding disking area EXT's The opposite edge in boundary between unit area CEL and welding disking area EXT is adjacent to be formed.6th extends burial 46 He of groove 7th extend bury groove 47 can be set away from the boundary between unit area CEL and welding disking area EXT relatively far away from away from From place.6th, which extends burial groove 46, can be formed between the first extension burial groove 41 and third extension burial groove 43. 6th extension is buried groove 46 and can be connected to the first extension burial groove 41 and third extension burial groove 43 (for example, even It connects).6th, which extends burial groove 46, can extend burial groove 44 relatively with the 4th.7th, which extends burial groove 47, to form Extend second and buries between groove 42 and third extension burial groove 43.7th extends burial groove 47 can extend with second It buries groove 42 and is connected to (for example, connection) with third extension burial groove 43.7th extends burial groove 47 can prolong with the 5th It stretches and buries groove 45 relatively.

Multiple cell channel structure 69C, which can be set, buries groove 31 and the burial of multiple second units in multiple first units Between groove 32.Multiple illusory channel structure 69D, which can be set to extend first, buries groove 41 and the second extension burial groove Between 42.

Supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include support plate 50, support Pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.Support plate 50 can be with It is formed in unit area CEL and welding disking area EXT.Support plate 50 can be set on displacement conductor wire 93 and mold layer 29.Branch Support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be set Multiple burial grooves 31,31A, 32, in 32A, 33,41,42,43,44,45,46 and 47, and can be continuous with support plate 50 (for example, integral).

Multiple isolated grooves 88,89 and 90 can pass through supporter 50,31P, 32P, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.Multiple isolated grooves 88,89 and 90 can pass through support plate 50, support pattern 31P, 31AP, 32P and At least some of 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.

Support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B It may include material identical with support plate 50.Such as support plate 50, support pattern 31P, 31AP, 32P and 32AP and support 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include polysilicon.Support pattern 31P, 31AP, 32P and 32AP Lower end and the lower end of support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can directly be contacted with lower conductiving layer 25. Displacement conductor wire 93 can directly be contacted with lower conductiving layer 25 and support plate 50.Information storage figure can be passed through by replacing conductor wire 93 Case 64 with the side surface of channel pattern 65 directly to contact.

Multiple first unit support pattern 31P, first tie up support pattern 31AP, multiple second units support pattern 32P Support pattern 32AP is tied up with second can be separately positioned on multiple first units bury grooves 31, first tie up burial groove 31A, multiple second unit grooves are buried groove 32 and second and are tied up in burial groove 32A.Third unit support bar 33B, first Extend support bar 41B, the second extension support bar 42B, third and extends support bar 43B, the 4th extension support bar 44B, the 5th extension Support bar 45B, the 6th extension support bar 46B and the 7th extension support bar 47B can be respectively arranged at third unit bury groove 33, First extends the burial extension burial of groove 41, second groove 42, the extension burial of groove the 43, the 4th groove 44 is buried in third extension, 5th extension is buried groove the 45, the 6th and is extended in burial groove 46 and the 7th extension burial groove 47.

First isolated groove 88 can pass through multiple first units support pattern 31P, first tie up support pattern 31AP and First extends support bar 41B.Second isolated groove 89 can pass through multiple second units and pattern 32P, second is supported to tie up support Pattern 32AP and second extends support bar 42B.Third isolated groove 90 can pass through a part that third extends support bar 43B.

With reference to Fig. 8, in some embodiments, lower mold layer 29A can be partially remaining in multiple second unit support figures Between case 32P and lower conductiving layer 25.Replace conductor wire 93 can multiple second units support pattern 32P and lower conductiving layer 25 it Between extend.Insulation spacer 103 can be supported in multiple second units to be extended between pattern 32P and lower conductiving layer 25.Lower mold layer 29A can be plugged between insulation spacer 103 and displacement conductor wire 93.

With reference to Fig. 9, in some embodiments, lower mold layer 29A can extend support bar 42B and lower conductiving layer 25 second Between extend.Insulation spacer 103 can extend between the second extension support bar 42B and lower conductiving layer 25.

With reference to Figure 10, in some embodiments, lower mold layer 29A can be partially remaining in multiple second unit support figures Between case 32P and lower conductiving layer 25.Replace conductor wire 93 can multiple second units support pattern 32P and lower conductiving layer 25 it Between extend.

With reference to Figure 11, in some embodiments, lower mold layer 29A can extend support bar 42B and lower conductiving layer second Extend between 25.

In some embodiments, it is similar to Fig. 8 to Figure 11, lower mold layer 29A can be partially remaining in support pattern Between 31P, 31AP, 32P and 32AP and lower conductiving layer 25 and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B Between lower conductiving layer 25.

Figure 12 to Figure 14 is the layout for describing the 3D semiconductor devices according to example embodiment, and Figure 15 is along figure The cross-sectional view of 14 line VI-VI' interception.

With reference to Figure 12, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, more A burial groove 31,31A, 32,32A, 33,41,42,43,44 and 45, support pattern 31P, 31AP, 32P and 32AP, support bar 33B, 41B, 42B, 43B, 44B and 45B, multiple cell channel structure 69C, multiple illusory channel structure 69D and multiple isolation Groove 88,89 and 90.

Multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44 and 45 may include that multiple first units are buried Groove 31, first are tied up and bury groove 31A, multiple second units bury groove 32, second ties up burial groove 32A, third list Groove 42 is buried in the member burial extension burial extension of groove 41, second of groove 33, first, third extension burial groove the 43, the 4th prolongs It stretches and buries groove 44 and the 5th extension burial groove 45.Support bar 33B, 41B, 42B, 43B, 44B and 45B may include third unit Support bar 33B, first extend support bar 41B, the second extension support bar 42B, third and extend support bar 43B, the 4th extension support Article 44B and the 5th extends support bar 45B.As shown in Figure 12, the embodiment of Figure 12 can not include shown in Fig. 1 at least 6th, which extends the burial extension burial groove the 47, the 6th of groove the 46, the 7th extension support bar 46B and the 7th, extends support bar 47B.

With reference to Figure 13, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, more A burial groove 31,31A, 32,32A, 33,41,42 and 43, support pattern 31P, 31AP, 32P and 32AP, support bar 33B, 41B, 42B and 43B, multiple cell channel structure 69C, multiple illusory channel structure 69D and multiple isolated grooves 88,89 and 90。

Multiple burial grooves 31,31A, 32,32A, 33,41,42 and 43 may include multiple first units bury grooves 31, First ties up burial groove 31A, multiple second units bury groove 32, second ties up burial groove 32A, third unit buries ditch Slot 33, first extends the burial extension of groove 41, second burial groove 42 and groove 43 is buried in third extension.Support bar 33B, 41B, 42B and 43B may include that third unit support bar 33B, the first extension support bar 41B, the second extension support bar 42B and third extend Support bar 43B.As shown in Figure 13, the embodiment of Figure 13 can not include that ditch is buried in at least the 4th extension shown in Figure 12 Slot the 44, the 5th, which extends, buries the extension of extension support bar 44B and the 5th of groove the 45, the 4th support bar 45B.

With reference to Figure 14 and Figure 15, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, multiple burial grooves 31,31A, 32,32A, 41,42,43,44,45,46 and 47, support pattern 31P, 31AP, 32P and 32AP, support bar 41B, 42B, 43B, 44B, 45B, 46B and 47B, multiple cell channel structure 69C, multiple illusory channel structures 69D and multiple isolated grooves 88,89 and 90.

Multiple burial grooves 31,31A, 32,32A, 41,42,43,44,45,46 and 47 may include that multiple first units are covered Buried channel slot 31, first are tied up and bury groove 31A, multiple second units bury groove 32, second ties up burial groove 32A, first Extend the burial extension burial of groove 41, second groove 42, the extension burial groove the 44, the 5th of groove the 43, the 4th is buried in third extension Extend the burial extension of groove the 45, the 6th burial groove 46 and groove 47 is buried in the 7th extension.

Support pattern 31P, 31AP, 32P and 32AP may include that multiple first units support pattern 31P, first to tie up branch Support pattern 31AP, multiple second units support pattern 32P and second tie up support pattern 32AP.Support bar 41B, 42B, 43B, 44B, 45B, 46B and 47B may include the first extension support bar 41B, second extend support bar 42B, third extend support bar 43B, 4th, which extends support bar 44B, the 5th extension support bar 45B, the 6th extension support bar 46B and the 7th, extends support bar 47B.Such as figure Shown in 14 and Figure 15, the embodiment of Figure 14 and 15 can not include that at least third unit buries groove 33 shown in Fig. 1 and 2 With third unit support bar 33B.

Figure 16 is the layout for describing the 3D semiconductor devices according to example embodiment, and Figure 17 is the line along Figure 16 The cross-sectional view of VII-VII' interception.

With reference to Figure 16 and Figure 17, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, multiple burial grooves 33,41,42,43,44,45,46 and 47, support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B, multiple cell channel structure 69C, multiple illusory channel structure 69D and multiple isolated grooves 88,89 and 90.

Multiple burial grooves 33,41,42,43,44,45,46 and 47 may include that third unit is buried groove 33, first prolonged Stretch the burial extension burial of groove 41, second groove 42, third extends the burial extension burial groove the 44, the 5th of groove the 43, the 4th and prolongs It stretches and buries the extension of groove the 45, the 6th burial groove 46 and the 7th extension burial groove 47.In some embodiments, third unit Unit burial groove can be referred to as by burying groove 33.

Support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include third unit support bar 33B, first prolong It stretches support bar 41B, the second extension support bar 42B, third and extends support bar 43B, the 4th extension support bar 44B, the 5th extension branch Stay 45B, the 6th extend support bar 46B and the 7th and extend support bar 47B.As shown in Figure 16 and Figure 17, the reality of Figure 16 and Figure 17 The mode of applying can not include Fig. 1 and at least the multiple first unit shown in Figure 2 buries groove 31, first ties up burial ditch Slot 31A, the multiple second unit burial groove 32, second, which are tied up, buries groove 32A, the multiple first unit support pattern 31P, first, which are tied up, supports pattern 31AP, the multiple second unit support pattern 32P and second to tie up support pattern 32AP.

Figure 18 is the layout for describing the 3D semiconductor devices according to example embodiment, and Figure 19 is the line along Figure 18 The cross-sectional view of VIII-VIII' interception.

With reference to Figure 18 and Figure 19, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include mold layer 29, multiple burial grooves 41,42,43,44,45,46 and 47, support bar 41B, 42B, 43B, 44B, 45B, 46B and 47B, multiple Cell channel structure 69C, multiple illusory channel structure 69D and multiple isolated grooves 88,89 and 90.

Multiple burial grooves 41,42,43,44,45,46 and 47 may include that the extension of groove 41, second is buried in the first extension Bury groove 42, third extension burial groove the 43, the 4th extends burial groove the 44, the 5th and extends the burial extension of groove the 45, the 6th It buries groove 46 and the 7th and extends burial groove 47.Support bar 41B, 42B, 43B, 44B, 45B, 46B and 47B may include first prolonging It stretches support bar 41B, the second extension support bar 42B, third and extends support bar 43B, the 4th extension support bar 44B, the 5th extension branch Stay 45B, the 6th extend support bar 46B and the 7th and extend support bar 47B.As shown in Figures 18 and 19, the implementation of Figure 18 and Figure 19 Mode can not include Fig. 1 and at least the multiple first unit shown in Figure 2 buries groove 31, first ties up burial groove 31A, the multiple second unit burial groove 32, second are tied up and bury groove 32A, third unit buries groove 33, described more A first unit support pattern 31P, first tie up support pattern 31AP, the multiple second unit support pattern 32P, the second bundle Prick support pattern 32AP and third unit support bar 33B.

Figure 20 to Figure 22 is the section view of the 3D semiconductor devices of the example embodiment for describing to conceive according to the present invention Figure.

With reference to Figure 20, according to the present invention the 3D semiconductor devices for the example embodiment conceived may include substrate 21, under Conductive layer 25, multiple burial grooves 31,32 and 33, supporter 50,31P, 32P and 33B, gap filling layer 54, first stack knot Structure 60, the second stacked structure 160, multiple first unit channel structure 69C, multiple second unit channel structure 169C, it is multiple every From groove 88 and 89, the second interlayer insulating film 87, displacement conductor wire 93, impurity range 97, insulation spacer 103, groove buried layer 105, third interlayer insulating film 106, selection line partition pattern 107, the 4th interlayer insulating film 108, multiple sub- position plugs 113, more Insulating layer 121, multiple plugs 123 and bit line 125 between a sub-bit-line 115, layer 5.The example conceived according to the present invention is implemented The 3D semiconductor devices of mode can be interpreted as including dual-stack structure.

Second stacked structure 160 may include the multiple second insulating layers 161 being alternately stacked and multiple second conductive layers 195.Multiple first unit channel structure 69C may include first information storage pattern 64, the first channel pattern 65, the first core figure Case 66 and the first pad 67A.Multiple second unit channel structure 169C may include the second information storage pattern 164, the second ditch Road pattern 165, the second core pattern 166 and the second pad 167.Second channel pattern 165 can be connected to via the first pad 67A First channel pattern 65.In some embodiments, it is convenient to omit the first pad 67A.

With reference to Figure 21, multiple first unit channel structure 69C may include first information storage pattern 64, the first channel figure Case 65 and the first core pattern 66.Multiple second unit channel structure 169C may include the second information storage pattern 164, the second ditch Road pattern 165, the second core pattern 166 and the second pad 167.Second channel pattern 165 may be coupled to the first channel pattern 65. Second core pattern 166 may be coupled to the first core pattern 66.

With reference to Figure 22, the 3D semiconductor devices for the example embodiment conceived according to the present invention may include substrate 21, Peripheral interlayer interconnection 217, peripheral circuit interconnection 219, lower conductiving layer 225, multiple burial grooves 31,32 and 33, supporter 50, 31P, 32P and 33B, device isolation layer 53, gap filling layer 54, stacked structure 60, multiple cell channel structures 69C, Duo Gejing Body pipe 212, lower interlayer insulating film 215, multiple isolated grooves 88 and 89, the second interlayer insulating film 87, is set etching stopping layer 213 Conductor wire 93, impurity range 97, insulation spacer 103, groove buried layer 105, third interlayer insulating film 106, selection line is changed to separate It is insulating layer 121 between pattern 107, the 4th interlayer insulating film 108, multiple sub- position plugs 113, multiple sub-bit-lines 115, layer 5, more A plug 123 and bit line 125.Supporter 50,31P, 32P and 33B may include support plate 50, support pattern 31P and 32P, with And support bar 33B.The 3D semiconductor devices for the example embodiment conceived according to the present invention can be interpreted as including outer place Unit (COP) structure.

In some embodiments, groove buried layer 105 may include insulating layer.Displacement conductor wire 93 can be led under Electric layer 225 is electrically connected to peripheral circuit interconnection 219.Lower conductiving layer 225 may include that there are the multiple of different conduction-types partly to lead Body layer.

Figure 23 is the embodiment for describing to conceive according to the present invention to Figure 25, Figure 28 to Figure 35 and Figure 42 to Figure 46 Formation 3D semiconductor devices method cross-sectional view.Figure 26 and Figure 27 is the enlarged drawing for being shown specifically a part of Figure 25, figure 36, Figure 38 and Figure 40 is the enlarged drawing for being shown specifically the part E4 of Figure 35, and Figure 37, Figure 39 and Figure 41 are be shown specifically Figure 35 one The enlarged drawing of part E5.Figure 23 is line I-I', II-II', III- in Fig. 1 to Figure 25, Figure 28 to Figure 35 and Figure 42 to Figure 46 The cross-sectional view of III' and IV-IV' interception.

With reference to Fig. 1 and Figure 23, the first trap 23, the second trap 24 and lower conduction can be formed in presumptive area in the substrate 21 Layer 25.The upper surface of the second trap 24 and the upper surface of lower conductiving layer 25 can be etched so that it is to lower recess.

Substrate 21 may include semiconductor substrate, such as silicon wafer or silicon-on-insulator (SOI) chip.For example, substrate 21 It can be p type single crystal silicon chip.First trap 23, the second trap 24 and lower conductiving layer 25 can be p-type or N-type conduction type.Second Trap 24 can be and the identical conduction type of the first trap 23 or the conduction type different with the first trap 23.Lower conductiving layer 25 can be Conduction type identical with the first trap 23 or the second trap 24, first trap 23 or the second trap 24 can be with lower conductiving layers 25 simultaneously It is formed.For example, lower conductiving layer 25 may include p type single crystal silicon.

Substrate 21 may include the pad of unit area CEL, (for example, continuous) adjacent with the side surface of unit area CEL The region EXT and peripheral region PERI being arranged in outside unit area CEL and welding disking area EXT.Lower conductiving layer 25 can be with shape At in unit area CEL and welding disking area EXT.In some embodiments, lower conductiving layer 25 can be defined as in unit (for example, the substrate in capping unit region CEL and welding disking area EXT on substrate 21 in region CEL and welding disking area EXT 21).In some embodiments, lower conductiving layer 25 may include the semiconductor layer of such as polysilicon.First trap 23 and the second trap 24 can be formed in peripheral region PERI.The technique for etching the upper surface of the second trap 24 and lower conductiving layer 25 may include buffering Layer formation process and Patternized technique, but for simplicity, buffer layer formation process and Patternized technique will be omitted.Second The upper surface of trap 24 and the upper surface of lower conductiving layer 25 can be formed in the level lower than the upper surface of the first trap 23.

With reference to Fig. 1 and Figure 24, first grid dielectric layer 27, second grid dielectric layer 28 and mold layer 29 can be formed. Mold layer 29 may include lower mold layer 29A, centre mold layer 29M and the upper mold layer 29C that sequence stacks.

Mold layer 29 can be formed as on the lower conductiving layer 25 in unit area CEL and welding disking area EXT, and some Lower conductiving layer 25 in embodiment, in capping unit region CEL and welding disking area EXT.Mold layer 29 may include such as oxide, Nitride, semiconductor or combinations thereof.Mold layer 29 may include the material for having etching selectivity relative to lower conductiving layer 25.It is intermediate Mold layer 29M may include the material for having etching selectivity relative to lower conductiving layer 25, lower mold layer 29A and upper mold layer 29C.Example Such as, lower mold layer 29A may include Si oxide, and intermediate mold layer 29M may include silicon nitride, and upper mold layer 29C may include silicon Oxide.Intermediate mold layer 29M can be thicker than lower mold layer 29A or upper mold layer 29C.

First grid dielectric layer 27 can be formed on the first trap 23, and second grid dielectric layer 28 can be formed in On two traps 24.Second grid dielectric layer 28 can be thicker than first grid dielectric layer 27.In some embodiments, the first grid Pole dielectric layer 27 may include and with (it can be same with first grid dielectric layer 27 with lower mold layer 29A or upper mold layer 29C When formed) the identical material layer of material layer of essentially identical thickness.Second grid dielectric layer 28 may include such as silicon oxidation Object, silicon nitride, silicon-oxygen nitride, high-k dielectrics material or combinations thereof.

With reference to Fig. 1 and Figure 25, mold layer 29 can be patterned, so as to formed multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47.Multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47 can It is tied up including multiple first units burial groove 31, first and buries groove 31A, multiple second units are buried groove 32, second and tied Bundle burial groove 32A, third unit bury the extension burial extension burial of groove 41, second of groove 33, first groove 42, third is prolonged The burial extension burial extension burial extension burial groove 46 and the 7th of groove the 45, the 6th of groove the 44, the 5th of groove the 43, the 4th is stretched to prolong It stretches and buries groove 47.

With reference to Figure 26, each of multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47 Mold layer 29 can be passed completely through.The upper surface of lower conductiving layer 25 can multiple burial grooves 31,31A, 32,32A, 33,41, 42,43,44,45,46 and 47 bottom-exposed.Figure 26 shows the example that first unit buries one of groove 31.For example, multiple First unit, which buries each of groove 31, can pass through upper mold layer 29C, centre mold layer 29M and lower mold layer 29A, and lower conduction It the upper surface of layer 25 can be in the bottom-exposed of multiple first units burial groove 31.

With reference to Figure 27, each of multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47 can Partially across mold layer 29.In some embodiments, the upper surface of lower mold layer 29A can multiple burial grooves 31, 31A, 32, the bottom-exposeds of 32A, 33,41,42,43,44,45,46 and 47.Figure 27 show first unit bury groove 31 it One example.For example, multiple first units, which bury each of groove 31, can pass through upper mold layer 29C and intermediate mold layer 29M, and And the upper surface of lower mold layer 29A can be in the bottom-exposed of multiple first units burial groove 31.

With reference to Fig. 1 and Figure 28, can be formed in unit area CEL and welding disking area EXT supporter 50,31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B, and peripheral gate can be formed in peripheral region PERI Electrode layer 51.

Supporter 50,31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include phase There is the material of etching selectivity for mold layer 29.For example, supporter 50,31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include polysilicon.Peripheral gate electrode layer 51 may include with supporter 50,31P, 31AP, The material of 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B (it can be formed simultaneously with peripheral gate electrode layer 51) Expect identical material.Peripheral gate electrode layer 51 can be formed in first grid dielectric layer 27 and second grid dielectric layer 28 On.

Supporter 50,31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include support Plate 50, support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.Branch Fagging 50 can be in the mold layer 29 in unit area CEL and welding disking area EXT, and in some embodiments, and covering is single Mold layer 29 in first region CEL and welding disking area EXT.Support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be continuous (for example, integral) with the side surface of support plate 50.Support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be formed in the multiple cover In buried channel slot 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47.Support pattern 31P, 31AP, 32P and 32AP and Support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can with multiple burial grooves 31,31A, 32,32A, 33,41, 42,43,44,45,46 and 47 bottom and side wall directly contacts.In some embodiments, pattern 31P, 31AP, 32P are supported It can be direct with the upper surface of lower conductiving layer 25 with 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B Contact.In some embodiments, support pattern 31P, 31AP, 32P and 32AP and support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can directly be contacted with the upper surface of lower mold layer 29A.

Support pattern 31P, 31AP, 32P and 32AP may include be formed in multiple first units bury it is more in grooves 31 A first unit support pattern 31P, it is formed in first and ties up first buried in groove 31A and tie up support pattern 31AP, formed It buries multiple second units support pattern 32P in groove 32 in multiple second units and is formed in second and tie up burial ditch Second in slot 32A ties up support pattern 32AP.Support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B may include shape At third unit bury groove 33 in third unit support bar 33B, be formed in the first extension bury groove 41 in first Extend support bar 41B, be formed in the second extension bury groove 42 in second extension support bar 42B, be formed in third extension cover Third in buried channel slot 43 extend support bar 43B, be formed in the 4th extension bury in groove 44 the 4th extend support bar 44B, Be formed in the 5th extension bury the 5th extension support bar 45B in groove 45, be formed in the 6th extension bury in groove 46 the Six extension support bar 46B, the 7th be formed in the 7th extension burial groove 47 extend support bar 47B.

With reference to Fig. 1 and Figure 29, device isolation layer 53 can be formed in peripheral region PERI, and can be in supporter 50, gap filling layer 54 is formed on 31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B, it can To fill multiple burial grooves 31,31A, 32,32A, 33,41,42,43,44,45,46 and 47.Device isolation layer 53 and gap are filled out Filling each of layer 54 may include insulating materials, such as Si oxide, silicon nitride, silicon nitrogen oxides or combinations thereof. It the upper surface of gap filling layer 54 and support plate 50 can be in the exposure of essentially identical surface.

With reference to Fig. 1 and Figure 30, can supporter 50,31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, Form plurality of insulating layer 61 on 45B, 46B and 47B and gap filling layer 54 and multiple sacrificial layers 62 are alternately stacked just Grade stacked structure 60T.Multiple sacrificial layers 62 may include the material for having etching selectivity relative to multiple insulating layers 61.Example Such as, multiple insulating layers 61 may include the oxide of such as Si oxide, and multiple sacrificial layers 62 may include such as silicon nitride Nitride.Lowest level in primary stacked structure 60T can be the lowest level in multiple insulating layers 61, primary stacked structure Top layer in 60T can be the top layer in multiple insulating layers 61.Primary stacked structure 60T extends to peripheral region In PERI.

With reference to Fig. 1 and Figure 31, Patternized technique, which can be used, makes the part primary stacked structure 60T in welding disking area EXT Ground recess.Although the primary stacked structure 60T in welding disking area EXT is portion concave, external zones can be completely removed Primary stacked structure 60T in the PERI of domain.First source/drain regions 71, the lower gate electrode 73 in the second source/drain regions 72, first, Gate electrode 76 on gate electrode 75, second on second lower gate electrode 74, first, the first overlay pattern 77, the second overlay pattern 78, the One grid spacer 79, second grid spacer 80 and etching stopping layer 83 can be formed in peripheral region PERI.The first grid Pole dielectric layer 27 can be retained between the first trap 23 and the first lower gate electrode 73.Second grid dielectric layer 28 can retain Under the second trap 24 and second between gate electrode 74.

The first interlayer insulating film 85 can be formed on etching stopping layer 83 and primary stacked structure 60T.First interlayer is exhausted Edge layer 85 may include oxide, such as Si oxide.The technique for forming the first interlayer insulating film 85 may include that film is formed Technique and flatening process.The upper surface of first interlayer insulating film 85 and the upper surface of primary stacked structure 60T can be basic Exposure at identical surface.First interlayer insulating film 85 can on the primary stacked structure 60T in welding disking area EXT, and In some embodiments, the primary stacked structure 60T in welding disking area EXT is covered.

Multiple cell channel structure 69C can be formed in the CEL of unit area, and multiple illusory channel structure 69D can To be formed in welding disking area EXT.Some in multiple cell channel structure 69C can pass completely through primary stacked structure 60T, Support plate 50 and mold layer 29, and can be formed in lower conductiving layer 25.Other unit ditches in multiple cell channel structure 69C Road structure can pass completely through primary stacked structure 60T and third unit support bar 33B, and can be formed in lower conductiving layer 25 It is interior.Some in multiple illusory channel structure 69D can pass completely through the first interlayer insulating film 85, primary stacked structure 60T, branch Fagging 50 and mold layer 29, and can be formed in lower conductiving layer 25.Other illusory channels in multiple illusory channel structure 69D Structure can pass completely through the first interlayer insulating film 85, primary stacked structure 60T and third extend support bar 43B, and can be with It is formed in lower conductiving layer 25.

Each of multiple cell channel structure 69C and multiple illusory channel structure 69D may include information storage pattern 64, Channel pattern 65, core pattern 66 and the first pad 67.Channel pattern 65 can on the side surface and bottom of core pattern 66 (example Such as, around the side surface and bottom of core pattern 66).First pad 67 can be formed in 65 top of channel pattern.Core pattern 66 can To include insulating materials, such as Si oxide, silicon nitride, silicon nitrogen oxides or combinations thereof.Channel pattern 65 can wrap Include semiconductor layer, such as polysilicon.For example, channel pattern 65 may include p-type polysilicon layer.First pad 67 can be with Channel pattern 65 directly contacts.First pad 67 may include semiconductor layer, such as polysilicon.For example, the first pad 67 It may include N-type polycrystalline silicon layer.In some embodiments, the first pad 67 may be used as drain region.In some embodiments In, the first pad 67 may include conductive material, such as metal silicide, metal, metal nitride, metal oxide or A combination thereof.

Information stores pattern 64 can be on the outside of channel pattern 65 (for example, the outside for surrounding channel pattern 65).In In some embodiments, as shown in figure 5, information storage pattern 64 may include tunnel insulation layer 64T, charge storage layer 64E and First barrier layer 64B.Tunnel insulation layer 64T can directly be contacted with channel pattern 65.Charge storage layer 64E can be plugged on tunnel Between road insulating layer 64T and the first barrier layer 64B.First barrier layer 64B can be set to be deposited in primary stacked structure 60T and charge Between reservoir 64E.In some embodiments, tunnel insulation layer 64T may include such as Si oxide, charge storage layer 64E It may include such as silicon nitride, the first barrier layer 64B may include such as Si oxide, silicon nitride, silicon nitrogen oxides, height K dielectric material or combinations thereof.

Grid on gate electrode 73, first under first trap 23, first grid dielectric layer 27, the first source/drain regions 71, first Electrode 75, the first overlay pattern 77 and first grid spacer 79 may be constructed the first transistor 81.The first transistor 81 can be with It is low voltage transistor.Second trap 24, second grid dielectric layer 28, the lower gate electrode 74 in the second source/drain regions 72, second, the Gate electrode 76, the second overlay pattern 78 and second grid spacer 80 may be constructed second transistor 82 on two.Second transistor 82 can be high voltage transistor.

With reference to Fig. 1 and Figure 32, it is exhausted the second interlayer can be formed on primary stacked structure 60T and the first interlayer insulating film 85 Edge layer 87.Second interlayer insulating film 87 can on multiple cell channel structure 69C and multiple illusory channel structure 69D (for example, Cover multiple cell channel structure 69C and multiple illusory channel structure 69D).Second interlayer insulating film 87 may include oxide, Such as Si oxide.Second interlayer insulating film 87, the first interlayer insulating film 85, primary stacked structure 60T and supporter 50, 31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B can be patterned to allow to be formed Multiple isolated grooves 88,89 and 90.Multiple isolated grooves 88,89 and 90 may include the first isolated groove 88, the second isolating trenches Slot 89 and third isolated groove 90.

Second isolated groove 89 can be parallel to the first isolated groove 88.First isolated groove 88 and the second isolated groove 89 Each of can be with cross unit region CEL and welding disking area EXT.First isolated groove 88 can be buried with multiple first units Groove 31, first tie up the extension burial groove 41 of burial groove 31A and first and overlap.Second isolated groove 89 can be with multiple The burial of Unit two groove 32, second tie up the extension burial groove 42 of burial groove 32A and second and overlap.Third isolated groove 90 can To be formed between the first isolated groove 88 and the second isolated groove 89.Third isolated groove 90 can be set in welding disking area In EXT.Third isolated groove 90 can be arranged in the edge of welding disking area EXT towards unit area CEL.Third isolated groove 90 can extend burial groove 43 with third partly overlaps.

With reference to Fig. 1 and Figure 33, sidewall spacer 91 can be formed in the side-walls of multiple isolated grooves 88,89 and 90.Shape Technique at sidewall spacer 91 may include film forming technology and anisotropic etching process.Sidewall spacer 91 may include There is the material of etching selectivity relative to mold layer 29.For example, sidewall spacer 91 may include polysilicon.Multiple isolated grooves 88,89 and 90 can pass through the second interlayer insulating film 87, the first interlayer insulating film 85, primary stacked structure 60T, supporter 50, 31P, 31AP, 32P, 32AP, 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B.

In the CEL of unit area, the first isolated groove 88 and the second isolated groove 89 can pass through support plate 50, so that mould Layer 29 can expose.In the CEL of unit area, the first isolated groove 88 and the second isolated groove 89 can pass through multiple first lists Member support pattern 31P, first, which are tied up, supports pattern 31AP, multiple second units support pattern 32P and second to tie up support pattern 32AP exposes lower conductiving layer 25.In welding disking area EXT, the first isolated groove 88, the second isolated groove 89 and Three isolated grooves 90 may pass through the first extension support bar 41B, the second extension support bar 42B and third and extend support bar 43B, so that Lower conductiving layer 25 can expose.

With reference to Fig. 1 and Figure 34, in the CEL of unit area, primary cavity can be formed by removing intermediate mold layer 29M 29MC.Mold layer 29 can be retained in welding disking area EXT.

With reference to Fig. 1 and Figure 35, in the CEL of unit area, cavity 29G can be formed by removal mold layer 29.Mold layer 29 can To be retained in welding disking area EXT.

With reference to Figure 36, support pattern 31P, 31AP, 32P and 32AP lower surface and support bar 33B, 41B, 42B, 43B, The lower surface of 44B, 45B, 46B and 47B can directly be contacted with lower conductiving layer 25.For example, multiple second units support pattern 32P Lower surface can directly be contacted with lower conductiving layer 25.In the CEL of unit area, when removing mold layer 29 to form cavity 29G, Information storage pattern 64 can be partly removed, the side surface of channel pattern 65 is exposed.Letter can partly be removed Breath storage pattern 64, so as to form the first undercut area UC1 between support plate 50 and channel pattern 65.First undercut region Domain UC1 can be connected to (for example, being connected to cavity 29G) with cavity 29G.

With reference to Figure 37, in welding disking area EXT, the first extension support bar 41B, the second extension support bar 42B and third are prolonged Stretching support bar 43B can be retained between mold layer 29 and multiple isolated grooves 88,89 and 90.When cavity 29G is formed in cellular zone When in the CEL of domain, the first extension support bar 41B, the second extension support bar 42B and third, which extend support bar 43B, can prevent pad Mold layer 29 in the EXT of region is removed.Mold layer 29 can be retained in welding disking area EXT.

With reference to Figure 38, the part of lower mold layer 29A can be retained in support pattern 31P, 31AP, 32P and 32AP and lower conduction Between layer 25 and between support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B and lower conductiving layer 25.Under for example, The part of mold layer 29A can be retained between multiple second unit support pattern 32P and lower conductiving layer 25.In unit area CEL In, when remove mold layer 29 to form cavity 29G when, can support pattern 31P, 31AP, 32P and 32AP and lower conductiving layer 25 it Between form the second undercut area UC2 and third undercut area UC3.For example, the second undercut area UC2 and third undercut area UC3 It can be formed between multiple second unit support pattern 32P and lower conductiving layer 25.Second undercut area UC2 can be with cavity 29G is connected to (for example, being connected to cavity 29G).Third undercut area UC3 can be connected to the second isolated groove 89 (for example, connecting To the second isolated groove 89).

With reference to Figure 39, lower mold layer 29A can be retained in support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B with Between lower conductiving layer 25.In welding disking area EXT, the 4th undercut area UC4 can be formed in the first extension support bar 41B under Between conductive layer 25, second extension support bar 42B and lower conductiving layer 25 between and third extend support bar 43B and under lead Between electric layer 25.For example, the 4th undercut area UC4 can be connected to (for example, being connected to the second isolating trenches with the second isolated groove 89 Slot 89).

With reference to Figure 40, in some embodiments, sidewall spacer 91 can directly be contacted with lower conductiving layer 25.Lower mold layer The part of 29A can be retained in support pattern 31P, 31AP, 32P and 32AP and lower conductiving layer 25 between and support bar 33B, Between 41B, 42B, 43B, 44B, 45B, 46B and 47B and lower conductiving layer 25.For example, the part of lower mold layer 29A can be retained in it is more Between a second unit support pattern 32P and lower conductiving layer 25.In the CEL of unit area, when removal mold layer 29 is to form cavity When 29G, the second undercut area UC2 can be formed between support pattern 31P, 31AP, 32P and 32AP and lower conductiving layer 25.Example Such as, the second undercut area UC2 can be formed between multiple second unit support pattern 32P and lower conductiving layer 25.Second undercutting Region UC2 can be connected to (for example, being connected to cavity 29G) with cavity 29G.For example, third bottom can not be formed compared with Figure 38 Cut region UC3.

With reference to Figure 41, lower mold layer 29A can be retained in support bar 33B, 41B, 42B, 43B, 44B, 45B, 46B and 47B with Between lower conductiving layer 25.For example, lower mold layer 29A can be retained in the second extension support bar 42B under in welding disking area EXT Between conductive layer 25.For example, the 4th undercut area UC4 can not be formed compared with Figure 39.

With reference to Fig. 1 and Figure 42, displacement conductor wire 93 can be formed in cavity 29G.Replacing conductor wire 93 can be with channel The side surface of pattern 65 directly contacts.Replacing conductor wire 93 may include conductive material, and such as, N-type polycrystalline silicon or p-type are more Crystal silicon.In some embodiments, displacement conductor wire 93 may include such as metal, metal silicide, metal nitride, metal oxygen Compound or combinations thereof.Displacement conductor wire 93 can be formed at the level essentially identical with mold layer 29.In some embodiments, Displacement conductor wire 93 may be provided as common source polar curve (CSL).Replacing conductor wire 93 can be on the second interlayer insulating film 87 (for example, second interlayer insulating film 87 of covering) and in the inside of multiple isolated grooves 88,89 and 90.

With reference to Fig. 1 and Figure 43, it can partly remove displacement conductor wire 93 and sidewall spacer 91 can be removed, so that Multiple isolated grooves 88,89 and 90 can expose.Can be formed by removing multiple sacrificial layers 62 with multiple isolated grooves 88, 89 are connected to multiple gap area 62G of (for example, being connected to multiple isolated grooves 88,89 and 90) with 90.

With reference to Fig. 1 and Figure 44, multiple conductive layers 95 can be formed in multiple gap area 62G.Alternating and repeatedly heap Folded multiple insulating layers 61 and multiple conductive layers 95 may be constructed stacked structure 60.Multiple conductive layers 95 may include for example golden Category, metal silicide, metal nitride, metal oxide, polysilicon, conductive carbon or combinations thereof.Form multiple conductive layers 95 Technique may include film forming technology and anisotropic etching process.Lower conductiving layer 25 can be in multiple isolated grooves 88,89 With 90 bottom-exposed.

In some embodiments, as shown in figure 4, information storage pattern 64 may include that tunnel insulation layer 64T, charge are deposited Reservoir 64E, the first barrier layer 64B and the second barrier layer 64B2.Second barrier layer 64B2 can be plugged on multiple 95 Hes of conductive layer Between first barrier layer 64B.Second barrier layer 64B2 can be in the upper and lower surfaces in each of multiple conductive layers 95 Extend.Second barrier layer 64B2 may include for example Si oxide, silicon nitride, silicon nitrogen oxides, high-k dielectrics material or its Combination.

With reference to Fig. 1 and Figure 45, can be formed in the lower conductiving layer 25 of the bottom-exposed of multiple isolated grooves 88,89 and 90 Impurity range 97.Insulation spacer 103 can be formed in the side-walls of multiple isolated grooves 88,89 and 90.It can be in multiple isolation Groove buried layer 105 is formed in groove 88,89 and 90.In some embodiments, impurity range 97 may include N-type impurity.Absolutely Insulating divider 103 may include such as Si oxide, silicon nitride, silicon nitrogen oxides, low-k dielectric materials, high-k dielectrics material Material or combinations thereof.Groove buried layer 105 may include such as metal, metal silicide, metal nitride, metal oxide, more Crystal silicon, conductive carbon or combinations thereof.In some embodiments, groove buried layer 105 may include such as insulating materials, such as silicon Oxide, silicon nitride, silicon nitrogen oxides, low-k dielectric materials, high-k dielectrics material or combinations thereof.

With reference to Fig. 1 and Figure 46, third interlayer insulating film 106 can be formed on the second interlayer insulating film 87.It can be formed Separate figure across third interlayer insulating film 106 and the second interlayer insulating film 87 and partially across the selection line of stacked structure 60 Case 107.In some embodiments, selection line partition pattern 107 can pass through multiple conductive layers 95 in top layer and most Layer below upper layer.Selection line partition pattern 107, which can be set, buries groove 33 and third extension mask trench in third unit 43 tops.It can be formed across third interlayer insulating film 106 and the second interlayer insulating film 87 to be connected to multiple cell channel knots Multiple sub- position plugs 113 of structure 69C.The 4th interlayer insulating film 108 can be formed on third interlayer insulating film 106.It can be The multiple sub-bit-lines 115 for being connected to multiple sub- position plugs 113 are formed in 4th interlayer insulating film 108.

Referring again to Fig. 1 and Fig. 2, insulating layer 121 between layer 5 can be formed on multiple sub-bit-lines 115.It can be Multiple plugs 123 for being connected to multiple sub-bit-lines 115 are formed in five interlayer insulating films 121.Can between layer 5 insulating layer The bit line 125 for being connected to multiple plugs 123 is formed on 121.Third interlayer insulating film 106, selection line partition pattern 107, Insulating layer 121 may include insulating materials between four interlayer insulating films 108 and layer 5, such as Si oxide, silicon nitride, silicon nitrogen Oxide, low-k dielectric materials or combinations thereof.Multiple sub- position plugs 113, multiple sub-bit-lines 115, multiple plugs 123 and position Line 125 may include such as metal, metal silicide, metal nitride, metal oxide, polysilicon, conductive carbon or combinations thereof.

The example embodiment conceived according to the present invention, providing a kind of includes supporter, displacement conductor wire and stacking knot The 3D semiconductor devices of structure.Supporter may include support plate, support pattern and/or support bar.Displacement conduction is formed executing When the technique of line, supporter can reduce and/or prevent the damage to stacked structure.It can use simplified technique and realize have surely Determine the 3D semiconductor devices of structure.

It will be understood that although being used herein term " first ", " second " etc. to describe the example embodiment party of present inventive concept Component, region, layer, part, section, component and/or element in formula, but component, region, layer, part, section, component and/ Or element should not be limited by these terms.These terms are only used to by a component, region, part, section, component or element with Another component, region, part, section, component or element distinguish.Therefore, in the feelings for the range for not departing from present inventive concept Under condition, first component, region, part, section, component or element described below can also be referred to as second component, region, portion Point, section, component or element.Such as first element can also be referred to as second element, and similarly, second element can also To be referred to as first element, without departing from the range of present inventive concept.

Herein, for convenience of description, spatial relation term can be used, such as " ... lower section ", " ... under Face ", "lower", " in ... top ", "upper" etc., come describe an elements or features and other element (s) or feature (s) as Relationship shown in figure.It will be understood that spatial relation term, which is intended to also cover, to be used or is grasping other than orientation shown in figure Other different orientations of device in work.For example, being described as " " other elements or feature if the device in figure is reversed The element of " lower section " or " following " will be oriented as " " other elements or feature " on ".Therefore, exemplary term " ... Lower section " can cover above and below two kinds orientation.Device can otherwise be orientated and (be rotated by 90 ° or in other orientations), And spatial relation description symbol used herein is interpreted accordingly.

Term used herein is only used for the purpose of description particular implementation, it is not intended to limit example embodiment.Such as Used herein above, singular " one ", "one" and "the" are also intended to including plural form, unless the context otherwise specifically It is bright.Will be further understood that, if be used herein term "comprising", " including ... ", " comprising " and/or " including ... ", show the presence of the feature, integer, step, operation, element and/or component, but be not excluded for it is one or more other Feature, integer, step, operation, the presence or addition of element, component and/or group.

Unless otherwise defined, otherwise all terms (including technical and scientific term) used herein have and structure of the present invention Think the identical meaning of the normally understood meaning of those of ordinary skill in the art.It will also be understood that fixed such as in common dictionary Those of justice term should be interpreted as having and its meaning in the context of this specification and related fields is consistent contains Justice, and the explanation that will not be understood to idealization or over formalization, unless explicitly defining herein.

When can differently realize some example embodiment, specific work can be differently carried out with described sequence Skill sequence.For example, two techniques continuously described can be executed substantially concurrently or with opposite with described sequence Sequence executes.

In the accompanying drawings, it is contemplated that the variation of the shown shape of the result as such as manufacturing technology and/or tolerance.Cause This, the example embodiment of present inventive concept should not be construed as limited to the specific shape in region shown here, but can be with It is interpreted as including the deviation of such as shape as caused by manufacturing process.For example, the etching area for being shown as rectangular shape can To be sphering or specific curved shape.Therefore, region shown in the accompanying drawings is substantially schematical, shown in the accompanying drawings The shape in region is intended to show that the specific shape in the region of device, is not intended to limit the invention the range of design.Such as institute here It uses, term "and/or" includes any and all combinations of one or more related listed items.Such as "at least one" One column element of statement before when, modification permutation element is without the individual element modified in the column.

It will be understood that when an element referred to as " connects " or when " coupled " to another element, it can be directly connected to or It is connected to another element, or may exist intervening elements.On the contrary, when an element referred to as " be directly connected to " or " directly When another element is arrived in connection ", intervening elements are not present.Other words for describing the relationship between element or layer should be with class As mode explain (for example, " ... between " and " between directly existing ... ", " adjacent " and " direct neighbor ", " above " and " on directly existing ... ").

Identical number always shows identical element.Therefore, even if both not referring to or not having in the corresponding drawings Description can also describe the same or similar number with reference to other accompanying drawings.Furthermore, it is possible to describe not use with reference to other accompanying drawings The element that appended drawing reference indicates.

Although describing the embodiment of present inventive concept by reference to attached drawing, those skilled in the art should be managed Solution, in the case where not departing from the range of present inventive concept and not changing its essential characteristic, various modifications can be carried out.Therefore, Above embodiment should be to be considered only as it is descriptive, rather than the purpose for limitation.

This application claims enjoy No. 10-2018-0057636 submitted in Korean Intellectual Property Office on May 21st, 2018 The priority and right of South Korea patent application, entire disclosure are incorporated in this by reference.