阅读说明：本技术 多层一次性可编程永久存储器单元及其制备方法 (Multilayer One Time Programmable persistent memory unit and preparation method thereof ) 是由 彭泽忠 于 2017-08-28 设计创作，主要内容包括：多层一次性可编程永久存储器单元及其制备方法,涉及存储器技术。本发明提供一种多层一次性可编程永久存储器单元,含有：至少两层一次性可编程永久存储器模块,一层堆叠在另一层的上面；所述至少两层一次性可编程永久存储器模块的每一层,包含有用反相掺杂半导体材料制成的M行和N列,其中M和N是大于1正整数；薄绝缘电介质材料设置在所述至少两层一次性可编程永久存储器模块的每一层的所述M行和N列的相交处,在M行和N列之间；所述薄绝缘电介质材料在每一所述M行和N列的顶面和底面之一上。本发明的多层OTP永久存储器单元具有高存储密度。(Multilayer One Time Programmable persistent memory unit and preparation method thereof, is related to memory technology.The present invention provides a kind of multilayer One Time Programmable persistent memory unit, contains: at least two layers of One Time Programmable persistent storage module, a layer heap are stacked in the upper surface of another layer；Each layer of at least two layers One Time Programmable persistent storage module, comprising M row made of useful reverse phase doped semiconductor materials and N column, wherein M and N is greater than 1 positive integer；Each layer of the M row of at least two layers One Time Programmable persistent storage module and the intersection of N column is arranged in thin insulating dielectric substance, between M row and N column；The thin insulating dielectric substance is on one of top and bottom that each M row and N are arranged.Multilayer OTP persistent memory unit of the invention has high storage density.)

A multi-level one-time programmable persistent memory cell comprising:

at least two layers of one-time programmable permanent memory modules, one layer stacked on top of the other; each layer of the at least two layers of otp-nonvolatile memory modules includes M rows and N columns made of an inversely doped semiconductor material, where M and N are positive integers greater than 1;

a thin insulating dielectric material is disposed at the intersection of the M rows and N columns of each layer of the at least two layers of one-time programmable permanent memory modules, between the M rows and N columns; the thin insulating dielectric material is on one of a top surface and a bottom surface of each of the M rows and N columns.

The multi-layer otp-persistent memory cell of claim 1, wherein each layer of the otp-memory modules is stacked in a bottom-up direction, connected at the intersection of M rows and N columns, and wherein the M rows in each layer of the otp-memory modules are disposed on one of the top and bottom of the N columns.

The multi-layer otp-nonvolatile memory cell of claim 1, further comprising a plurality of otp-nonvolatile memory cells formed at the intersection of M rows and N columns of the otp-nonvolatile memory module in each layer and a plurality of otp-nonvolatile memory cells formed at the intersection between the otp-nonvolatile memory modules.

The multi-layer one-time programmable permanent memory cell of claim 3 wherein the one-time programmable memory cell comprises a p-type semiconductor region, an n-type semiconductor region, and a thin insulating dielectric region between the p-type semiconductor region and the n-type semiconductor region.

The multi-layer one-time programmable permanent memory cell of claim 4 wherein each one-time programmable memory cell further comprises at least two connection terminals located in the p-type semiconductor region and the n-type semiconductor region.

The multilevel one time programmable permanent memory cell of claim 5 wherein the at least two connection terminals in each of the one time programmable memory cells are connected to each other using conductive vias.

The multi-layer one-time programmable persistent memory cell of claim 4 wherein a thickness of the thin insulating dielectric material forming the thin insulating dielectric region in the one-time programmable memory cell is a predetermined value corresponding to a breakdown voltage of each of the one-time programmable memory cells.

The multi-level one time programmable persistent memory unit of claim 1, further comprising multi-level decoder circuits for the M rows and N columns of the one time programmable persistent memory module, the multi-level decoder circuits being shared by at least two layers of the one time programmable persistent memory module stacked one on top of the other.

The multi-layer otp persistent memory cell of claim 1, wherein the M rows of each layer of the otp persistent memory module are comprised of one of a p-type semiconductor material and an N-type semiconductor material, and the N columns are comprised of an inverse of the one of the p-type semiconductor material and the N-type semiconductor material.

A multi-level one-time programmable persistent memory cell comprising:

at least two layers of otp-nonvolatile memory modules stacked one on top of the other, each layer of the at least two layers of otp-nonvolatile memory modules comprising M rows and N columns of useful conductors, wherein M and N are positive integers greater than 1;

a plurality of one-time programmable persistent memory cells formed at the intersections of M rows and N columns of the one-time programmable persistent memory modules at each layer, and a plurality of one-time programmable persistent memory cells formed at the intersections between the one-time programmable persistent memory modules.

A multi-level one-time programmable persistent memory cell comprising:

at least two layers of one-time programmable permanent memory modules, one layer stacked on top of the other; each of the at least two layers of otp-nonvolatile memory blocks includes M row lines and N column lines, where M and N are positive integers greater than 1;

at each intersection point, the materials of the row line M and the column line N are respectively two materials which are required for generating Schottky contact at the intersection point;

a thin insulating dielectric material is disposed at the intersection of the M rows and N columns of each of the at least two layers of one time programmable permanent memory modules.

A method of making a multi-layer one-time programmable permanent memory cell, the method comprising:

disposing a semiconductor material on a top planar surface of a wafer containing completed memory peripheral circuitry using one of a deposition process and an epitaxial process;

counter-doping the semiconductor material with a dopant that is one of a p-type dopant and an n-type dopant using one of an ion implantation process and a diffusion process;

removing the redundant part of the doped semiconductor material by using a photoetching mask process and an etching process, manufacturing the anti-doped semiconductor material into a strip-shaped semiconductor material strip, and forming one of M rows and N columns which are formed by anti-phase doped semiconductor material in the one-time programmable permanent memory module, wherein M and N are positive integers which are more than one;

filling strips of semiconductor material comprising one of M rows and N columns of the one time programmable permanent memory module with an insulating dielectric material using a planarization process;

removing the insulating dielectric material overfilled in strips of semiconductor material comprising one of the M rows and N columns of the one time programmable non-volatile memory module using a chemical-mechanical polishing process;

creating a thin insulating dielectric film over the filled strips of semiconductor material that make up one of the M rows and N columns of the OTP memory module using a thermal oxidation process, or a low temperature chemical vapor deposition process, or an atomic layer deposition process;

repeating the method in a direction from bottom to top to a predetermined number of times, symmetrically stacking the one-time programmable persistent memory modules produced by each repetition to produce the multi-level one-time programmable persistent memory cells.

The method of claim 12 further characterized by forming a number of one time programmable memory cells at the M row and N column intersections of the one time programmable persistent memory modules and at the intersections between the one time programmable persistent memory modules.

The method of claim 12, further comprising iteratively adding another layer of said thin insulating dielectric film on top of the topmost one of said otp-memory modules, stacking one of said M rows and N columns of counter-doped semiconductor material on said added another layer of thin insulating dielectric to add otp-memory cells in said multi-layer otp-memory cells; the counter-doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.

A method of making a multi-layer one-time programmable permanent memory cell, the method comprising:

depositing a thick insulating dielectric material on a top planar surface of a wafer containing completed memory peripheral circuitry;

building a trench on the deposited thick dielectric layer using a mask etch process for locating one of a row and a column of an otp permanent memory module;

depositing a semiconductor material on the trench;

counter-doping the doped semiconductor material with a dopant, which is one of a p-type dopant and an n-type dopant, using a diffusion process or an ion implantation process;

removing the excessively deposited anti-doping semiconductor material by adopting a conventional planarization process to form one of M rows and N columns of the one-time programmable permanent memory module, wherein M and N are positive integers larger than 1;

depositing a layer of insulating dielectric material on the top planar surface of the wafer;

forming a trench in the deposited thick dielectric layer using a mask etch process for locating one of a row and a column of the otp permanent memory module; the etching process will be until the last deposited semiconductor material is reached;

depositing a thin insulating dielectric film on one of the M rows and the N columns of the one-time programmable permanent memory module by using a thermal oxidation process, or a thermal deposition process, or an atomic layer deposition process, wherein the thin insulating dielectric film on one of the M rows and the N columns of the one-time programmable permanent memory module is used as a programmable dielectric material;

repeating the method in a direction from bottom to top to a predetermined number of times, symmetrically stacking the one-time programmable persistent memory modules produced by each repetition to produce the multi-level one-time programmable persistent memory cells.

The method of claim 15, further comprising forming a number of one-time programmable memory cells at an intersection of M rows and N columns of the one-time programmable persistent memory module and at an intersection between the one-time programmable persistent memory modules.

The method of claim 16, further comprising iteratively adding another layer of the thin insulating dielectric film over a topmost one of the otp-memory modules, stacking one of the M rows and N columns of counter-doped semiconductor material over the added another layer of the thin insulating dielectric film to add otp-memory cells in the multi-layer otp-memory cell; the counter-doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.