阅读说明：本技术 降低单元接触缺陷的制造方法及半导体存储器 (Reduce the manufacturing method and semiconductor memory of unit contact deficiency ) 是由 吴小飞 于 2018-05-24 设计创作，主要内容包括：本发明揭示一种降低单元接触缺陷的制造方法及半导体存储器,方法包括提供衬底,并在衬底上的位线结构、有源区和浅沟槽隔离结构的表面上沉积形成第一接触层,第一接触层在相邻位线结构之间形成第一凹槽；在第一接触层上沉积形成第二接触层,第二接触层在所述第一凹槽处形成第二凹槽；去除位线结构顶部和第二凹槽底部的第二接触层,露出第一接触层；过度刻蚀第一接触层,以露出位线结构和浅沟槽隔离结构的顶部,并在第二凹槽中填充接触间隔材料,以间隔单元接触；半导体存储器包括上述方法制备的单元接触。本发明的第二接触层用作保护层,以使在过度刻蚀第一接触层时,减少对浅沟槽隔离结构两侧硅的刻蚀,减少单元接触的缺陷。(The present invention discloses a kind of manufacturing method and semiconductor memory for reducing unit contact deficiency, method includes providing substrate, and deposition forms the first contact layer on the surface of bit line structure on substrate, active area and fleet plough groove isolation structure, the first contact layer forms the first groove between adjacent bit lines structure；Deposition forms the second contact layer on the first contact layer, and the second contact layer forms the second groove in first groove；The second contact layer at the top of bit line structure with the second bottom portion of groove is removed, the first contact layer is exposed；The first contact layer of overetch to expose the top of bit line structure and fleet plough groove isolation structure, and is filled contact interval material in the second groove, is contacted with spacer units；Semiconductor memory includes the unit contact of above method preparation.Second contact layer of the invention is used as protective layer, so as to reduce the etching to fleet plough groove isolation structure two sides silicon in the first contact layer of overetch, reduces the defect of unit contact.)

1. reducing the manufacturing method of unit contact deficiency in a kind of semiconductor memory characterized by comprising

Substrate is provided, the substrate includes the shallow ridges to form multiple active areas in the substrate, each active area of isolation Recess isolating structure, part form a plurality of wordline in the active area and are partially formed on the active area and are located at Multiple bit line structures between two wordline；

Deposit the surfaces of active regions of first contact material between institute's bit line structures surface, adjacent institute's bit line structures and On the surface of shallow trench isolation structure, to form the first contact layer, wherein first contact layer is in the adjacent bitline junction The first groove is formed between structure；

The second contact material is deposited on first contact material, to form the second contact layer, wherein second contact layer The second groove is formed in first groove；The bottom of second groove is aligned with the fleet plough groove isolation structure, described The width of second bottom portion of groove is less than the width of the fleet plough groove isolation structure, and described second connects under identical etching condition The etch rate for touching the first contact material described in material etch speed ratio is slow；

Second contact layer at the top of institute's bit line structures with second bottom portion of groove is removed, is located at the bit line to expose First contact layer of structural top and positioned at first bottom portion of groove in alignment with described in the fleet plough groove isolation structure First contact layer, second contact layer of part are still located at side of first contact layer between institute's bit line structures；

Overetch be located at bit line structure top first contact layer and overetch described in the second bottom portion of groove institute The first contact layer is stated, at the top of the bit line structures and top of the fleet plough groove isolation structure to expose；And

Contact interval material is filled, in second groove to be formed on the fleet plough groove isolation structure and spacer units connect The spacer structure of touching.

2. the manufacturing method according to claim 1, which is characterized in that fill contact interval material in second groove The step of include:

The first wall two sides above the fleet plough groove isolation structure are formed, to cover first contact layer and described second The surface that contact layer appears, and first wall forms opening；And

The second wall is formed on first wall, is open with filling first wall；The manufacturing method is also Include:

First contact layer and second contact layer upper surface are etched downwards, to form contact openings, and in the contact Metal material is filled in opening, to form metal contact layer, the unit contact connects including first contact layer, described second Contact layer and the metal contact layer.

3. the manufacturing method according to claim 1, which is characterized in that removal institute's bit line structures at the top of and described second Before second contact material of bottom portion of groove, the manufacturing method further include:

Third contact material is deposited on second contact layer, to form third contact layer, the third contact layer fills institute State the second groove；And

The step of removing second contact layer at the top of institute's bit line structures with second bottom portion of groove further include:

The third contact layer at the top of institute's bit line structures with second bottom portion of groove is etched, when exposing institute's bit line structures First contact layer at top, positioned at first bottom portion of groove in alignment with the part of the fleet plough groove isolation structure described One contact layer and also expose positioned at second contact layer of first recess sidewall.

4. the manufacturing method according to claim 1, which is characterized in that the resistance of second contact layer is higher than described first The resistance of contact layer.

5. manufacturing method according to claim 3, which is characterized in that first contact material and the third contact material Material includes high-concentration dopant polysilicon, and second contact material includes low concentration doping polysilicon.

6. manufacturing method according to any one of claims 1 to 3, which is characterized in that the overetch includes that dry method is carved Erosion.

7. a kind of semiconductor memory for reducing unit contact deficiency characterized by comprising

Substrate, the substrate include to be formed multiple active areas in the substrate, each active area of isolation shallow trench every A plurality of wordline in the active area is formed from structure, part and is partially formed on the active area and is located at two Multiple bit line structures between the wordline；

First contact layer is formed between adjacent institute's bit line structures on the active area of the fleet plough groove isolation structure two sides, often The section of first contact layer described in side includes L-type, and first contact layer includes the bottom for covering the active area, and covering institute The side of bit line structures side wall；

Second contact layer is formed on the bottom of first contact layer and covers the side wall of the side, wherein described second The etch rate of contact layer is less than the etch rate of first contact layer；

Contact interval structure is formed in above the fleet plough groove isolation structure and connects positioned at first contact layer and described second Space between contact layer, is contacted with spacer units.

8. semiconductor memory according to claim 7, which is characterized in that the contact interval structure includes:

First wall is formed in above the fleet plough groove isolation structure, and first wall covers first contact layer Bottom sidewall and second contact layer side wall, wherein the thickness of first wall be less than the shallow trench every 1/2 of width from structure, so that first wall has opening；And

Second wall is formed on the first wall, for filling the opening of first wall；

The unit contact includes first contact layer, second contact layer and metal contact layer, the metal contact layer It is formed at the top of first contact layer and at the top of second contact layer, and the top of the metal contact layer and described first Wall top and the second wall hanging.

9. semiconductor memory according to claim 7, which is characterized in that the material of first contact layer includes highly concentrated DOPOS doped polycrystalline silicon is spent, the material of second contact layer includes low concentration doping polysilicon.

10. according to semiconductor memory described in claim 7,8 or 9, which is characterized in that the resistance of second contact layer is high In the resistance of first contact layer.

Technical field

The present invention relates to reduce unit in a kind of semiconductor memory technology processing procedure more particularly to a kind of semiconductor memory The manufacturing method and semiconductor memory of contact deficiency.

Background technique

In the processing procedure of semiconductor memory, for the structure of unit contact, as shown in Figure 1, being formed on substrate 10 Source region 12, wordline 11, bit line structure 13 and fleet plough groove isolation structure (STI) 14, it is single in contact to constitute osculating element opening Member opening deposit polycrystalline silicon 16, deposits one layer of silicon nitride 15, while etching polysilicon 16 and silicon nitride 15 on polysilicon 16, with Unit contact structures are formed, but due to polysilicon 16 and 15 etch rate difference of silicon nitride and silicon nitride 15 is only deposited on polycrystalline 16 surface of silicon can cause defect to 16 side of polysilicon in vertical etching process, while appear in overetch polysilicon 16 When fleet plough groove isolation structure 14, the silicon positioned at 16 bottom fleet plough groove isolation structure of polysilicon, 14 two sides can be also etched, defect is caused, Such defect will form leakage path, and charge storage is caused to leak electricity, and adversely affect to device performance.

Summary of the invention

The present invention provides a kind of manufacturing method and semiconductor memory for reducing unit contact deficiency, existing at least to solve The above technical problem in technology.

In order to achieve the above objectives, the manufacturing method of unit contact deficiency, packet are reduced in a kind of semiconductor memory of the present invention It includes:

Substrate is provided, the substrate includes multiple active areas, each active area of isolation to be formed in the substrate Fleet plough groove isolation structure, part form a plurality of wordline in the active area and part is formed on the active area and Multiple bit line structures between two wordline；

Deposit the active area table of first contact material between institute's bit line structures surface, adjacent institute's bit line structures On face and the surface of shallow trench isolation structure, to form the first contact layer, wherein first contact layer is in adjacent institute's rheme The first groove is formed between cable architecture；

The second contact material is deposited on first contact material, to form the second contact layer, wherein described second connects Contact layer forms the second groove in first groove；The bottom of second groove is aligned with the fleet plough groove isolation structure, The width of second bottom portion of groove is less than the width of the fleet plough groove isolation structure, and described the under identical etching condition Two contact material etch rates are slower than the etch rate of first contact material；

Second contact layer at the top of institute's bit line structures with second bottom portion of groove is removed, to expose positioned at described First contact layer at the top of bit line structure and positioned at first bottom portion of groove in alignment with the fleet plough groove isolation structure First contact layer, second contact layer of part are still located at side of first contact layer between institute's bit line structures Face；

Overetch be located at bit line structure top first contact layer and overetch described in the second bottom portion of groove First contact layer, at the top of the bit line structures and top of the fleet plough groove isolation structure to expose；And

Contact interval material is filled, in second groove to be formed on the fleet plough groove isolation structure and interval is single The spacer structure of member contact.

In a kind of embodiment, the step of contact interval material is filled in second groove, includes:

The first wall two sides above the fleet plough groove isolation structure are formed, to cover first contact layer and described The surface that second contact layer appears, and first wall forms opening；And

The second wall is formed on first wall, is open with filling first wall；The manufacturer Method further include:

First contact layer and second contact layer upper surface are etched downwards, to form contact openings, and described Metal material is filled in contact openings, to form metal contact layer, the unit contact includes first contact layer, described the Two contact layers and the metal contact layer.

In a kind of embodiment, at the top of removal institute's bit line structures and the second contact material of second bottom portion of groove Before material, the manufacturing method further include:

Third contact material is deposited on second contact layer, to form third contact layer, the third contact layer is filled out Fill second groove；And

The step of removing second contact layer at the top of institute's bit line structures with second bottom portion of groove further include:

The third contact layer at the top of institute's bit line structures with second bottom portion of groove is etched, when the exposing bit line First contact layer of structural top, positioned at first bottom portion of groove in alignment with the part institute of the fleet plough groove isolation structure It states the first contact layer and also exposes positioned at second contact layer of first recess sidewall.

In a kind of embodiment, the resistance of second contact layer is higher than the resistance of first contact layer.

In a kind of embodiment, first contact material and the third contact material include high-concentration dopant polysilicon, Second contact material includes low concentration doping polysilicon.

In a kind of embodiment, the overetch includes dry etching.

In order to achieve the above objectives, a kind of semiconductor memory for reducing unit contact deficiency of the present invention, comprising:

Substrate, the substrate include the shallow ridges to form multiple active areas in the substrate, each active area of isolation Recess isolating structure, part form a plurality of wordline in the active area and are partially formed on the active area and are located at Multiple bit line structures between two wordline；

First contact layer is formed in the active area of the fleet plough groove isolation structure two sides between adjacent institute's bit line structures On, the section of the first contact layer described in every side includes L-type, and first contact layer includes the bottom for covering the active area, and Cover the side of institute's bit line structures side wall；

Second contact layer is formed on the bottom of first contact layer and covers the side wall of the side, wherein described The etch rate of second contact layer is less than the etch rate of first contact layer；

Spacer structure is formed in above the fleet plough groove isolation structure and connects positioned at first contact layer and described second Space between contact layer, is contacted with spacer units.

In a kind of embodiment, the contact interval structure includes:

First wall is formed in above the fleet plough groove isolation structure, and the first wall covering described first connects The side wall of the bottom sidewall of contact layer and second contact layer, wherein the thickness of first wall is less than the shallow ridges The 1/2 of the width of recess isolating structure, so that first wall has opening；And

Second wall is formed on the first wall, for filling the opening of first wall；

The unit contact includes that first contact layer, second contact layer and metal contact layer, the metal connect Contact layer is formed at the top of first contact layer and at the top of second contact layer, and the top of the metal contact layer with it is described First wall top and the second wall hanging.

In a kind of embodiment, the material of first contact layer includes high-concentration dopant polysilicon, second contact layer Material include low concentration doping polysilicon.

In a kind of embodiment, the resistance of second contact layer is higher than the resistance of first contact layer.

First contact layer of the invention does not deposit full shallow trench isolation upper space, and deposits on first contact layer the Two contact layers, and there are etch rate difference, the etching speed of the second contact layer for second contact layer and first contact layer Rate is slow, and the second contact layer side generates etching defect, while the etching speed of the first contact layer when can be etched vertically with effective protection Rate is fast, in overetch, reduces the etching to the two sides STI silicon, reduces the defect of unit contact.

Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further Aspect, embodiment and feature, which will be, to be readily apparent that.

Detailed description of the invention

In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings depict only according to the present invention Disclosed some embodiments, and should not serve to limit the scope of the present invention.

Fig. 1 is that manufacturing cell contacts the cross-sectional view of the structure to form defect in the prior art.

Fig. 2 is the flow chart that the method for unit contact deficiency is reduced in the embodiment of the present invention.

Fig. 3 is cross-sectional view of the structure corresponding with step S10 in the embodiment of the present invention.

Fig. 4 is cross-sectional view of the structure corresponding with step S20 in the embodiment of the present invention.

Fig. 5 is cross-sectional view of the structure corresponding with step S30 in the embodiment of the present invention.

Fig. 6 is the sectional view for etching the structure that third contact layer is formed in the embodiment of the present invention on Fig. 5 counter structure.

Fig. 7 is cross-sectional view of the structure corresponding with step S40 in the embodiment of the present invention.

Fig. 8 is structure corresponding with step S50 in the embodiment of the present invention.

Fig. 9 is cross-sectional view of the structure corresponding with contact interval structure is formed in the embodiment of the present invention.

Figure 10 is with formation the first contact layer of etching and the second contact layer in the embodiment of the present invention to form metal contact layer Corresponding cross-sectional view of the structure.

Figure 11 is the overall structure sectional view of unit contact in the embodiment of the present invention.

The appended drawing reference of attached drawing 1: 10 substrates, 11 wordline, 12 active areas, 13 bit line structures, 14 fleet plough groove isolation structures, 15 Silicon nitride, 16 polysilicons.

The appended drawing reference of attached drawing 2 to 9:

110 substrates,

111 active areas,

112 wordline,

113 bit line structures,

113a bit line contact point,

The barrier layer 113b,

113c bit line-tungsten,

113d isolation structure,

114 fleet plough groove isolation structures,

120 first contact layers,

121 first grooves,

130 second contact layers,

131 second grooves,

140 metal contact layers,

150 first walls,

160 second walls,

170 third contact layers.

Specific embodiment

Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that Like that, without departing from the spirit or scope of the present invention, described embodiment can be modified by various different modes. Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.