阅读说明：本技术 半导体结构、晶体管结构的制备方法及半导体处理设备 (Semiconductor structure, the preparation method of transistor arrangement and semiconductor processing equipment ) 是由 刘铁 于 2018-05-24 设计创作，主要内容包括：本发明一种基于低温离子注入的半导体结构、晶体管制备及半导体处理设备,半导体结构制备包括：提供待处理结构,定义具有离子注入面的离子注入层区；对待处理结构进行降温处理,自离子注入面进行离子注入,在离子注入的过程中,离子注入层区转换成恢复损伤结晶层区和晶格破坏非晶层区,降温处理减缓离子注入层区内部的自退火效应,减小恢复损伤结晶层区区域的大小；进行退火处理,晶格破坏非晶层区转换成重结晶层区,恢复损伤结晶层区转换成结晶缺陷层区。本发明通过对待处理结构进行离子注入的过程中同时对其进行降温,在低温条件下进行离子注入,减缓了离子注入过程中的自退火效应,从而减少退火后的EOR缺陷,减少结漏电流,减少电子器件的功耗。(A kind of semiconductor structure based on cryogenic implantation of the present invention, transistor preparation and semiconductor processing equipment, semiconductor structure preparation include: to provide structure to be processed, define the ion implanted layer area with ion implanting face；It treats processing structure and carries out cooling processing, ion implanting is carried out from ion implanting face, during ion implanting, ion implanted layer area is converted into restoring damage crystallizing layer area and lattice damage amorphous layer area, cooling processing slows down the self annealing effect inside ion implanted layer area, reduces the size for restoring damage crystallizing layer region；It is made annealing treatment, lattice damage amorphous layer area is converted into re-crystallized layers area, restores damage crystallizing layer area and is converted into crystal defect floor area.Cooling down during the present invention is by treating processing structure progress ion implanting while to it, ion implanting is carried out under cryogenic, slows down the self annealing effect in ion implantation process, to reduce the EOR defect after annealing, junction leakage is reduced, the power consumption of electronic device is reduced.)

1. a kind of preparation method of the semiconductor structure based on cryogenic implantation, which comprises the steps of:

1) structure to be processed is provided, and defines an ion implanted layer area in the structure to be processed, and the ion implanting Floor area has an ion implanting face；

2) cooling processing carried out to the structure to be processed, and from the ion implanting in face of the ion implanted layer area carry out from Son injection, during carrying out the ion implanting, the ion implanted layer area is converted into dominating shape based on self annealing effect At recovery damage crystallizing layer area and based on the leading lattice damage amorphous layer area formed of injection ion damaged, wherein the drop Temperature processing continues to make the structure to be processed at 0 degree Celsius hereinafter, to slow down the ion in the ion implantation process The self annealing effect inside ion implanted layer area described in injection process, to reduce the life for restoring damage crystallizing layer area At thickness；And

3) structure that step 2) obtains is made annealing treatment, so that lattice damage amorphous layer area is converted into re-crystallized layers Area, and recovery damage crystallizing layer area is converted into crystal defect floor area.

2. the preparation method of the semiconductor structure according to claim 1 based on cryogenic implantation, which is characterized in that step It is rapid 2) in, the damage crystallizing layer area of restoring is located at the crystallizing layer area in lattice damage amorphous layer area and the structure to be processed Between, wherein in step 2), the temperature of the cooling processing is carried out between -100 DEG C~-50 DEG C.

3. the preparation method of the semiconductor structure according to claim 2 based on cryogenic implantation, which is characterized in that institute State restore damage crystallizing layer area thickness account for the ion implanted layer area thickness ratio between 1/5~1/2；It is described extensive The thickness for damaging crystallizing layer area again is less than 15nm.

4. the preparation method of the semiconductor structure according to claim 1 based on cryogenic implantation, which is characterized in that step It is rapid 2) in, the cooling processing is carried out to the structure to be processed by cooling device, wherein the cooling device and plummer It is connected, the structure setting to be processed is on the plummer, and the structure to be processed is far from the ion implanting face Side is in contact with the plummer, the cooling device by the plummer cool down with realize to the structure to be processed into The row cooling processing.

5. the preparation method of the semiconductor structure according to claim 4 based on cryogenic implantation, which is characterized in that step It is rapid 2) further include: it is processed to the cooling by temperature control device during carrying out cooling processing to the structure to be processed Temperature in journey is controlled, wherein the temperature control device is set on the plummer, and the temperature control device passes through monitoring The temperature of the plummer is carrying out the temperature in the ion implantation process to monitor the structure to be processed, and based on described The monitoring result of temperature control device controls the cooling device to realize that the temperature to the cooling treatment process is controlled System.

6. the preparation method of the semiconductor structure according to claim 5 based on cryogenic implantation, which is characterized in that base It is controlled in the monitoring result of the temperature control device by the temperature to coolant in the cooling device to realize to described Cooling device is controlled.

7. the preparation method of the semiconductor structure according to claim 1 based on cryogenic implantation, which is characterized in that step It is rapid 3) in, the thickness in crystal defect floor area is less than 15nm.

8. the preparation method of the semiconductor structure according to claim 7 based on cryogenic implantation, which is characterized in that step It is rapid 3) in, the thickness in crystal defect floor area accounts for the ratio of the thickness in the ion implanted layer area between 1/5~1/2.

9. the preparation method of the semiconductor structure according to claim 1 based on cryogenic implantation, which is characterized in that step It is rapid 3) in, ingots that crystal defect floor area includes several to be formed through the annealing, and each ingot At least one of size and orientation difference, wherein inside the crystalline state and the re-crystallized layers area inside the ingot Crystalline state be generally in identical.

10. the preparation side of the semiconductor structure described according to claim 1~any one of 9 based on cryogenic implantation Method, which is characterized in that in step 2), the molecular weight for carrying out the injection ion of the ion implanting is greater than 40, carries out the ion The implantation dosage of injection is greater than 1E15/ square centimeters.

11. a kind of preparation method of transistor arrangement, which is characterized in that the preparation method includes the following steps:

1) semiconductor substrate is provided, and definition has at least one source electrode region to be implanted and at least one in the semiconductor base A drain electrode region to be implanted；

2) cooling processing is carried out to the semiconductor base, and to source electrode region to be implanted and the drain electrode region to be implanted Ion implanting is carried out respectively, and during carrying out the ion implanting, the source electrode region to be implanted is converted into being located at described The source electrode of source electrode region lower part to be implanted restores damage crystallizing layer area and the source electrode crystalline substance positioned at source electrode area top to be implanted Lattice destroy amorphous layer area, and the drain electrode that the drain electrode region to be implanted is converted into being located at the drain electrode region lower part to be implanted restores damage Hurt crystallizing layer area and positioned at the drain electrode lattice damage amorphous layer area of the drain electrode area top to be implanted, wherein at the cooling Reason continues to make the semiconductor base at 0 degree Celsius hereinafter, to slow down the ion implanting in the ion implantation process Self annealing effect inside source electrode region to be implanted and inside the drain electrode region to be implanted in the process, to reduce the source Damage crystallizing layer area is restored in pole and the drain electrode restores the thickness in damage crystallizing layer area；And

3) structure that step 2) obtains is made annealing treatment, so that the source electrode lattice damage amorphous layer area is converted into source electrode Re-crystallized layers area, and constitute source electrode；The source electrode restores damage crystallizing layer area and is converted into source end defect crystal region；The leakage Pole lattice damage amorphous layer area is converted into drain electrode re-crystallized layers area, and constitutes drain electrode；The drain electrode restores damage crystallizing layer area and turns Change drain end defect crystal region into.

12. the preparation method of transistor arrangement according to claim 11, which is characterized in that the semiconductor base is default The active area and isolated area that justice has several to be intervally arranged, wherein the source electrode and the drain electrode are formed in the active area In, and buried gate word line structure is also formed between the source electrode and the drain electrode.

13. a kind of semiconductor processing equipment, which is characterized in that the semiconductor processing equipment includes plummer and cooling dress It sets, the cooling device is connected with the plummer, for cooling down to the structure to be processed carried on the plummer Processing, wherein the cooling processing is included in during the structure to be processed carries out ion implanting while to described wait locate Manage the cooling processing that structure carries out.

14. 3 semiconductor processing equipment according to claim 1, which is characterized in that the semiconductor processing equipment further includes temperature Device is controlled, the temperature control device is set on the plummer, and the temperature control device passes through the temperature of the monitoring plummer The temperature in the ion implantation process, and the monitoring knot based on the temperature control device are being carried out to monitor the structure to be processed Fruit controls the cooling device to realize that the temperature to the cooling treatment process controls.

Technical field

The invention belongs to semiconductor device structure preparation technical fields, more particularly to one kind based on cryogenic implantation half Conductor structure preparation method, the preparation method of transistor arrangement and semiconductor processing equipment.

Background technique

Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer Semiconductor storage unit, be made of many duplicate storage units.Each storage unit generally includes capacitor and transistor； The grid of transistor is connected with wordline, drain be connected with bit line, source electrode is connected with capacitor；Voltage signal in wordline can be controlled Transistor processed opens or closes, and then reads the data information of storage in the capacitor by bit line, or will by bit line Data information is written in capacitor and is stored.Currently, DRAM is all made of stacking-type in 20nm DRAM processing procedure below Capacitor structure, capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio to increase surface area.

Currently, with portable electronic product in daily life become increasingly popular and electronic product in device size Reduce, density increases, and saves electrical source consumption and has become one of significant challenge.In semiconductor fabrication in ion implanting and annealing EOR (the End of Range) defect formed afterwards will lead to junction leakage (Junction leakage), in the prior art, such as exist In source-drain area preparation, EOR defect layer is thicker, causes junction leakage (10^-5~10^-8A/CM₂), to increase the function of electronic device Consumption.

Therefore, how the preparation method and semiconductor equipment of a kind of semiconductor structure, transistor arrangement are provided, it is existing to solve There is in technology EOR defect influence serious problem to device performance to be necessary.

Summary of the invention

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide one kind based on cryogenic implantation half Conductor structure preparation method, the preparation method of transistor arrangement and semiconductor processing equipment are lacked for solving EOR in the prior art Falling into influences serious problem on device performance.

In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor junction based on cryogenic implantation The preparation method of structure, which comprises the steps of:

1) structure to be processed is provided, and defines an ion implanted layer area in the structure to be processed, and the ion Implanted layer area has an ion implanting face；

2) cooling processing carried out to the structure to be processed, and from the ion implanting in face of the ion implanted layer area into Row ion implanting, during carrying out the ion implanting, the ion implanted layer area is converted into based on self annealing effect master Lead the recovery damage crystallizing layer area to be formed and based on the leading lattice damage amorphous layer area formed of injection ion damaged, wherein institute Stating cooling processing continues to make in the ion implantation process structure to be processed at 0 degree Celsius hereinafter, described to slow down The self annealing effect inside ion implanted layer area described in ion implantation process, to reduce recovery damage crystallizing layer area Generation thickness；And

3) structure that step 2) obtains is made annealing treatment, so that lattice damage amorphous layer area is converted into tying again Crystal layer area, and recovery damage crystallizing layer area is converted into crystal defect floor area.

As a preferred solution of the present invention, in step 2), it is broken that recovery damage crystallizing layer area is located at the lattice Between bad amorphous layer area and the crystallizing layer area of the structure to be processed, wherein in step 2), carry out the temperature of the cooling processing Between -100 DEG C~-50 DEG C.

As a preferred solution of the present invention, the thickness for restoring damage crystallizing layer area accounts for the ion implanted layer area Thickness ratio between 1/5~1/2；The thickness for restoring damage crystallizing layer area is less than 15nm.

As a preferred solution of the present invention, in step 2), institute is carried out to the structure to be processed by cooling device State cooling processing, wherein the cooling device is connected with plummer, the structure setting to be processed on the plummer, And the structure to be processed is in contact far from the side in the ion implanting face with the plummer, passes through in the cooling device The plummer cooling carries out the cooling processing to the structure to be processed to realize.

As a preferred solution of the present invention, step 2) further include: cooling processing is carried out to the structure to be processed In the process, the temperature in the cooling treatment process is controlled by temperature control device, wherein the temperature control device is set to On the plummer, and the temperature control device is being carried out by monitoring the temperature of the plummer with monitoring the structure to be processed Temperature in the ion implantation process, and the monitoring result based on the temperature control device to the cooling device controlled with Realize that the temperature to the cooling treatment process controls.

As a preferred solution of the present invention, the monitoring result based on the temperature control device passes through to the cooling device The temperature of middle coolant is controlled to realize and control the cooling device.

As a preferred solution of the present invention, in step 3), the thickness in crystal defect floor area is less than 15nm.

As a preferred solution of the present invention, in step 3), the thickness in crystal defect floor area accounts for the ion note The ratio of the thickness in the area Ru Ceng is between 1/5~1/2.

As a preferred solution of the present invention, in step 3), crystal defect floor area includes moving back described in several warps The ingot that fiery processing is formed, and at least one of the size of each ingot and orientation difference, wherein the ingot Internal crystalline state and the crystalline state inside the re-crystallized layers area is generally in identical.

As a preferred solution of the present invention, in step 2), the molecular weight of the injection ion of the ion implanting is carried out Greater than 40, the implantation dosage for carrying out the ion implanting is greater than 1E15/ square centimeters.

The present invention also provides a kind of preparation method of transistor arrangement, the preparation method includes the following steps:

1) semiconductor substrate is provided, and definition has at least one source electrode region to be implanted and extremely in the semiconductor base Few drain electrode region to be implanted；

2) cooling processing is carried out to the semiconductor base, and to be implanted to source electrode region to be implanted and the drain electrode Region carries out ion implanting respectively, and during carrying out the ion implanting, the source electrode region to be implanted is converted into being located at The source electrode of the source electrode region lower part to be implanted restores damage crystallizing layer area and positioned at the source of source electrode area top to be implanted Pole lattice damage amorphous layer area, the drain electrode that the drain electrode region to be implanted is converted into being located at the drain electrode region lower part to be implanted are extensive Crystallizing layer area is damaged again and positioned at the drain electrode lattice damage amorphous layer area of the drain electrode area top to be implanted, wherein the drop Temperature processing continues to make the semiconductor base at 0 degree Celsius hereinafter, to slow down the ion in the ion implantation process Self annealing effect inside the region to be implanted of source electrode described in injection process and inside the drain electrode region to be implanted, to reduce State the thickness that source electrode restores damage crystallizing layer area and the drain electrode restores damage crystallizing layer area；And

3) structure that step 2) obtains is made annealing treatment, so that the source electrode lattice damage amorphous layer area is converted into Source electrode re-crystallized layers area, and constitute source electrode；The source electrode restores damage crystallizing layer area and is converted into source end defect crystal region；Institute It states drain electrode lattice damage amorphous layer area and is converted into drain electrode re-crystallized layers area, and constitute drain electrode；The drain electrode restores damage crystallizing layer Area is converted into drain end defect crystal region.

As a preferred solution of the present invention, the active area that definition has several to be intervally arranged in the semiconductor base And isolated area, wherein the source electrode and the drain electrode are formed in the active area, and between the source electrode and the drain electrode It is also formed with buried gate word line structure.

The present invention also provides a kind of semiconductor processing equipment, the semiconductor processing equipment includes plummer and cooling dress It sets, the cooling device is connected with the plummer, for cooling down to the structure to be processed carried on the plummer Processing, wherein the cooling processing is included in during the structure to be processed carries out ion implanting while to described wait locate Manage the cooling processing that structure carries out.

As a preferred solution of the present invention, the semiconductor processing equipment further includes temperature control device, the temperature control dress It installs and is placed on the plummer, and the temperature control device is by monitoring the temperature of the plummer to monitor the knot to be processed Structure is carrying out the temperature in the ion implantation process, and the monitoring result based on the temperature control device to the cooling device into Row control is controlled with the temperature to the cooling treatment process.

As described above, the preparation of the invention based on cryogenic implantation semiconductor structure preparation method, transistor arrangement Method and semiconductor processing equipment, have the advantages that

The present invention provides a kind of preparation method of semiconductor structure, by the mistake for treating processing structure progress ion implanting Cool down to it to provide a low temperature environment simultaneously in journey, carry out ion implanting under cryogenic, slows down ion note Self-annealing (self annealing effect) during entering, so that having residual during ion implanting The crystallized layer depth of damage is reduced, to reduce the EOR defect after annealing, can reduce 50% or more compared with the prior art, from And junction leakage (Junction leakage) is reduced, reduce the power consumption of electronic device.

Detailed description of the invention

Fig. 1 is shown as the semiconductor structure preparation technology flow chart provided by the invention based on cryogenic implantation.

Fig. 2 is shown as providing showing for structure to be processed in the semiconductor structure preparation of the invention based on cryogenic implantation It is intended to.

Fig. 3 is shown as the semiconductor structure of the invention based on cryogenic implantation and prepares intermediate ion treated that structure is shown It is intended to.

Fig. 4 is shown as the structure after making annealing treatment in the semiconductor structure preparation of the invention based on cryogenic implantation and shows It is intended to.

Fig. 5 be shown as it is of the invention based on cryogenic implantation semiconductor structure preparation in cool down processing device signal Figure.

Fig. 6 is shown as the transistor arrangement schematic diagram that crystal tube preparation method of the invention is prepared.

Component label instructions

100 structures to be processed

100a crystallizing layer area

101 ion implanted layer areas

101a ion implanting face

102 lattice damage amorphous layer areas

103 restore damage crystallizing layer area

104 re-crystallized layers areas

105 crystal defect floor area

200 plummers

300 cooling devices

301 refrigeration machines

302 transfer conduits

400 semiconductor bases

401 isolated areas

402 active areas

403 source electrodes area to be implanted

404 drain electrode areas to be implanted

405 source electrodes

406 source end defect crystal regions

407 drain electrodes

408 drain end defect crystal regions

S1~S3 step 1)~step 3)

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.

Fig. 1 is please referred to Fig. 6.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout form may also be increasingly complex.

As shown in Fig. 1~5, the present invention provides a kind of preparation method of semiconductor structure based on cryogenic implantation, institute Preparation method is stated to include the following steps:

1) structure to be processed is provided, and defines an ion implanted layer area in the structure to be processed, and the ion Implanted layer area has an ion implanting face；

2) cooling processing carried out to the structure to be processed, and from the ion implanting in face of the ion implanted layer area into Row ion implanting, during carrying out the ion implanting, the ion implanted layer area is converted into based on self annealing effect master Lead the recovery damage crystallizing layer area to be formed and based on the leading lattice damage amorphous layer area formed of injection ion damaged, wherein institute State cooling processing continue make in the ion implantation process structure to be processed at 0 degree Celsius (that is, 0 DEG C) hereinafter, with Slow down the self annealing effect inside ion implanted layer area described in the ion implantation process, to reduce the recovery damage The generation thickness in crystallizing layer area；And

3) structure that step 2) obtains is made annealing treatment, so that lattice damage amorphous layer area is converted into tying again Crystal layer area, recovery damage crystallizing layer area are converted into crystal defect floor area.

Below in conjunction with the preparation of the attached drawing semiconductor structure based on cryogenic implantation that the present invention will be described in detail.

Firstly, carrying out step 1) shown in S1 and Fig. 2 and Fig. 5 as shown in figure 1, providing a structure 100 to be processed, and in institute It states and defines an ion implanted layer area 101 in structure to be processed, and the ion implanted layer area has an ion implanting face 101a.

Specifically, providing a structure to be processed for needing to carry out ion implanting in this step, wherein the structure to be processed Shape can be common structure shape in the industry well known within the skill of those ordinarily skilled, can be with shape in the structure to be processed At there is any other semiconductor component structures, it can be single layer structure layer, be also possible to multi-layer laminate structure, do not do have herein Body limitation.In addition, the ion implanted layer area 101 for needing to carry out ion implanting is defined in the structure to be processed, and Define its ion implanting face 101a, the ion implanting face 101a is selected as the ion note in this example according to actual selection The upper surface in the area Ru Ceng 101 is the ion implanting face 101a.

Then, shown in S2 and Fig. 3 as shown in figure 1, step 2) is carried out, cooling processing is carried out to the structure 100 to be processed, And ion implanting is carried out to the ion implanted layer area 101 from the ion implanting face 101a, carrying out the ion implanting In the process, the ion implanted layer area 101 is at least converted into damaging crystallizing layer area based on the leading recovery formed of self annealing effect 103 and based on the leading lattice damage amorphous layer area 102 formed of injection ion damaged, wherein the cooling processing is persistently in institute It states and makes the structure to be processed 100 at 0 degree Celsius hereinafter, to slow down institute in the ion implantation process in ion implantation process The self annealing effect inside ion implanted layer area 101 is stated, to reduce the big of the recovery damage 103 region of crystallizing layer area It is small, restore the generation thickness in damage crystallizing layer area 103 as described in reducing.Wherein, line of the Fig. 3 with arrow indicates ion implanting Direction.

Specifically, the step carries out cryogenic implantation to the structure 100 to be processed, that is to say, that in ion implanting The temperature that the structure to be processed is reduced while process makes the structure to be processed keep low temperature environment, that is, make it is described from Sub- implanted layer area 101 keeps low temperature environment, to slow down the self annealing effect occurred in the ion implanted layer area, infuses in ion During entering, the inside in the ion implanted layer area on the one hand can be due to the effect of injection ion, to the lattice structure of injection region Destruction is generated, so that it is changed into amorphous layer, the self annealing effect of itself on the other hand, inside the ion implanted layer area occurs Answer so that occur self annealing effect part formed have residual damage crystallizing layer, therefore, when injection from When son destruction accounts for leading, the ion implanted layer area of the position is converted into lattice damage amorphous layer area 102, works as self annealing When effect accounts for leading, recovery damage crystallizing layer area 103 described in the ion implanted layer area of the position.Make in the low temperature of the application Under, the self annealing effect inside the ion implanted layer area can be effectively reduced, to have based on what self annealing generated The volume of the crystallizing layer of residual damage will tail off namely the body in the region for restoring damage crystallizing layer area 103 Long-pending and area will be reduced, and the recovery damages crystallizing layer area 103 in subsequent annealing, can be transformed into and be not intended to deposit Defect, i.e. EOR defect (crystal defect floor area), the application restores damage by reducing described in ion implantation process The size in crystallizing layer area 103, significantly reduces the size in crystal defect floor area 105, to reduce the junction leakage of device Electric current.

Specifically, the sequence that the cooling processing is carried out with the ion implanting does not limit specifically, preferably implement one In example, the technique of the cooling processing is carried out prior to the technique of the ion implanting, and first carrying out the cooling processing can make The structure to be processed is first down to certain temperature, it is easier to achieve the effect that slow down the self annealing effect, while can also be with The requirement to board is reduced, process costs are reduced, improves working efficiency.

As an example, in step 2), the bottom restored damage crystallizing layer area 103 and be located at the ion implanted layer area 101 Portion, lattice damage amorphous layer area 102 are located in recovery damage crystallizing layer area 103, wherein the cooling processing slows down The self annealing effect inside ion implanted layer area 101 described in the ion implantation process, to reduce the institute for being located at bottom State the thickness for restoring damage crystallizing layer area 103.

As an example, recovery damage crystallizing layer area 103 is located at lattice damage amorphous layer area 102 in step 2) Between the crystallizing layer area (dotted line frame part immediately below in such as Fig. 3) of the structure to be processed, wherein in step 2), carry out institute The temperature of cooling processing is stated between -100 DEG C~-50 DEG C.

Specifically, in one example, as shown in figure 3, forming the recovery damage in the bottom in the ion implanted layer area 101 Hurt crystallizing layer area 103, what it is in the recovery damage 103 upper surface of crystallizing layer area formation is lattice damage amorphous layer area 102, The technique of cooling processing based on the application, the recovery damage crystallizing layer area 103 formed in ion implantation process Thickness relative to without cooling processing ion implanting, the application the recovery damage crystallizing layer area 103 thickness only Reduce half, wherein the thickness for restoring damage crystallizing layer area 103 refers to the upper of recovery damage crystallizing layer area 103 The distance between surface and lower surface, the lower surface for restoring damage crystallizing layer area 103 is described in the ion implanted layer area The line of demarcation in the region for not carrying out ion implanting of structure to be processed, i.e., the bottom in the described ion implanted layer area, the ion note The bottom in the area Ru Ceng refers to the surface of the other side opposite with the ion implanting face in the ion implanted layer area.

As an example, carrying out the temperature of the cooling processing between -100 DEG C~-50 DEG C in step 2).

Specifically, the temperature of the cooling processing carried out to the structure to be processed is between -100 DEG C~-50 DEG C, It is preferred that the structure to be processed in the temperature in the ion implantation process between -100 DEG C~-50 DEG C, so as to bright It is aobvious to improve final EOR defect, further preferably between -80 DEG C~-60 DEG C, -70 DEG C ± 5 DEG C are selected in this example, is made Obtaining conventional semiconductor equipment can achieve above-mentioned condition, and can significantly reduce EOR defect, it will be apparent that it is existing to improve junction leakage As.

As an example, the thickness for restoring damage crystallizing layer area 103 accounts for the ratio of the thickness in the ion implanted layer area 101 Example is between 1/5~1/2.

As an example, the thickness for restoring damage crystallizing layer area 103 is less than 15nm.

Specifically, the thickness H2 for restoring damage crystallizing layer area 103 accounts for the thickness H1's in the ion implanted layer area 101 Ratio is between 1/5~1/2, it is preferable that rationally controls the temperature of the cooling processing, the recovery of formation damages crystallization The ratio that the thickness in floor area 103 occupies entire ion implanted layer area can be decreased to 1/4 or 1/3 etc. ratio, the recovery damage The thickness H2 in crystallizing layer area 103 is less than 15nm, even less than 10nm or even several nanometers, such as the thickness of 6nm, so as to aobvious The EOR defect that the reduction of work is subsequently formed, it is significant to improve junction leakage phenomenon.

As an example, the cooling processing is carried out to the structure 100 to be processed by cooling device 300 in step 2), Wherein, the cooling device 300 is connected with plummer 200, and the structure 100 to be processed is set to the plummer 200 On, and the side far from the ion implanting face 101a of the structure to be processed 100 is in contact with the plummer 200, institute It states cooling device 300 and the cooling processing is carried out to the structure 100 to be processed to realize by the plummer 200 cooling.

Specifically, as shown in fig.5, a kind of mode for carrying out the cooling processing is provided in this example, by cool down Device 300 and plummer 200 heat the structure 100 to be processed, it is preferable that implement back to the structure 100 to be processed The mode of face heating, wherein the cooling device 300 includes refrigeration machine 301 and transfer conduit 302, the cooling in refrigeration machine 301 Agent is transmitted to the plummer (platen) 200 via the transfer conduit 302, then reduces the knot to be processed by heat transfer The temperature of structure 100.

As an example, step 2) further include: during carrying out cooling processing to the structure to be processed, filled by temperature control It sets (not shown) to control the temperature in the cooling treatment process, wherein the temperature control device is set to described On plummer 200, and the temperature control device is by monitoring the temperature of the plummer 200 to monitor the structure to be processed 100 The temperature in the ion implantation process is being carried out, and the monitoring result based on the temperature control device is to the cooling device 300 It is controlled to realize that the temperature to the cooling treatment process controls.

As an example, the monitoring result based on the temperature control device by the temperature to coolant in the cooling device into Row control controls the cooling device with realizing.

Specifically, in one example, being provided with temperature control device, also on the plummer 200 accurately to realize to institute The control of the temperature of structure to be processed is stated, the position of the temperature control device can arbitrarily be arranged, be not particularly limited, this example In, the temperature control device replaces the temperature of the structure to be processed by testing the temperature of the plummer, further, one In preferred embodiment, based on the monitoring result of the temperature control device, to the temperature of the refrigeration machine in the cooling device 300 into Row regulation, so as to realize the structure to be processed temperature regulation, it is of course also possible to be other modes, not with this It is limited.

In another example, it is provided with temperature control device on the cooling device, the temperature for coolant described in direct monitoring Degree, and then realize the regulation to the temperature of structure to be processed described in cooling treatment process.

Finally, carry out step 3) shown in S3 and Fig. 4 as shown in figure 1, the structure that step 2) obtains is made annealing treatment, So that lattice damage amorphous layer area 102 is converted into re-crystallized layers area 104, recovery damage crystallizing layer area 103 is converted At crystal defect floor area 105.

Specifically, made annealing treatment in this step to the structure 100 to be processed, the annealing can into Lattice in the row ion implantation process is repaired, wherein lattice damage amorphous layer area 102 is recrystallized, shape At complete crystal structure, and the recovery damages crystallizing layer area 103 in the annealing process, and lattice transformation occurs, Become an incomplete crystal defect floor area 105, in the present invention, based at the cooling that the ion implanting stage is implemented Reason, so that recovery damage 103 thickness of crystallizing layer area that ion implanting is formed greatly reduces, so that turning after annealing The thickness in the crystal defect floor area 105 being deformed into greatly reduces, to greatly reduce junction leakage.

As an example, the thickness in crystal defect floor area 105 is less than 15nm in step 3).

As an example, the thickness in crystal defect floor area 105 accounts for the thickness in the ion implanted layer area in step 3) Ratio is between 1/5~1/2.

Specifically, the thickness H3 in crystal defect floor area 105 accounts for the ratio of the thickness H1 in the ion implanted layer area 101 Between 1/5~1/2, it is preferable that rationally control the temperature of the cooling processing, the crystal defect floor area 105 of formation Thickness occupy entire ion implanted layer area ratio can be decreased to 1/4 or 1/3 etc. ratio, crystal defect floor area 105 Thickness H3 be less than 15nm, even less than 10nm or even several nanometers, such as the thickness of 6nm, so as to significantly improve knot Leakage phenomenon.

As an example, crystal defect floor area 105 includes the knot that several are formed through the annealing in step 3) Crystal block 1051, and at least one of the size of each ingot 1051 and orientation difference, wherein in the ingot 1051 The crystalline state in portion is generally in identical with the crystalline state inside the re-crystallized layers area 104.

Specifically, obtained crystal defect floor area 105 includes several ingots 1051 irregularly arranged, In, after annealing, the crystalline state inside the ingot 1051 and the crystalline state phase inside the re-crystallized layers area 104 Together, specifically, at least one of size and orientation of each ingot 1051 difference refer to, each ingot 1051 Size distribution is uneven, and at least the two is of different sizes；Both the distribution of orientations of either each ingot 1051 is different, at least Orientation it is different；Either above-mentioned two situations exist, wherein the size of the ingot 1051 refers to the ingot Based on the size of the interpretable partial size of those of ordinary skill in the art, such as lateral dimension or longitudinal size, the ingot 1051 Orientation refer to that the ingot 1051 arragement direction as a whole is different, such as the distribution of orientations of a certain crystal face is different. Obtained crystal defect floor area 105 influences the junction leakage of device smaller.

As an example, in step 2), the molecular weight for carrying out the injection ion of the ion implanting is greater than 40, carry out it is described from The implantation dosage of son injection is greater than 1E15/ square centimeters.

Specifically, the molecular weight for injecting ion is greater than 40, preferably greater than in the ion implantation process of step 2) 50, implantation dosage is greater than 1E15/ square centimeters, preferably greater than 1E16/ square centimeters, can be effective using the solution of the present invention Generated EOR defect during the ion implanting and annealing of ground solution aforesaid way, as can be applied to source-drain area Preparation, to improve junction leakage.

As shown in fig. 6, the preparation method includes following step the present invention also provides a kind of preparation method of transistor arrangement It is rapid:

1) semiconductor substrate 400 is provided, and definition has at least one source electrode region to be implanted in the semiconductor base 403 and at least one region 404 to be implanted of draining；

2) cooling processing is carried out to the semiconductor base 400, and to source electrode region to be implanted 403 and the drain electrode Region 404 to be implanted carries out ion implanting respectively, wherein during carrying out the ion implanting, the source electrode is to be implanted Region 403 is converted into restoring damage crystallizing layer area positioned at the source electrode of source electrode region lower part to be implanted and is located at the source The source electrode lattice damage amorphous layer area of area top extremely to be implanted, the drain electrode region 404 to be implanted are converted into being located at the leakage The drain electrode of region lower part extremely to be implanted restores damage crystallizing layer area and the drain electrode crystalline substance positioned at the drain electrode area top to be implanted Lattice destroy amorphous layer area, wherein the cooling processing continues to make the semiconductor base 400 in the ion implantation process At 0 degree Celsius hereinafter, to slow down 403 inside of the region to be implanted of source electrode described in the ion implantation process and described drain wait infuse Enter the self annealing effect inside region 404, the source electrode restores damage crystallizing layer area and the drain electrode restores damage to reduce The thickness in crystallizing layer area；And

3) structure that step 2) obtains is made annealing treatment, so that the source electrode lattice damage amorphous layer area is converted into Source electrode re-crystallized layers area, and constitute source electrode 405；The source electrode restores damage crystallizing layer area and is converted into source end defect crystal region 406；Drain electrode lattice damage amorphous layer area is converted into drain electrode re-crystallized layers area, and constitutes drain electrode 407；The drain electrode restores damage Hurt crystallizing layer area and is converted into drain end defect crystal region 408.

As an example, definition has several to be intervally arranged in the semiconductor base 400 active area 402 and isolated area 401, wherein the source electrode 405 and the drain electrode 407 are formed in the active area 402, and the source electrode 405 with it is described Buried gate word line structure 409 is also formed between drain electrode 407.

Specifically, the present invention also provides a kind of preparation methods of the source-drain electrode of transistor based on cryogenic implantation, such as Shown in Fig. 6, in the source electrode 405 and the preparation process of the drain electrode 407, carry out while ion implanting to described The cooling of semiconductor base 400 is handled, so as to reduce source end defect crystal region 406 and drain end defect crystal region 407 thickness reduces the junction leakage of entire transistor, reduces electronic device power consumption, improves the stability of transistor.

As shown in fig.5, the semiconductor processing equipment includes carrying the present invention also provides a kind of semiconductor processing equipment Platform 200 and cooling device 300, the cooling device 300 are connected with the plummer 200, for the plummer The structure to be processed 100 carried on 200 carries out cooling processing, wherein the cooling processing is included in the structure to be processed 100 The cooling carry out simultaneously to the structure to be processed during ion implanting is handled.

As an example, the semiconductor processing equipment further includes temperature control device, the temperature control device is set to the carrying On platform 200, and the temperature control device monitored by monitoring the temperature of the plummer 200 structure to be processed 100 into Temperature in the row ion implantation process, and the monitoring result based on the temperature control device carries out the cooling device 300 Control is controlled with the temperature to the cooling treatment process.

Specifically, as shown in fig.5, a kind of mode for carrying out the cooling processing is provided in this example, by cool down Device 300 and plummer 200 heat the structure 100 to be processed, it is preferable that implement back to the structure 100 to be processed The mode of face heating, wherein the cooling device 300 includes refrigeration machine 301 and transfer conduit 302, the transfer conduit 302 It is connected with the refrigeration machine 301, and is touched with the back face of the plummer 200, the coolant warp in the refrigeration machine 301 The plummer (platen) 200 is transmitted to by the transfer conduit 302, then the structure to be processed is reduced by heat transfer 100 temperature.

Specifically, in one example, being provided with temperature control device, also on the plummer 200 accurately to realize to institute The control of the temperature of structure to be processed is stated, the position of the temperature control device can arbitrarily be arranged, be not particularly limited, this example In, the temperature control device replaces the temperature of the structure to be processed by testing the temperature of the plummer, further, one In preferred embodiment, based on the monitoring result of the temperature control device, to the temperature of the refrigeration machine in the cooling device 300 into Row regulation, so as to realize the structure to be processed temperature regulation, it is of course also possible to be other modes, not with this It is limited.

In another example, it is provided with temperature control device on the cooling device, the temperature for coolant described in direct monitoring Degree, and then realize the regulation to the temperature of structure to be processed described in cooling treatment process.

As shown in figure 4, the present invention also provides a kind of semiconductor structures based on cryogenic implantation, it is preferred to use the present invention The preparation method of the semiconductor structure based on cryogenic implantation of description is prepared, and semiconductor structure includes:

Crystallizing layer area 100a；

Crystal defect floor area 105 is located on the crystallizing layer area 100a, and crystal defect floor area 105 includes several Ingot 1051, and at least one of the size of each ingot 1051 and orientation difference；And

Re-crystallized layers area 104 is located in crystal defect floor area 105, and the re-crystallized layers area 104 includes after recrystallizing Crystalline state, the crystalline state inside the ingot 1051 is generally in the crystalline state inside the re-crystallized layers area 104 It is identical.

As an example, the thickness in crystal defect floor area 105 is less than 15nm.

As an example, the thickness in crystal defect floor area 105 accounts for crystal defect floor area 105 and the re-crystallized layers The ratio of the overall thickness (thickness of the i.e. described ion implanted region) in area 104 is between 1/5~1/2.

It, can be under cold service specifically, the present invention also provides a kind of semiconductor structures based on cryogenic implantation The self annealing effect inside the ion implanted layer area is effectively reduced, to have residual based on what self annealing generated The volume of the crystallizing layer of damage will tail off namely it is described restore damage crystallizing layer area 103 region volume and area just It can reduce, and the recovery damages crystallizing layer area 103 in subsequent annealing, can be transformed into and be not intended to existing defect, That is EOR defect (crystal defect floor area), the application restore damage crystallizing layer area by reducing described in ion implantation process 103 size, significantly reduces the size in crystal defect floor area 105, to reduce the junction leakage of device.

Specifically, the thickness H3 in crystal defect floor area 105 accounts for the ratio of the thickness H1 in the ion implanted layer area 101 Between 1/5~1/2, it is preferable that rationally control the temperature of the cooling processing, the crystal defect floor area 105 of formation Thickness occupy entire ion implanted layer area ratio can be decreased to 1/4 or 1/3 etc. ratio, crystal defect floor area 105 Thickness H3 be less than 15nm, even less than 10nm or even several nanometers, such as the thickness of 6nm, so as to significantly improve junction leakage Current phenomena.In addition, obtained crystal defect floor area 105 includes several ingots 1051 irregularly arranged, wherein After annealing, the crystalline state inside the ingot 1051 is identical as the crystalline state inside the re-crystallized layers area 104, Specifically, at least one of size and orientation of each ingot 1051 difference refer to, each ingot 1051 it is big Small to be unevenly distributed, at least the two is of different sizes；Both the distribution of orientations of either each ingot 1051 is different, at least Orientation is different；Either above-mentioned two situations exist, wherein the size of the ingot 1051 refers to the base of the ingot In the size of the interpretable partial size of those of ordinary skill in the art, such as lateral dimension or longitudinal size, the ingot 1051 Orientation refers to that the arragement direction of the ingot 1051 as a whole is different, and the distribution of orientations of such as a certain crystal face is different. The crystal defect floor area 105 arrived influences the junction leakage of device smaller.

As shown in fig. 6, the present invention also provides a kind of transistor arrangement, including described in above-mentioned any scheme based on low temperature from The semiconductor structure of son injection, wherein section substrate of the crystallizing layer area as the transistor arrangement, the annealed zone 104 as at least one of the source electrode 405 of the transistor arrangement and drain electrode 407, and crystal defect floor area 105 is used as source At least one of pole end defect crystal region 406 and drain end defect crystal region 408.

Specifically, the preparation of source-drain electrode is based on the crystalline substance of cryogenic implantation the present invention also provides a kind of transistor arrangement The preparation method of the source-drain electrode of body pipe, as shown in fig. 6, in the source electrode 405 and the preparation process of the drain electrode 407, into The processing of the cooling to the semiconductor base 400 is carried out while row ion implanting, so as to reduce source end defect knot The thickness of crystalline region 406 and drain end defect crystal region 407 reduces the junction leakage of entire transistor, reduces electronic device Power consumption improves the stability of transistor.

In conclusion a kind of preparation method of the semiconductor structure based on cryogenic implantation of the present invention, transistor preparation Method and semiconductor processing equipment, semiconductor structure preparation method include: one structure to be processed of offer, and in the knot to be processed An ion implanted layer area is defined in structure, and the ion implanted layer area has an ion implanting face；It is faced from the ion implanting The ion implanted layer area carries out ion implanting, and carries out cooling processing to the structure to be processed simultaneously, carry out it is described from During son injection, the ion implanted layer area is at least converted into based on the leading recovery damage crystallization formed of self annealing effect Floor area and based on the leading lattice damage amorphous layer area formed of injection ion damaged, wherein the cooling processing is persistently described Make in ion implantation process the structure to be processed at 0 degree Celsius hereinafter, with slow down described in the ion implantation process from The self annealing effect inside sub- implanted layer area, to reduce the size for restoring damage crystallizing layer region；And to upper The structure that one step obtains is made annealing treatment, so that lattice damage amorphous layer area is converted into re-crystallized layers area, it is described extensive Damage crystallizing layer area is converted into crystal defect floor area again.Through the above scheme, the present invention provides a kind of preparation of semiconductor structure Method, by cooling down to it to provide a low temperature ring simultaneously during treating processing structure and carrying out ion implanting Border carries out ion implanting under cryogenic, slows down the self-annealing (self annealing effect) in ion implantation process, So that the crystallized layer depth with residual damage during ion implanting is reduced, to reduce annealing EOR defect afterwards, can reduce 50% or more compared with the prior art, to reduce junction leakage (Junction leakage), subtract The power consumption of few electronic device.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value Value.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.