阅读说明：本技术 一种信号处理系统 (Signal processing system ) 是由 张明明 张懿麒 林维聪 于 2019-09-10 设计创作，主要内容包括：本发明公开了一种信号处理系统,包括：输入接口、现场可编程门阵列模块以及至少两个输出接口；现场可编程门阵列模块通过输入接口接收外部设备的输入信号；现场可编程门阵列模块用于检测输入信号的接口类型,若接口类型为预设类型,则将输入信号转换为预设格式的标准信号,并通过第一输出接口输出标准信号；若接口类型为非预设类型,则通过第二输出接口输出输入信号。上述技术方案根据接口类型对输入信号进行选择性处理,对预设类型接口的输入信号转换后输出,对非预设类型接口的输入信号直接从不同的输出接口输出,实现了对两种类型接口的输入信号的分别处理,提高信号格式转换的效率。(The invention discloses a signal processing system, comprising: the system comprises an input interface, a field programmable gate array module and at least two output interfaces; the field programmable gate array module receives an input signal of an external device through an input interface; the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal with a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; and if the interface type is not a preset type, outputting the input signal through the second output interface. According to the technical scheme, the input signals are selectively processed according to the interface types, the input signals of the preset type interfaces are output after being converted, the input signals of the non-preset type interfaces are directly output from different output interfaces, the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.)

1. a signal processing system, comprising: the system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interfaces; the field programmable gate array module receives an input signal of an external device through the input interface;

The field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal with a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; and if the interface type is a non-preset type, outputting the input signal through a second output interface.

2. the system of claim 1, wherein the fpga module is specifically configured to detect whether the input signal matches a preset format, and if not, mark the interface type of the input interface as a preset type.

3. The system of claim 1, wherein the number of input interfaces is at least two, and the field programmable gate array module comprises:

The interface identification recognition unit is used for recognizing the interface identification of the input interface corresponding to the input signal;

And the interface type identification unit is used for determining the interface type according to the mapping relation between the interface identifier and the interface type.

4. The system of claim 2 or 3, wherein the field programmable gate array module further comprises:

A signal extraction unit for extracting a high level appearing for the first time in the input signal;

the signal adjusting unit is used for adjusting the duration time of the high level to a preset duration time to obtain the standard signal;

and the first signal output unit is used for outputting the standard signal through a first output interface.

5. The system of claim 2 or 3, wherein the input signal comprises at least two level signals, the field programmable gate array module further comprising:

the signal decoding unit is used for decoding the input signal into at least two parallel standard signals with preset formats;

And the second signal output unit is used for outputting the parallel standard signals through the first output interface.

6. the system of claim 5, wherein the signal decoding unit is specifically configured to:

extracting a high level which appears for the first time in each level signal in the input signal;

and adjusting the duration time of each high level to be preset duration time to obtain parallel standard signals.

Technical Field

the embodiment of the invention relates to the technical field of signal processing, in particular to a signal processing system.

background

in the process of collecting and integrating signals of different devices, the signals of different devices are required to have the same format, so that the signals are convenient to identify and process. In practice, however, the formats of signals from different devices are often not consistent. For example, when signals of an eye tracker and a motion capture device are input into an electroencephalograph for integration, the signals input by the eye tracker and the motion capture device have respective formats and time stamps, for example, the input signals may include a cyclic signal, a continuous clock signal with a fixed frequency, a continuous high level signal, and the like, and the input signals with different formats cannot be directly recognized and used by the electroencephalograph, but need to be converted into standard format signals before further processing.

the existing signal format conversion method converts all collected signals, and cannot selectively process input signals, so that the delay of signal format conversion is high, and the efficiency is low.

Disclosure of Invention

The invention provides a signal processing system for improving the efficiency of signal format conversion.

An embodiment of the present invention provides a signal processing system, including:

The system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interfaces; the field programmable gate array module receives an input signal of an external device through the input interface;

The field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal with a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; and if the interface type is a non-preset type, outputting the input signal through a second output interface.

The field programmable gate array module is specifically configured to detect whether the input signal matches a preset format, and if not, mark the interface type of the input interface as a preset type.

Further, the number of the input interfaces is at least two, and the field programmable gate array module includes:

The interface identification recognition unit is used for recognizing the interface identification of the input interface corresponding to the input signal;

And the interface type identification unit is used for determining the interface type according to the mapping relation between the interface identifier and the interface type.

Further, the field programmable gate array module further includes:

a signal extraction unit for extracting a high level appearing for the first time in the input signal;

the signal adjusting unit is used for adjusting the duration time of the high level to a preset duration time to obtain the standard signal;

And the first signal output unit is used for outputting the standard signal through a first output interface.

Further, the input signal includes at least two level signals, and the field programmable gate array module further includes:

The signal decoding unit is used for decoding the input signal into at least two parallel standard signals with preset formats;

and the second signal output unit is used for outputting the parallel standard signals through the first output interface.

Further, the signal decoding unit is specifically configured to:

Extracting a high level which appears for the first time in each level signal in the input signal;

and adjusting the duration time of each high level to preset duration to obtain the standard signal.

An embodiment of the present invention provides a signal processing system, including: the system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interfaces; the field programmable gate array module receives an input signal of an external device through an input interface; the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal with a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; and if the interface type is not a preset type, outputting the input signal through the second output interface. According to the technical scheme, the input signals are selectively processed according to the interface types, the input signals of the preset type interfaces are output after being converted, the input signals of the non-preset type interfaces are directly output from different output interfaces, the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.

Drawings

Fig. 1 is a schematic structural diagram of a signal processing system according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a signal processing system according to an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a signal processing system according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating input signals according to a second embodiment of the present invention;

Fig. 5 is a schematic diagram of an output signal in the second embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.