阅读说明：本技术 数据输出缓冲器和具有该数据输出缓冲器的存储装置 (data output buffer and memory device having the same ) 是由 安根善 郑尧韩 黄珍夏 于 2019-02-18 设计创作，主要内容包括：数据输出缓冲器和具有该数据输出缓冲器的存储装置。本公开涉及一种数据输出缓冲器和具有该数据输出缓冲器的存储装置。该数据输出缓冲器包括：上拉主驱动器,该上拉主驱动器联接在电源端子和输出端子之间,所述上拉主驱动器被配置为输出高电平的数据；以及下拉主驱动器,该下拉主驱动器联接在所述输出端子和接地端子之间,所述下拉主驱动器被配置为输出低电平的数据,其中,所述上拉主驱动器包括：主上拉晶体管,该主上拉晶体管是第一类型的；以及多个第一微调晶体管,所述多个第一微调晶体管中的每一个是第二类型的。(A data output buffer and a memory device having the same. The present disclosure relates to a data output buffer and a memory device having the same. The data output buffer includes: a pull-up main driver coupled between a power supply terminal and an output terminal, the pull-up main driver configured to output data of a high level; and a pull-down main driver coupled between the output terminal and a ground terminal, the pull-down main driver configured to output data of a low level, wherein the pull-up main driver includes: a main pull-up transistor, the main pull-up transistor being of a first type; and a plurality of first trim transistors, each of the plurality of first trim transistors being of a second type.)

1. A data output buffer, the data output buffer comprising:

A pull-up main driver coupled between a power supply terminal and an output terminal, the pull-up main driver configured to output data of a high level; and

a pull-down main driver coupled between the output terminal and a ground terminal, the pull-down main driver configured to output data of a low level,

wherein the pull-up master driver includes:

A main pull-up transistor, the main pull-up transistor being of a first type; and

A plurality of first trim transistors, each of the plurality of first trim transistors being of a second type.

2. The data output buffer of claim 1,

Wherein the transistors of the first type are PMOS transistors, and

Wherein the second type of transistor is an NMOS transistor.

3. The data output buffer of claim 1, wherein the main pull-up transistor and the plurality of first trim transistors are coupled in parallel between the power supply terminal and the output terminal.

4. the data output buffer of claim 3,

wherein the main pull-up transistor outputs data of a high level in response to the pull-up main data, and

Wherein the plurality of first trim transistors correct the high level data in response to a pull-up trim code.

5. The data output buffer of claim 4, wherein the plurality of first trim transistors are all turned off when the main pull-up transistor is turned off.

6. the data output buffer of claim 3,

Wherein the main pull-up transistor comprises a low voltage PMOS transistor, and

wherein the plurality of first trim transistors comprise low voltage NMOS transistors.

7. the data output buffer of claim 6, further comprising a blocking transistor coupled between the pull-up main driver and the power supply terminal and configured to block a current path in response to a blocking signal.

8. The data output buffer of claim 7, wherein the blocking transistor comprises a non-low voltage PMOS transistor.

9. The data output buffer of claim 1, wherein the pull-down master driver comprises:

A main pull-down transistor of the second type; and

A plurality of second trim transistors, each of the plurality of second trim transistors being of the second type.

10. The data output buffer of claim 9, wherein the main pull-down transistor and the plurality of second trim transistors are coupled in parallel between the output terminal and the ground terminal.

11. the data output buffer of claim 10,

wherein the main pull-down transistor outputs data of a low level in response to pulling down main data, and

Wherein the plurality of second trim transistors correct the low level data in response to a pull-down trim code.

12. the data output buffer of claim 11, wherein the plurality of second trim transistors are all off when the main pull-down transistor is off.

13. the data output buffer of claim 9, wherein the main pull-down transistor and the plurality of second trim transistors comprise low voltage NMOS transistors.

14. The data output buffer of claim 13, further comprising a blocking transistor coupled between the pull-down main driver and the ground terminal and configured to block a current path in response to a blocking signal.

15. The data output buffer of claim 14, wherein the blocking transistor comprises a non-low voltage NMOS transistor.

16. a memory device, the memory device comprising:

A memory cell array configured to store data;

Peripheral circuitry configured to perform a program operation, a read operation, an erase operation, or an output operation on the memory cell array; and

Control logic configured to control the peripheral circuitry in response to commands received from a memory controller,

Wherein the peripheral circuit comprises:

A pull-up main driver including a first type transistor and a second type transistor and configured to output data of a high level to the memory controller according to control of the control logic during the output operation; and

A pull-down master driver including the second type transistor and configured to output data of a low level to the memory controller according to control of the control logic during the output operation.

17. The storage device of claim 16, wherein the pull-up master drive comprises:

A main pull-up transistor of the first type; and

a plurality of first trim transistors, each of the plurality of first trim transistors being of the second type.

18. The memory device of claim 17, wherein the main pull-up transistor and the plurality of first trim transistors are coupled in parallel between a power supply terminal and an output terminal.

19. the storage device as set forth in claim 18,

wherein the main pull-up transistor outputs data of a high level in response to the pull-up main data, and

Wherein the plurality of first trim transistors correct the high level data in response to a pull-up trim code.

20. The storage device of claim 16, wherein the pull-down master driver comprises:

A main pull-down transistor, the main pull-down transistor being of the second type; and

A plurality of second trim transistors, each of the plurality of second trim transistors being of the second type.

21. The memory device of claim 20, wherein the main pull-down transistor and the plurality of second trim transistors are coupled in parallel between a ground terminal and an output terminal.

22. The storage device as set forth in claim 21,

wherein the main pull-down transistor outputs data of a low level in response to pulling down main data, and

wherein the plurality of second trim transistors correct the low level data in response to a pull-down trim code.

23. the memory device of claim 16, further comprising a first blocking transistor and a second blocking transistor configured to selectively activate the pull-up master driver and the pull-down master driver, respectively.

24. The memory device of claim 23, wherein the first blocking transistor is coupled between a power supply terminal and the pull-up main driver and forms a current path or blocks a current path according to control of the control logic.

25. The memory device of claim 23, wherein the second blocking transistor is coupled between a ground terminal and the pull-down main driver and forms a current path or blocks a current path according to control of the control logic.

26. the storage device of claim 23, wherein the control logic comprises:

A command detector configured to detect whether a command received from the memory controller is an internal operation command or an output command, and output information on a detection result together with the command; and

an operation controller configured to output a first blocking signal and a second blocking signal for controlling the first blocking transistor and the second blocking transistor, respectively, in response to the command received from the command detector and the information on the detection result.

27. The storage device of claim 26, wherein the command detector is configured to:

When the command received from the memory controller is the output command, enabling the first blocking signal and the second blocking signal such that both the pull-up master driver and the pull-down master driver are disabled, and

Disabling the first blocking signal and the second blocking signal when the command received from the memory controller is the internal operation command, such that both the pull-up master driver and the pull-down master driver are activated.

28. The memory device of claim 27, wherein an output node of the pull-up main driver and an output node of the pull-down main driver float when the first blocking signal and the second blocking signal are enabled.

29. A data output buffer, the data output buffer comprising:

A pull-up driver configured to pull-up data; and

A pull-down driver configured to pull down data,

Wherein the pull-up driver comprises:

A PMOS transistor configured to pull up data; and

one or more NMOS transistors configured to emphasize or de-emphasize the pull-up of the data in response to pull-up trimming codes respectively corresponding to the one or more NMOS transistors, and

Wherein the pull-down driver includes:

a main transistor configured to pull down data; and

One or more trim transistors configured to emphasize or de-emphasize pull-down of data in response to pull-down trim codes respectively corresponding to the one or more trim transistors.

Technical Field

Embodiments of the present invention relate to a data output buffer and a memory device having the same. In particular, the embodiments relate to a data output buffer including a pull-up master driver and a pull-down master driver.

Background

the storage device may store data and output the stored data. The storage device may be a volatile storage device that loses stored data when power is blocked or disconnected, or a non-volatile storage device that retains stored data even when power is blocked or disconnected. The storage device may include: a memory cell array storing data; peripheral circuitry that performs various operations including a program operation, a read operation, and an erase operation; and control logic that controls the peripheral circuitry.

The storage controller may control data communication between the host and the storage device.

The storage device may communicate with the storage controller through a channel. For example, a data output buffer among peripheral circuits included in the memory device may output data read from the memory device via the channel.

Disclosure of Invention

various embodiments relate to a data output buffer capable of reducing capacitance and a memory device including the same.

According to one embodiment, a data output buffer may include: a pull-up main driver coupled between a power supply terminal and an output terminal, the pull-up main driver configured to output data of a high level; and a pull-down main driver coupled between the output terminal and a ground terminal, the pull-down main driver configured to output data of a low level, wherein the pull-up main driver includes: a main pull-up transistor, the main pull-up transistor being of a first type; and a plurality of first trim (trim) transistors, each of the plurality of first trim transistors being of a second type.

According to one embodiment, a storage device may include: a memory cell array configured to store data; peripheral circuitry configured to perform a program operation, a read operation, an erase operation, or an output operation on the memory cell array; and control logic configured to control the peripheral circuitry in response to commands received from a memory controller, wherein the peripheral circuitry comprises: a pull-up main driver including a first type transistor and a second type transistor and configured to output data of a high level to the memory controller according to control of the control logic during the output operation; and a pull-down main driver including the second type transistor and configured to output data of a low level to the memory controller according to control of the control logic during the output operation.

According to one embodiment, a data output buffer may include: a pull-up driver configured to pull-up data; and a pull-down driver configured to pull down data, wherein the pull-up driver includes: a PMOS transistor configured to pull up data; and one or more NMOS transistors configured to emphasize or de-emphasize a pull-up of (de-emphasze) data in response to pull-up fine codes respectively corresponding to the one or more NMOS transistors, and wherein the pull-down driver includes: a main transistor configured to pull down data; and one or more trim transistors configured to emphasize or de-emphasize the pull-down of the data in response to pull-down trim codes respectively corresponding to the one or more trim transistors.

Drawings

FIG. 1 is a diagram illustrating a storage system according to one embodiment of the present disclosure;

FIG. 2 is a diagram illustrating a storage device such as the storage device shown in FIG. 1;

FIG. 3 is a diagram illustrating control logic such as that shown in FIG. 2;

FIG. 4 is a diagram illustrating a data output buffer according to one embodiment of the present disclosure;

FIG. 5 is a diagram illustrating a pull-up pre-driver, such as the pull-up pre-driver shown in FIG. 4, according to one embodiment of the present disclosure;

FIG. 6 is a diagram illustrating a pull-up trim circuit, such as the pull-up trim circuit shown in FIG. 5, according to one embodiment of the present disclosure;

FIG. 7 is a diagram illustrating a pull-down pre-driver such as the pull-down pre-driver shown in FIG. 4;

FIG. 8 is a diagram illustrating a pull-down trim circuit, such as the pull-down trim circuit shown in FIG. 7, according to one embodiment of the present disclosure;

FIG. 9 is a diagram illustrating a pull-up master drive such as that shown in FIG. 4;

Fig. 10 is a diagram illustrating a pull-up master driver such as the pull-up master driver shown in fig. 4 according to another embodiment of the present disclosure;

FIG. 11 is a diagram illustrating a pull-down master such as the one shown in FIG. 4;

Fig. 12 is a diagram illustrating a pull-down main driver such as the pull-down main driver shown in fig. 4 according to another embodiment of the present disclosure;

FIG. 13 is a diagram illustrating another embodiment of a storage system including the storage device shown in FIG. 2;

FIG. 14 is a diagram illustrating another embodiment of a storage system including the storage device shown in FIG. 2;

FIG. 15 is a diagram illustrating another embodiment of a storage system including the storage device shown in FIG. 2; and

fig. 16 is a diagram illustrating another embodiment of a storage system including the storage device shown in fig. 2.

Detailed Description

Various embodiments will now be described more fully with reference to the accompanying drawings. However, the elements and features of the present invention may be configured or arranged differently than as disclosed herein. Accordingly, the present invention is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. Throughout the specification, references to "one embodiment," "another embodiment," and so forth, do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment.

It will be understood that when an element is referred to as being "coupled" or "connected" to a particular element, it can be directly coupled or connected to the particular element or be indirectly coupled or connected to the particular element with one or more intervening elements therebetween. Communication between elements may be wired or wireless, depending on whether the two elements are directly or indirectly connected or coupled, unless otherwise specified or otherwise context dictates. In the specification, when an element is referred to as being "comprising" or "including" a component, such open-ended phrases do not preclude the presence or addition of one or more other components, unless specifically stated or the context dictates otherwise.

fig. 1 is a diagram illustrating a storage system 1000.

referring to fig. 1, an electronic system 10000 may include a storage system 1000 and a host 2000 controlling the storage system 1000.

The storage system 1000 may include: a storage device 1100 that stores data; a buffer memory 1300 that temporarily stores data for the operation of the storage system 1000; and a storage controller 1200 controlling the storage device 1100 and the buffer memory 1300 in response to control of the host 2000.

The host 2000 may communicate with the storage system 1000 using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), register DIMM (rdimm), and load reduced DIMM (lrdimm).

The storage device 1100 may include a volatile storage device that loses stored data when power is blocked or interrupted or a non-volatile storage device that retains stored data even when power is blocked or interrupted. The memory controller 1200 may control the memory device 1100 to perform a program operation, a read operation, or an erase operation. For example, during a program operation, the memory device 1100 may receive a command, an address, and data from the memory controller 1200 and perform the program operation. During a read operation, the memory device 1100 may receive a command and an address from the memory controller 1200 and output read data to the memory controller 1200. The memory device 1100 may include input/output circuits for inputting and outputting data.

the storage controller 1200 may control the overall operation of the storage system 1000 and control data exchange between the host 2000 and the storage device 1100. For example, the memory controller 1200 may control the memory device 1100 to program data, read data, or erase data in response to a request from the host 2000. In addition, the memory controller 1200 may receive data and logical addresses from the host 2000 and convert the logical addresses into physical addresses indicating areas where the data is stored. In addition, the memory controller 1200 may store a logical-physical address mapping table configuring a mapping relationship between logical addresses and physical addresses in the buffer memory 1300.

The buffer memory 1300 may be used as an operation memory or a cache memory of the memory controller 1200, and the buffer memory 1300 may store system data used in the memory system 1000 in addition to storing the above-described information. According to embodiments, buffer memory 1300 may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data 4(LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR), or Rambus Dynamic Random Access Memory (RDRAM).

Fig. 2 is a diagram illustrating a memory device (e.g., the memory device 1100 shown in fig. 1).

Referring to fig. 2, a storage device 1100 may be a volatile storage device or a nonvolatile storage device. Although fig. 2 shows a nonvolatile memory device as an embodiment, the present invention is not limited thereto.

the memory device 1100 may include a memory cell array 100 storing data. The memory device 1100 may include a peripheral circuit 200, the peripheral circuit 200 being configured to perform a program operation for storing data in the memory cell array 100, a read operation for reading the stored data, an erase operation for erasing the stored data, or an output operation for outputting the read data. The memory device 1100 may include control logic 300, the control logic 300 configured to control the peripheral circuit 200 in response to control of the memory controller 1200 shown in fig. 1.

The memory cell array 100 may include a plurality of memory blocks. The memory block may store user data and various types of information for performing operations of the memory device 1100. The memory block may have a two-dimensional structure or a three-dimensional structure. The latter configuration provides a higher degree of integration. The two-dimensional memory block may have memory cells arranged in parallel with the substrate, and the three-dimensional memory block may have memory cells stacked in a direction perpendicular to the substrate.

The control logic 300 may control the peripheral circuit 200 to perform a program operation, a read operation, and an erase operation. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input/output circuit 250, and a current sensing circuit 260.

The voltage generation circuit 210 may generate various operation voltages Vop for performing a program operation, a read operation, and an erase operation in response to the operation CODE V _ CODE. Examples of the operating voltage Vop generated by the voltage generation circuit 210 in response to the control logic 300 may include a program voltage, a verify voltage, a pass voltage, a read voltage, and an erase voltage.

the row decoder 220 may transmit the operation voltage Vop to a local line LL coupled to a selected memory block among the memory blocks of the memory cell array in response to a row address RADD. The local lines LL may include local word lines, local drain select lines, and local source select lines. Further, the local line LL may include various lines (such as source lines) coupled to the memory block.

The page buffer group 230 may be coupled to bit lines BL1 to BLI coupled to memory blocks of the memory cell array 100. The page buffer group 230 may include a plurality of page buffers PB1 to PBI coupled to bit lines BL1 to BLI, respectively. The page buffers PB1 through PBI may operate in response to page buffer control signals PBSIGNALS. For example, during a read operation or a verify operation, the page buffers PB1 to PBI may temporarily store data received through the bit lines BL1 to BLI, or may sense voltages or currents in the bit lines BL1 to BLI, respectively.

the column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230 in response to a column address CADD. For example, the column decoder 240 may exchange data with the page buffers PB1 to PBI through the data lines DL or with the input/output circuit 250 through the column lines CL.

The input/output circuit 250 may receive a command CMD, an address ADD, and data from the memory controller 1200 shown in fig. 1 through an input/output pad DQ, and output the read data to the memory controller 1200 through the input/output pad DQ. For example, the input/output circuit 250 may transmit a command CMD and an address ADD from the memory controller 1200 shown in fig. 1 to the control logic 300, or may exchange DATA with the column decoder 240. Also, when data is not output, the first blocking signal V _ BL1 and the second blocking signal V _ BL2 may be activated or enabled, and the input/output circuit 250 may block current or voltage leakage in response to the first blocking signal V _ BL1 and the second blocking signal V _ BL 2. The first blocking signal V _ BL1 and the second blocking signal V _ BL2 may be output by the control logic 300 according to the configuration of the input/output circuit 250. For example, when the input/output circuit 250 includes low voltage transistors, the first blocking signal V _ BL1 and the second blocking signal V _ BL2 may be used.

during a read operation or a verify operation, the current sensing circuit 260 may generate a reference current in response to the allowable BIT VRY _ BIT < # > and compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current to output a PASS signal PASS or a FAIL signal FAIL.

Control logic 300 may receive commands CMD and addresses ADD in response to signals received through pads CE #, WE #, RE #, ALE, CLE, and WP #. The control logic 300 may control the peripheral circuit 200 by outputting an operation CODE V _ CODE, a row address RADD, a page buffer control signal PBSIGNALS, and an allowable BIT VRY _ BIT < # > in response to a command CMD and an address ADD. Control logic 300 may determine whether the verify operation passed or failed in response to PASS signal PASS or FAIL signal FAIL. Further, the control logic 300 may output the first blocking signal V _ BL1 and the second blocking signal V _ BL2 in response to the received command. For example, the control logic 300 may activate or enable the first blocking signal V _ BL1 and the second blocking signal V _ BL2 when receiving a data output command, and may deactivate or disable the first blocking signal V _ BL1 and the second blocking signal V _ BL2 when receiving a command associated with an internal operation of the memory device 1100 without outputting data.

Fig. 3 is a diagram illustrating control logic (e.g., control logic 300 shown in fig. 2).

Referring to fig. 3, the control logic 300 may include an Operation (OP) controller 310 and a Command (CMD) detector 320.

The CMD detector 320 may determine the type of the command CMD received from the memory controller 1200 of fig. 1 and transmit information about the detection result to the OP controller 310 together with the command CMD. For example, the command CMD from the memory controller 1200 may include a command for an internal operation (internal operation command) of the memory device 1100 of fig. 1 and a command for outputting result data of the internal operation (output command). For example, the internal operation command may include a program command, a read command, and an erase command, and the output command may be a command to output result data of a read operation performed in response to the read command.

When the OP controller 310 detects that the command received from the CMD detector 320 is an internal operation command, the OP controller 310 may output operation signals (V _ CODE, PBSIGNALS, and VRY _ BIT < #) to execute the received command. When performing the internal operation, the OP controller 310 may disable or disable the first blocking signal V _ BL1 and the second blocking signal V _ BL 2. When detecting that the command received from the CMD detector 320 is an output command, the OP controller 310 may output a signal for an output operation among the operation signals (V _ CODE, PBSIGNALS, and VRY _ BIT < # >), and keep the first blocking signal V _ BL1 and the second blocking signal V _ BL2 activated or enabled while data is being output.

The CMD detector 320 can be eliminated according to the transistors constituting the input/output circuit 250. For example, CMD detector 320 can be included in control logic 300 when input/output circuit 250 includes low voltage transistors. However, when input/output circuit 250 includes normal transistors, CMD detector 320 can be eliminated. The low voltage transistor may be turned on by a lower voltage than the normal transistor.

When the control logic 300 does not include the CMD detector 320, the command CMD received from the host 2000 may be directly input to the OP controller 310, and the OP controller 310 may output operation signals (V _ CODE, PBSIGNALS, and VRY _ BIT < # >) in response to the input command. The CMD detector 320 may not output the first blocking signal V _ BL1 and the second blocking signal V _ BL 2.

Fig. 4 is a diagram illustrating a data output buffer 500 according to an embodiment.

Referring to fig. 4, the input/output circuit 250 shown in fig. 2 may include a data output buffer 500 for outputting data.

The DATA output buffer 500 may amplify the DATA received through the column line CL of fig. 2 and output the amplified DATA through the input/output pad DQ. The data output buffer 500 may include a pull-up predriver 510, a pull-down predriver 520, a pull-up master driver 530, and a pull-down master driver 540.

the pull-up pre-driver 510 may output pull-up main DATA PU _ MD and pull-up fine adjustment code PUTR < k:1> according to the received DATA DATA. The inverted DATA of the received DATA may be output as the pull-up main DATA PU _ MD while maintaining the wobble width of the received DATA. For example, the pull-up pre-driver 510 may output the low-level pull-up main DATA PU _ MD when the received DATA is high, and may output the high-level pull-up main DATA PU _ MD when the received DATA is low. The expressions low level and high level refer to subject data of low level or high level, respectively.

the pull-up trimming code PUTR < k:1> may include a code for correcting the pull-up main DATA PU _ MD according to the received DATA DATA. For example, when the wobble width of the received DATA is smaller than the reference width, a code for increasing the wobble width may be output, and when the wobble width of the received DATA is larger than the reference width, a code for decreasing the wobble width may be output. The pull-up fine adjustment code PUTR < k:1> may be output in an inverted form. The pull-up fine adjustment code PUTR < k:1> may be composed of either or both of "0" bits and "1" bits. Since the correction resolution increases as the number of bits included in the pull-up fine adjustment code PUTR < k:1> increases, the pull-up main data PU _ MD can be corrected more finely. However, since the number of transistors turned on or off according to the pull-up trimming code PUTR < k:1> increases as the number of bits in the pull-up trimming code PUTR < k:1> increases, the number of bits of the pull-up trimming code PUTR < k:1> may be set in consideration of the size of the data output buffer 500.

The pull-down pre-driver 520 may output pull-down main DATA PD _ MD and a pull-down trim code PDTR < k:1> according to the received DATA. The inverted DATA of the received DATA may be output as the pull-down master DATA PD _ MD while maintaining the swing width of the received DATA. For example, the pull-down pre-driver 520 may output a high level pull-down main DATA PD _ MD when the received DATA is a low level, and may output a low level pull-down main DATA PD _ MD when the received DATA is a high level.

the pull-down trimming code PDTR < k:1> may include a code for correcting the pull-down master DATA PD _ MD based on the received DATA. For example, when the wobble width of the received DATA is smaller than the reference width, a code for increasing the wobble width may be output, and when the wobble width of the received DATA is larger than the reference width, a code for decreasing the wobble width may be output. The pull-down trim code PDTR < k:1> may be composed of either or both of "0" bits and "1" bits. The number of bits of the pull-down trim code PDTR < k:1> may depend on the size of the data output buffer 500.

the pull-up main driver 530 may output high-level data to the input/output pad DQ in response to the pull-up main data PU _ MD and the pull-up trimming code PUTR < k:1 >. For example, the pull-up main driver 530 may output high-level data to the input/output pad DQ when receiving low-level pull-up main data PU _ MD. When the high level pull-up main data PU _ MD is received, the pull-up main driver 530 may not output data. When the pull-up main driver 530 does not output data, an output node of the pull-up main driver 530 may be floated.

The pull-down master driver 540 may output low-level data to the input/output pad DQ in response to the pull-down master data PD _ MD and the pull-down trim code PDTR < k:1 >. For example, the pull-down main driver 540 may output low-level data to the input/output pad DQ when receiving high-level pull-down main data PD _ MD. For example, when receiving the low level pull-down master data PD _ MD, the pull-down master driver 540 may not output data. When the pull-down main driver 540 does not output data, the output node of the pull-down main driver 540 may be floated.

Fig. 5 is a diagram illustrating the pull-up pre-driver 510 shown in fig. 4.

Referring to fig. 5, the pull-up pre-driver 510 may include a pull-up (PU) main circuit 511 and a pull-up (PU) fine tuning circuit 512.

The PU master circuit 511 may invert the received DATA and output the pull-up master DATA PU _ MD. For example, the PU main circuit 511 may output the low-level pull-up main DATA PU _ MD when receiving the high-level DATA, and may output the high-level pull-up main DATA PU _ MD when receiving the low-level DATA. Further, the PU main circuit 511 may keep the swing width of the pull-up main DATA PU _ MD the same as the swing width of the received DATA by reflecting the swing width of the received DATA.

The PU trimming circuit 512 may output a pull-up trimming code PUTR < k:1> for correcting the pull-up main DATA PU _ MD according to the received DATA DATA. For example, the PU trimming circuit 512 may output a pull-up trimming code PUTR < k:1> to increase the wobble width of the received DATA DATA when the wobble width is smaller than the reference width, and may output a pull-up trimming code PUTR < k:1> to decrease the wobble width of the received DATA DATA when the wobble width is larger than the reference width. In addition, the PU trimming circuit 512 may control the number of "0" bits and "1" bits included in the pull-up trimming code PUTR < k:1> according to a difference between the wobble width of the received DATA and the reference width. For example, the PU trim circuit 512 may output a pull-up trim code PUTR < k:1> by combining "0" bits and "1" bits according to the received DATA DATA.

fig. 6 is a diagram illustrating a pull-up (PU) trim circuit, such as pull-up (PU) trim circuit 512 shown in fig. 5, according to one embodiment of the present disclosure.

Referring to fig. 6, the PU trim circuit 512 may include a trim circuit 512a and a pull-up (PU) inverter circuit 512 b.

The trimming circuit 512a may receive the DATA and output a sub-code SCM < k:1> for correcting the received DATA. The sub-code SCM < k:1> may comprise a plurality of bits.

The pull-up inverting circuit 512b may invert the sub-code SCM < k:1> and output the inverted sub-code as the pull-up fine adjustment code PUTR < k:1 >. For example, when the sub-code SCM < k:1> having the value "001011." is output, the pull-up trim code PUTR < k:1> may be output as "110100.", by inverting the value "001011." of the sub-code SCM < k:1 >. Among the transistors in the pull-up main driver 530 shown in fig. 4, the transistor operating in response to the pull-up trim code PUTR < k:1> may be an NMOS transistor instead of a PMOS transistor. In other words, when the transistors operating in response to the pull-up trim code PUTR < k:1> are PMOS transistors, the sub-code SCM < k:1> may be directly transferred to the pull-up main driver 530. However, according to the present embodiment, since the transistors operating in response to the pull-up trimming code PUTR < k:1> are NMOS transistors, an inverted version of the sub-code SCM < k:1> may be transferred to the pull-up main driver 530 as the pull-up trimming code PUTR < k:1 >. When the pull-up main data PU _ MD has a high level, the pull-up main driver 530 will not output data, so the fine tuning circuit 512a can output all 1 sub-codes SCM < k:1> and the PU inverse circuit 512b can output all 0 pull-up fine tuning codes PUTR < k:1 >.

Fig. 7 is a diagram illustrating the pull-down pre-driver 520 shown in fig. 4.

Referring to fig. 7, the pull-down pre-driver 520 may include a pull-down (PD) main circuit 521 and a pull-down (PD) trimming circuit 522.

The PD master circuit 521 may invert the received DATA and output pull-down master DATA PD _ MD. For example, the PD main circuit 521 may output the low-level pull-down main DATA PD _ MD when receiving the high-level DATA, and may output the high-level pull-down main DATA PD _ MD when receiving the low-level DATA. Further, the PD main circuit 521 can keep the swing width of the pull-down main DATA PD _ MD the same as that of the received DATA by directly reflecting the swing width of the received DATA.

The PD trimming circuit 522 may output a pull-down trimming code PDTR < k:1> for correcting the pull-down master DATA PD _ MD based on the received DATA. For example, the PD trimming circuit 522 may output a pull-down trimming code PDTR < k:1> to increase the wobble width of the received DATA DATA when the wobble width is smaller than the reference width, and may output a pull-down trimming code PDTR < k:1> to decrease the wobble width of the received DATA DATA when the wobble width is larger than the reference width. Further, the PD trimming circuit 522 may control the number of "0" bits and "1" bits included in the pull-down trimming code PDTR < k:1> according to the difference between the wobble width and the reference width of the received DATA. For example, the PD trimming circuit 522 may output the pull-down trimming code PDTR < k:1> by combining "0" bits and "1" bits according to the received DATA.

Fig. 8 is a diagram illustrating an embodiment of PD trimming circuit 522 shown in fig. 7.

referring to fig. 8, the PD trimming circuit 522 may receive DATA and output a pull-down trimming code PDTR < k:1> for correcting the received DATA. The pull-down trim code PDTR < k:1> may comprise a plurality of bits. For example, when the pull-down trimming code PDTR < k:1> is output as "010011." the code "010011." can be output to the pull-down main driver 540 shown in fig. 4.

in other words, PD trimming circuit 522 may perform the same functions as trimming circuit 512a of fig. 6. PD trimming circuit 522 may be configured to correct the minimum voltage level used to generate the data, and trimming circuit 512a may be configured to correct the maximum voltage level used to generate the data.

Fig. 9 is a diagram illustrating the pull-up main driver 530 shown in fig. 4.

referring to fig. 9, the pull-up main driver 530 may include a pull-up transistor 531. The pull-up transistor 531 may be coupled between a power VCC terminal and an input/output pad DQ.

Pull-up transistor 531 may include a main pull-up data output circuit MPUDO and a pull-up trim output circuit pull.

the main pull-up data output circuit MPUDO may include a main pull-up transistor MPUTR that is turned on or off in response to the pull-up main data PU _ MD. The main pull-up transistor MPUTR may be a first type of transistor, e.g., a PMOS transistor. Accordingly, when the low level pull-up main DATA PU _ MD is received, the main pull-up transistor mptr may be turned on to couple the power VCC terminal and the input/output pad DQ so that the high level DATA may be output. When the high-level pull-up main data PU _ MD is received, the main pull-up transistor mptr may be turned off, so that the output node of the pull-up main driver 530 may be floated. For this reason, all transistors included in the pull-up trimming output circuit PUTRO are necessarily turned off.

the pull-up trimming output circuit PUTRO may be composed of a second type (e.g., NMOS) transistor. For example, the pull-up trimming output circuit PUTRO may include first through kth trimming transistors N1 through Nk. The first through kth trimming transistors N1 through Nk may be coupled in parallel between a power supply VCC terminal and an input/output pad DQ. In other words, the main pull-up transistor mptr and the first through k-th trim transistors N1 through Nk may be coupled in parallel between the power supply VCC terminal and the input/output pad DQ. The first through kth trim transistors N1 through Nk may all be NMOS transistors. The NMOS transistor may be turned on in response to a lower turn-on voltage than the PMOS transistor. In other words, the NMOS transistor may allow a larger amount of current to flow than the PMOS transistor in response to the same turn-on voltage. Therefore, when all of the first through k-th trim transistors N1 through Nk are NMOS transistors, the overall size of the pull-up trim output circuit purro can be reduced. In addition, since the first through k-th trimming transistors N1 through Nk can be operated at a low voltage, the capacitance occurring in the pull-up trimming output circuit PUTRO can be reduced.

The first through kth trimming transistors N1 through Nk may be turned on or off in response to respective bits included in the pull-up trimming code PUTR < k:1 >. For example, when the first pull-up trimming code PUTR <1> is "1", the first trimming transistor N1 may be turned on, and when the first pull-up trimming code PUTR <1> is "0", the first trimming transistor N1 may be turned off. When the number of turned-on NMOS transistors increases, an emphasis function may be performed. On the other hand, when the number of turned-on NMOS transistors decreases, a de-emphasis function may be performed.

The first through kth trim transistors N1 through Nk may have the same or different sizes. For example, when the first through kth trim transistors N1 through Nk have the same size, the number of turned-on NMOS transistors increases as the number of "1" bits included in the pull-up trim code PUTR < k:1> increases, and thus the amount of current flowing through the pull-up main driver 530 may increase. On the other hand, when the number of "0" bits included in the pull-up trimming code PUTR < k:1> is increased, the number of NMOS transistors that are turned on may be decreased. As a result, the amount of current flowing through the pull-up main driver 530 may be reduced. According to another embodiment, when the first through kth trim transistors N1 through Nk have different sizes, the amount of current flowing through the pull-up main driver 530 may increase when the large-sized transistors are turned on, and the amount of current flowing through the pull-up main driver 530 may decrease when the small-sized transistors are turned on. Accordingly, the PU trimming circuit 512 of FIG. 5 may be designed such that the pull-up trimming code PUTR < k:1> may be output in consideration of the sizes of the first through k-th trimming transistors N1 through Nk.

As described above, when the master pull-up transistor MPUTR is a PMOS transistor and the pull-up trimming output circuit purro is composed of an NMOS transistor, an output signal having a full swing may be output through the PMOS transistor, the size of the pull-up master driver 530 may be reduced through the NMOS transistor, and the capacitance may also be reduced. For example, when the pull-up main driver 530 includes all NMOS transistors, an output signal having a narrower swing width than a PMOS transistor may be output. Therefore, according to this embodiment, the main pull-up transistor MPUTR operating in response to the pull-up main data PU _ MD may be a PMOS transistor, and the first through k-th trim transistors N1 through Nk for correcting the output signal may be NMOS transistors.

Fig. 10 is a diagram illustrating another embodiment of the pull-up main driver 530 shown in fig. 4.

Referring to fig. 10, in order to further reduce the size and capacitance of the pull-up main driver 530, the main pull-up transistor mptr and the first through kth trim transistors N1 through Nk as shown in fig. 9 may be low voltage transistors.

For example, the master pull-up transistor MPUTR included in the pull-up master driver 530' may be a low voltage master pull-up transistor L _ MPUTR, and the first through kth trim transistors N1 through Nk may be low voltage first through kth trim transistors L _ N1 through L _ Nk. The low voltage transistor may have a smaller size than a normal transistor and operate in response to a lower voltage. However, when the low voltage transistor is turned off, current leakage may occur. Therefore, a first blocking transistor TR _ BL1 may be further included to prevent current leakage of the low voltage transistor.

The first blocking transistor TR _ BL1 may be coupled between the power source VCC terminal and the pull-up transistor 531, and may be a normal transistor instead of a low voltage transistor. For example, the first blocking transistor TR _ BL1 may be a normal PMOS transistor. The first blocking transistor TR _ BL1 may be turned on or off in response to a first blocking signal V _ BL1 output from the control logic 300 of fig. 2. The control logic 300 may disable or disable the first blocking signal V _ BL1 to a high level when an output operation is not performed, and may enable or disable the first blocking signal V _ BL1 to a low level when an output operation is performed. Accordingly, the first blocking transistor TR _ BL1 may be kept off when the output operation is not performed, and may be kept on when the output operation is performed.

Fig. 11 is a diagram illustrating the pull-down main driver 540 shown in fig. 4.

Referring to fig. 11, the pull-down main driver 540 may include a pull-down transistor 541. The pull-down transistor 541 may be coupled in series between the input/output pad DQ and the ground VSS terminal. For example, pull-down transistor 541 may be coupled between a ground VSS terminal and an input/output pad DQ. The pull-down transistor 541 may be directly coupled to the ground VSS terminal and perform an emphasis function or a de-emphasis function.

the pull-down transistor 541 may include a main pull-down data output circuit MPDDO and a pull-down trim output circuit PDTRO.

The main pull-down data output circuit MPDDO may include a main pull-down transistor MPDTR turned on or off in response to the pull-down main data PD _ MD. The main pull-down transistor MPDTR may be a second type transistor, e.g., an NMOS transistor. Accordingly, when receiving the high-level pull-down main DATA PD _ MD, the main pull-down transistor MPDTR may be turned on to couple the ground VSS terminal and the input/output pad DQ, so that the low-level DATA L _ DATA may be output. When receiving the low-level pull-down main data PD _ MD, the main pull-down transistor MPDTR may be turned off, so that the output node of the pull-down main driver 540 may be floated. For this reason, all transistors included in the pull-down trimming output circuit PDTRO are necessarily turned off.

The pull-down trimming output circuit PDTRO may be composed of a second type (e.g., NMOS) transistor. For example, the pull-down trimming output circuit PDTRO may include first to kth trimming transistors N1 to Nk. Since the first through kth trimming transistors N1 through Nk included in the pull-down trimming output circuit PDTRO are physically different from the first through kth trimming transistors N1 through Nk included in the pull-up trimming output circuit purtro, the first through kth trimming transistors N1 through Nk described with reference to fig. 11 may be included in the pull-down trimming output circuit PDTRO.

The first through kth trim transistors N1 through Nk may be coupled in parallel between the input/output pad DQ and the ground VSS terminal. In other words, the main pull-down transistor MPDTR and the first through k-th trim transistors N1 through Nk may be coupled in parallel between the input/output pad DQ and the ground VSS terminal. The first through k-th trim transistors may all be NMOS transistors.

The first through kth trim transistors N1 through Nk may be turned on or off in response to respective bits included in the pull-down trim code PDTR < k:1 >. For example, when the first pull-down trim code PDTR <1> is "1", the first trim transistor N1 may be turned on, and when the first pull-down trim code PDTR <1> is "0", the first trim transistor N1 may be turned off. When the number of turned-on NMOS transistors increases, an emphasis function may be performed. On the other hand, when the number of turned-on NMOS transistors decreases, a de-emphasis function may be performed.

the first through kth trim transistors N1 through Nk may have the same or different sizes. For example, when the first through kth trim transistors N1 through Nk have the same size, the number of turned-on NMOS transistors increases as the number of "1" bits included in the pull-down trim code PDTR < k:1> increases, and thus the amount of current flowing through the pull-down main driver 540 may increase. On the other hand, when the number of "0" bits included in the pull-down trimming code PDTR < k:1> increases, the number of NMOS transistors that are turned on can be reduced. As a result, the amount of current flowing through the pull-down main driver 540 may be reduced. According to another embodiment, when the first through k-th trim transistors N1 through Nk have different sizes, the amount of current flowing through the pull-down main driver 540 may increase when the large-sized transistors are turned on, and the amount of current flowing through the pull-down main driver 540 may decrease when the small-sized transistors are turned on. Accordingly, the PD trimming circuit 522 of fig. 7 may be designed such that the pull-down trimming code PDTR < k:1> may be output in consideration of the sizes of the first through k-th trimming transistors N1 through Nk.

fig. 12 is a diagram illustrating another embodiment of the pull-down master driver 540 shown in fig. 4.

Referring to fig. 12, in order to further reduce the size and capacitance of the pull-down main driver 540, the main pull-down transistor MPDTR and the first through k-th trim transistors N1 through Nk as shown in fig. 11 may be low voltage transistors.

For example, the main pull-down transistor MPDTR included in the pull-down main driver 540' may be a low-voltage main pull-down transistor L _ MPDTR, and the first through k-th trim transistors N1 through Nk may be low-voltage first through k-th trim transistors L _ N1 through L _ Nk. The low voltage transistor may have a smaller size than a normal transistor and operate in response to a low voltage. However, when the low voltage transistor is turned off, current leakage may occur. Therefore, a second blocking transistor TR _ BL2 may be further included to prevent current leakage of the low voltage transistor.

the second blocking transistor TR _ BL2 may be coupled between the ground VSS terminal and the pull-down transistor 541, and is a normal transistor rather than a low-voltage transistor. For example, the second blocking transistor TR _ BL2 may be a normal NMOS transistor. The second blocking transistor TR _ BL2 may be turned on or off in response to a second blocking signal V _ BL2 output from the control logic 300 of fig. 2. The control logic 300 may disable or disable the second blocking signal V _ BL2 to a low level when an output operation is not performed, and may enable or enable the second blocking signal V _ BL2 to a high level when an output operation is performed. Therefore, the second blocking transistor TR _ BL2 may be kept off when the output operation is not performed, and may be kept on when the output operation is performed.

Fig. 13 is a diagram illustrating another embodiment of a storage system 30000 including the storage device 1100 shown in fig. 2.

Referring to fig. 13, the storage system 30000 may be implemented in a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), or a wireless communication device.

The memory system 30000 may include a memory device 1100 and a memory controller 1200 that controls the operation of the memory device 1100. The memory controller 1200 may control a data access operation of the memory device 1100, for example, a program operation, an erase operation, or a read operation of the memory device 1100 in response to the control of the host 2000.

the memory controller 1200 may control data programmed into the memory device 1100 to be output through the display 3200.

The radio transceiver 3300 may exchange radio signals through an antenna ANT. For example, the radio transceiver 3300 may convert a radio signal received through the antenna ANT into a signal that can be processed by the host 2000. Accordingly, the host 2000 may process a signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 may transfer signals processed by the host 2000 to the memory device 1100. In addition, the radio transceiver 3300 may convert a signal output from the host 2000 into a radio signal and output the radio signal to an external device through the antenna ANT. Control signals for controlling the operation of the host 2000 or data to be processed by the host 2000 may be input by the input device 3400, and the input device 3400 may include a pointing device such as a touch pad and a computer mouse, a keyboard, or a keypad. The host 2000 may control the operation of the display 3200 so that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 may be output through the display 3200.

Fig. 14 is a diagram illustrating another embodiment of a memory system 40000 including the memory device 1100 shown in fig. 2.

Referring to fig. 14, the memory system 40000 may be provided as a Personal Computer (PC), a tablet PC, a netbook, an e-reader, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a memory controller 1200 that controls data processing operations of the memory device 1100.

the host 2000 can output data stored in the storage device 1100 through the display 4300 according to data input through the input device 4200. Examples of input devices 4200 include a pointing device such as a touch pad or a computer mouse, a keyboard, or a keypad.

the host 2000 may control the overall operation of the memory system 40000 and control the operation of the memory controller 1200.

Fig. 15 is a diagram illustrating another embodiment of a memory system 50000 including the memory device 1100 shown in fig. 2.

Referring to fig. 15, a memory system 50000 may be implemented in an image processor, for example, a digital camera, a cellular phone with a digital camera attached thereto, a smart phone with a digital camera attached thereto, or a desktop PC with a digital camera attached thereto.

The memory system 50000 may include a memory device 1100 and a memory controller 1200, the memory controller 1200 controlling data processing operations (e.g., a program operation, an erase operation, or a read operation) of the memory device 1100.

The image sensor 5200 of the storage system 50000 may convert the optical image into a digital signal, and the converted digital signal may be transmitted to the host 2000. The converted digital signal may be output through the display 5300 or stored in the storage device 1100 through the storage controller 1200 in response to control of the host 2000. In addition, data stored in the storage device 1100 can be output through the display 5300 according to control of the host 2000.

Fig. 16 is a diagram illustrating another embodiment of a storage system 30000 including the storage device 1100 shown in fig. 2.

referring to fig. 16, a storage system 30000 may include a host 2000 and a memory card 70000.

the memory card 70000 may be implemented in a smart card. The memory card 70000 may include a memory apparatus 1100, a memory controller 1200, and a card interface 7100.

The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. The card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a multimedia card (MMC) interface. In addition, the card interface 7100 may perform interface data exchange between the host 2000 and the memory controller 1200 according to a protocol of the host 2000. Depending on the implementation, card interface 7100 may support the Universal Serial Bus (USB) protocol and/or the inter-chip (IC) -USB protocol. The card interface 7100 may refer to hardware supporting a protocol used by the host 2000, software installed on the hardware, or a signal transmission method.

according to the embodiments of the present disclosure, the capacitance and size of the data output buffer may be reduced.

it will be apparent to those skilled in the art that various modifications may be made to the above-described embodiments of the present invention without departing from the spirit or scope of the invention. Accordingly, it is intended that the invention cover all such modifications as fall within the scope of the appended claims and equivalents thereof.

cross Reference to Related Applications

This application claims korean patent application No.10-2018-0061373, filed on 29.5.2018, which is incorporated herein by reference in its entirety.