阅读说明：本技术 选择器件和存储装置 (Selection device and memory device ) 是由 五十岚实 曾根威之 野野口诚二 清宏彰 大场和博 于 2018-04-06 设计创作，主要内容包括：提供了根据本公开的一个实施例的选择器件,该选择器件具有：第一电极；与第一电极对置的第二电极；半导体层,设置在第一电极和第二电极之间,并且包括从碲(Te)、硒(Se)和硫(S)中选择的至少一种硫族元素,以及包括从硼(B)、铝(Al)、镓(Ga)、磷(P)、砷(As)、碳(C)、锗(Ge)和硅(Si)中选择的至少一种第一元素；以及第一热旁路层,其具有比半导体层高的热导率,并且设置在第一电极和第二电极之间、在半导体层的外围的至少一部分中。(A selection device according to one embodiment of the present disclosure is provided, the selection device having: a first electrode; a second electrode opposed to the first electrode; a semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and including at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and a first heat bypass layer having a higher thermal conductivity than the semiconductor layer and provided between the first electrode and the second electrode in at least a part of a periphery of the semiconductor layer.)

1. A selection device, comprising:

a first electrode;

A second electrode opposed to the first electrode;

A semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and

A first heat bypass layer provided in at least a part of a periphery of the semiconductor layer between the first electrode and the second electrode and having a higher thermal conductivity than the semiconductor layer.

2. The select device of claim 1, wherein the semiconductor layer further comprises at least one second element selected from oxygen (O) and nitrogen (N).

3. The select device of claim 1, wherein the first thermal bypass layer extends to the sides of the first electrode and the second electrode.

4. The select device of claim 1, wherein the first thermal bypass layer comprises an alloy comprising any one of silicon oxide (SiO2) or silicon nitride (Si3N4) doped with carbon (C), boron (B), or phosphorus (P), aluminum oxide (Al2O3), cerium oxide (CeO2), zirconium oxide (ZrO2), silicon carbide (SiC), beryllium oxide (BeO), zinc oxide (ZnO), titanium oxide (TiO2), Boron Arsenide (BAs), antimony boride (BSb), Boron Phosphide (BP), and Boron Nitride (BN).

5. The select device of claim 1, wherein a product of a thermal conductivity and a cross-sectional area of the first thermal bypass layer is greater than a product of a thermal conductivity and a cross-sectional area of the semiconductor layer.

6. The select device of claim 1, wherein the semiconductor layer has an annular shape and the second heat bypass layer is disposed in a central portion of the annular shape.

7. The selection device according to claim 1, wherein the semiconductor layer is changed to a low-resistance state by setting an applied voltage to a predetermined threshold voltage or more and the semiconductor layer is changed to a high-resistance state by reducing the applied voltage to below the predetermined threshold voltage without a phase change between the amorphous phase and the crystalline phase.

8. A memory device is provided with a plurality of memory cells, each of the plurality of memory cells including a memory device and a selection device coupled to the memory device,

the selection device includes:

A first electrode;

A second electrode opposed to the first electrode;

A semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and

a first heat bypass layer provided in at least a part of a periphery of the semiconductor layer between the first electrode and the second electrode and having a higher thermal conductivity than the semiconductor layer.

9. The memory device of claim 8, wherein an electrically and thermally insulating layer is disposed between adjacent select devices.

10. The memory device of claim 9, wherein an electrothermal insulating layer is disposed between adjacent ones of the plurality of memory cells.

11. The memory device of claim 9, wherein the electrothermal insulating layer comprises an alloy comprising a material included in the semiconductor layer, silicon oxide (SiO2), or silicon nitride (Si3N 4).

12. The memory apparatus according to claim 8, wherein the memory device is any one of a phase-change memory device, a resistive memory device, and a magnetoresistive memory device.

13. The memory device of claim 8, wherein two or more of the plurality of memory cells are stacked.

Technical Field

The present disclosure relates to a selection device including a semiconductor layer including a chalcogenide compound between electrodes, and a memory apparatus including the selection device.

Background

In recent years, there is a demand for increasing the capacity of nonvolatile memories for data storage represented by resistance change memories such as ReRAM (resistance random access memory). In contrast, a typical memory device employs a cross-point memory cell array structure in which a plurality of memory cells are arranged on a plane or a stacked memory cell array structure in which a plurality of memory cells are stacked in a direction perpendicular to a plane, thereby achieving an increase in capacity.

The memory cells each typically include two devices, namely a memory device and a select device. In a resistance change memory such as a ReRAM, writing, reading, or erasing of information is performed by changing electrical characteristics (resistance state) of a memory device. The selection devices each selectively perform a write operation or a read operation on memory devices coupled to a particular bit line and a particular word line, and are coupled in series with the memory devices. In the resistance change memory, a relatively large current needs to flow in order to change the resistance state of the memory device, but the magnitude of the current becomes a cause of a decrease in reliability of the memory apparatus. This is because most of the current flowing in the selection device is converted into heat, thereby degrading the cycle characteristics of the selection device.

In contrast, for example, PTL 1 discloses a nonvolatile memory device including an interlayer film provided between memory cells arranged at respective intersections of two types of wirings (a first metal wiring and a third metal wiring) that intersect each other. In the non-volatile memory device, the memory device includes a phase change material and the selection device includes polysilicon. An interlayer film provided between adjacent memory cells is different from an interlayer film provided between memory devices and an interlayer film provided between selection devices, and an interlayer film having a lower thermal conductivity than that of the interlayer film provided between the selection devices is provided between the memory devices, which realizes a memory cell structure in which the temperature of the selection devices is less likely to become high.

CITATION LIST

Patent document

PTL 1: japanese unexamined patent application publication No.2010-040820

Disclosure of Invention

As described above, in a memory device including a plurality of memory cells, improvement in reliability is desired.

It is desirable to provide a selection device that can improve reliability, and a memory apparatus including the selection device.

A selection device according to an embodiment of the present disclosure includes: a second electrode opposed to the first electrode; a semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and a first heat bypass layer provided in at least a part of a periphery of the semiconductor layer between the first electrode and the second electrode and having a higher thermal conductivity than the semiconductor layer.

A memory apparatus according to an embodiment of the present disclosure includes a plurality of memory cells, and each memory cell includes a memory device and a selection device according to the above-described embodiment of the present disclosure coupled to the memory device.

In the selection device according to the embodiment of the present disclosure and the memory apparatus according to the embodiment of the present disclosure, a first heat bypass layer having a higher thermal conductivity than the semiconductor layer is provided in at least a part around the semiconductor layer provided between the first electrode and the second electrode. This alleviates heat generation of the semiconductor layer in the on state.

According to a selection device according to an embodiment of the present disclosure and a memory apparatus according to an embodiment of the present disclosure, a first heat bypass layer is provided in at least a part around a semiconductor layer, the first heat bypass layer having a higher thermal conductivity than the semiconductor layer; therefore, heat generation of the semiconductor layer in the on state is reduced, a safe operation range is expanded, and variation in operation conditions is reduced. This makes it possible to improve the reliability of the selection device and the memory apparatus including the selection device.

It is to be noted that the effect described here is not necessarily restrictive, and may be any effect described in the present disclosure.

Drawings

fig. 1 is a schematic cross-sectional view of the configuration of a selection device according to a first embodiment of the present disclosure.

Fig. 2 is a perspective view of the construction of the OTS layer and the thermal bypass layer of the select device shown in fig. 1.

fig. 3 is a schematic cross-sectional view of a configuration in which a plurality of selection devices shown in fig. 1 are arranged.

Fig. 4 is a schematic diagram of an example of a schematic configuration of a memory cell array of the present disclosure.

Fig. 5 is an electrical schematic diagram of the memory cell array shown in fig. 4.

Fig. 6 is a schematic diagram of the configuration of the memory cell shown in fig. 4.

Fig. 7 is a measurement circuit diagram for evaluating the electrical characteristics of the selection device.

Fig. 8 is a characteristic diagram of a typical selection device.

Fig. 9 is a characteristic diagram showing the dependence of the resistance value of the selected device on the cross-sectional area of the electrode in the off state before molding.

Fig. 10 is a characteristic diagram showing the dependence of the resistance value of the selected device on the cross-sectional area of the electrode in an off state after molding.

Fig. 11 is a characteristic diagram showing a temperature distribution inside a filament (filament).

FIG. 12 is a characteristic diagram of a current density distribution in the filament.

Fig. 13 is a graph showing current-voltage characteristics of a typical selection device.

Fig. 14 is a graph showing current-voltage characteristics of the selection device shown in fig. 1.

Fig. 15 is a characteristic diagram showing the internal resistance of the selection device shown in fig. 1.

Fig. 16 is a schematic cross-sectional view of the configuration of a selection device according to a second embodiment of the present disclosure.

Fig. 17 is a perspective view of the construction of the OTS layer and the thermal bypass layer of the select device according to a third embodiment of the present disclosure.

Fig. 18 is a schematic cross-sectional view of the configuration of a selection device according to a first modification of the present disclosure.

Fig. 19 is a schematic diagram of another example of a schematic configuration of a memory cell array according to a second modification of the present disclosure.

Fig. 20 is a schematic diagram of another example of a schematic configuration of a memory cell array according to a third modification of the present disclosure.

fig. 21 is a detailed schematic cross-sectional view of the memory cell array shown in fig. 20 at one intersection.

Detailed Description

Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following description gives specific examples of the present disclosure, and the present disclosure is not limited to the following embodiments. In addition, the present disclosure is not limited to the positions, sizes, size ratios, and the like of the respective components illustrated in the respective drawings. Note that the description is given in the following order.

1. First embodiment (example of providing a thermal bypass layer around an OTS layer)

1-1, Structure of selection device

1-2, architecture of memory cell array

1-3, action and Effect

2. Second embodiment (example of extending heat bypass layer around upper and lower electrodes)

3. Third embodiment (example in which heat bypass layers are provided on both sides of a semiconductor layer extending in one direction)

4. Variants (other examples of selection devices and memory cell arrays)

<1, first embodiment >

Fig. 1 schematically shows a cross-sectional configuration of a selection device (selection device 10) according to a first embodiment of the present disclosure. For example, the selection device 10 selectively operates an optional memory device (memory device 40) among a plurality of memory devices arranged in a memory cell array (memory cell array 100) having a so-called cross-point array structure shown in fig. 4. The selection device 10 is coupled in series with the memory device 40, and has a configuration in which an OTS (ovonic threshold switching) layer 13 (semiconductor layer) is disposed between a lower electrode 11 (first electrode) and an upper electrode 12 (second electrode) opposed to each other, which will be described later in detail. In the selection device 10 according to the present embodiment, as shown in fig. 2, a thermal bypass layer 14 (first thermal bypass layer) is disposed around the OTS layer 13.

(1-1, Structure of selection device)

The selection device 10 has a resistance (low resistance state; on state) that decreases greatly with an increase in applied voltage, and exhibits a high resistance state (off state) with a low applied voltage. In other words, the selection device 10 has a nonlinear resistance characteristic in which the resistance is high in the case where the applied voltage is low, and the resistance is greatly reduced and a large current (for example, a current larger by several orders of magnitude) flows in the case where the applied voltage is high. In addition, the selection device 10 returns to the high-resistance state in a case where the applied voltage is decreased below a predetermined voltage (threshold voltage) or in a case where the applied voltage is stopped, and does not maintain the on-state (low-resistance state). The selection device 10 corresponds to a specific example of "selection device" of the present disclosure.

The lower electrode 11 includes a wiring material used for a semiconductor process, such as tungsten (W), tungsten nitride (WN), titanium nitride (TiN), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), and silicide. In the case where the lower electrode 11 includes a material such as Cu which can cause ion conduction by an electric field, the surface of the lower electrode 11 may be covered with a material such as W, WN, TiN, and TaN which is unlikely to cause ion conduction and difficult to conduct ions or thermally diffuse.

The upper electrode 12 may use a known semiconductor wiring material similar to the lower electrode 11, but the upper electrode 12 preferably uses a stable material that does not react with the OTS layer 13 even after post annealing.

In the case where a voltage is applied to the selection device 10 (for example, in the case where a voltage pulse is applied to both ends of the device or in the case where a current pulse flowing through the selection device 10 is applied), the OTS layer 13 serves as a current path, and the internal resistance of the OTS layer 13 reversibly changes with temperature. The OTS layer 13 includes, for example, a material (non-linear resistance material) in which the current (I) increases exponentially with an increase in the voltage (V).

In the present embodiment, the OTS layer 13 includes at least one chalcogen element selected from group 16 elements in the periodic table, specifically, tellurium (Te), selenium (Se), and sulfur (S). In addition to the above-described chalcogen elements, the OTS layer 13 includes at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si). In addition, the OTS layer 13 may further include at least one second element selected from oxygen (O) and nitrogen (N).

The OTS layer 13 preferably includes a chalcogenide element, a first element, and a second element, for example, in the following ranges. The chalcogen element is preferably included in a range of 10 atomic% or more and 70 atomic% or less. The first element is preferably included in the range of 5 atomic% or more and 50 atomic% or less. The second element is preferably included in the range of 1 atomic% or more and 40 atomic% or less.

Note that the OTS layer 13 may include elements other than these elements without impairing the effects of the present disclosure.

The heat bypass layer 14 has a higher thermal conductivity than the OTS layer 13 and serves as a heat flow path between the lower electrode 11 and the upper electrode 12 for heat generated in the case where a voltage is applied to the selection device 10. For example, as shown in fig. 2, a thermal bypass layer 14 is disposed around the OTS layer 13. The internal resistance of the thermal bypass layer 14 is preferably sufficiently greater than the internal resistance of the OTS layer 13, and is, for example, desired to have a bandgap of 2eV or greater. This may prevent the thermal bypass layer 14 from acting as a current path.

the thermal bypass layer 14 preferably comprises an alloy including any one of silicon oxide (SiO2) doped with carbon (C) or boron (B) or phosphorus (P), silicon nitride (Si3N4), aluminum oxide (Al2O3), cerium oxide (CeO2), zirconium oxide (ZrO2), silicon carbide (SiC), beryllium oxide (BeO), zinc oxide (ZnO), titanium oxide (TiO2), Boron Arsenide (BAs), antimony boride (BSb), Boron Phosphide (BP), and Boron Nitride (BN). Table 1 summarizes the thermal conductivity of typical materials. These materials are preferably used to form the thermal bypass layer 14.

[ Table 1]

The internal resistance (Rs) of the selection device 10 is represented by, for example, the following equation (1). It is to be noted that the cross-sectional area refers to an area in a plane direction orthogonal to the stacking direction, and the area is applicable to a cross-sectional area which will be described below. In addition, the internal resistance (Rs) of the select device 10 is precisely the parallel combined resistance of the OTS layer 13 and the thermal bypass layer 14, but in the present embodiment, current does not flow through the thermal bypass layer 14, which makes it possible to consider the internal resistance (Rs) of the select device 10 as the internal low voltage (electrical local) of the OTS layer 13.

[ equation 1]

(Rs: internal resistance (Ω), σ OTS: electric conductivity (S/m) of the OTS layer,. kappa.OTS: thermal conductivity (W/(mK)), SOTS: cross-sectional area (cm2), d: film thickness (cm) of the OTS layer.)

The resistance of the entire selection device 10 includes, in addition to the internal resistance (Rs) represented by the above equation (1), schottky contact resistance at the interface between the electrode (lower electrode 11 or upper electrode 12) and the OTS layer 13, and the like. The current (I) flowing through the selection device 10 defined by taking into account the schottky contact resistance and the above-described internal resistance is represented by, for example, the following equation (2).

[ formula 2]

(I: current (A), Richardson constant: A th (A/cm2K2), Schottky barrier height: φ B (eV), elementary charge: e (C), Boltzmann constant: kB (J/K), ideality factor: n, thermal voltage: Vt (kBT/e) (V))

In the selection device 10 according to the present embodiment, in order to concentrate heat flow flowing in a direction toward the lower electrode 11 or a direction toward the upper electrode 12 on the heat bypass layer 14, it is desirable that the heat bypass layer 14 satisfies the following equation (3).

[ formula 3]

κS＞κS·····(3)

(κ bypass: thermal conductivity of thermal bypass layer (W/(mK)), Sbypass: cross-sectional area of thermal bypass layer (cm2), κ ors: thermal conductivity (W/(mK)), sor: cross-sectional area (cm2))

That is, it is desirable that the product of the thermal conductivity (Kbypass) and the cross-sectional area (Sbypass) of the thermal bypass layer 14 is larger than the product of the thermal conductivity (Kots) and the cross-sectional area (Sots) of the OTS layer 13. Note that ideally, it is desirable that all heat flow passes through the heat bypass layer 14, and the thermal resistance (Rh) of the heat bypass layer 14 can be approximated by the following equation (4).

[ formula 4]

In the case where a plurality of selection devices 10 are used side by side as in a memory cell array 100 described later, as shown in fig. 3, an electrothermal insulation layer 15 is preferably provided between adjacent selection devices 10. The electrically heated insulating layer 15 has a lower thermal conductivity than the thermal bypass layer 14. Providing the electrothermal insulating layer 15 having low thermal conductivity between the adjacent selection devices 10 makes it possible to prevent thermal interference between the adjacent selection devices 10. Examples of the material of the electrothermal insulating layer 15 include silicon oxide (SiO2), silicon nitride (Si3N4), and alloys thereof. Alternatively, a material included in the OTS layer 13 may be used.

(1-2, Structure of memory cell array)

Fig. 4 is a perspective view of an example of the configuration of the memory cell array 100. The memory cell array 100 corresponds to a specific example of the "storage device" of the present disclosure. The memory cell array 100 is a memory device having a so-called cross-point array structure in which memory cells 1 are arranged at respective cross points of a plurality of word lines WL extending in one direction (for example, X-axis direction) and a plurality of bit lines BL extending in the other direction (for example, Z-axis direction).

Figure 5 shows an example of electrical coupling of the memory cell array 100. That is, the memory cell array 100 includes memory cells M11, M12, M13, M14, M21, M22, M23, M24, M31, M32, M33, M34, M41, M42, M43, and M44, one of which is arranged at a position corresponding to one of positions (cross points) where the respective word lines WL1 to WL4 and the respective bit lines BL1 to BL4 are opposed to each other.

The memory cells 1(M11, M12, M13, M14, M21, M22, M23, M24, M31, M32, M33, M34, M41, M42, M43, and M44) each include, for example, as shown in fig. 6, a selection device 10 and a memory device 40 coupled in series with each other, and have one end electrically coupled to a bit line BL (for example, on the selection device 10 side) and the other end electrically coupled to a word line WL (for example, on the memory device 40 side). In other words, in the memory cell array 100, the memory device 40 is disposed near the word line WL, and the selection device 10 is disposed near the bit line BL.

It is to be noted that, for example, in the memory cell array 200 as shown in fig. 16, among the selection device 10 and the memory device 40, the selection device 10 may be disposed close to the word line WL, and the memory device 40 may be disposed close to the bit line BL. In addition, in a certain layer in the memory cell array, the memory device 40 may be configured close to the bit line BL and the selection device 10 may be configured close to the word line WL, while in a layer adjacent to the certain layer, the memory device 40 may be configured close to the word line WL and the selection device 10 may be configured close to the bit line BL. Further, in each layer, memory device 40 may be formed on selection device 10, or conversely, selection device 10 may be formed on memory device 40.

As described above, the respective word lines WL (WL1 to WL4) extend in a common direction with each other (in the X-axis direction in fig. 4). As described above, the respective bit lines BL (BL1 to BL4) extend in a direction (in the Z-axis direction in fig. 4) different from the extending direction of the word lines WL (for example, in a direction perpendicular to the extending direction of the word lines WL) and common to each other. Note that the plurality of word lines WL and the plurality of bit lines BL may be configured in a plurality of layers, and may be separately configured in a plurality of layers as shown in fig. 17 and 18, for example.

Each word line WL and each bit line BL are provided on a substrate (not shown), for example. The substrate is provided with, for example, a wiring group electrically coupled to each word line WL and each bit line BL, a circuit for coupling the wiring group and an external circuit to each other, and the like.

the memory device 40 includes, for example, a pair of electrodes opposed to each other and a memory layer disposed between the pair of electrodes. The memory device has a resistance value that is substantially changed by applying a voltage to the memory device 40 (e.g., applying a voltage pulse across the device or applying a current pulse through the memory device 40). The memory device 40 is a so-called nonvolatile memory, and maintains a change in resistance value even if the applied voltage is removed. The storage device 40 corresponds to a specific example of the "storage device" of the present disclosure.

In general, a state in which the resistance value of the memory device is high is referred to as a "reset state" or an "off state", and a state in which the resistance value of the memory device is low is referred to as a "set state" or an "on state". The change from the high-resistance state to the low-resistance state is referred to as "set", the change from the low-resistance state to the high-resistance state is referred to as "reset", and the initial setting is particularly referred to as "molding". The profiling is an electrically operated method which determines the current path with the application of initial and subsequent voltage pulses or initial and subsequent current pulses and is formed autonomously. The molding is also performed in the selection device 10. The autonomously formed current path is often referred to as a "filament". One memory device 40 is capable of storing at least one bit of data by corresponding the off state to a theoretical value of "0" and the on state to a theoretical value of "1".

It is to be noted that the memory device 40 can take any memory form other than the above-described resistance change memory device, including, for example, an OTP (one-time-programmable) memory device, a unipolar phase-change memory device (PCRAM), a magnetoresistive memory device, or the like, which can be rewritten only once using a fuse or an antifuse.

In the memory cell array 100, each of a pair of electrodes (one electrode and the other electrode) of the memory device 40 and a pair of electrodes (the lower electrode 11 and the upper electrode 12) of the selection device 10 may be provided separately from the word line WL and the bit line BL, or the word line WL and the bit line BL may also be used as electrodes. That is, the memory cell 1 in the memory cell array 100 shown in fig. 4 may have a configuration in which one electrode, a memory layer, another electrode, a lower electrode 11, an OTS layer 13 (and a thermal bypass layer 14), and an upper electrode 12 are stacked from the word line WL side to the bit line BL side, or may have a structure in which the memory layer and the OTS layer 13 (and the thermal bypass layer 14) are directly stacked. It is noted that in case the memory cells 1 each comprise a storage layer and an OTS layer 13 (as well as a thermal bypass layer 14), an intermediate electrode is preferably provided between the selection device 10 and the memory device 40 as in the memory cell array 200 shown in fig. 16.

(1-3, action and Effect)

a unit device storing data in a semiconductor memory is referred to as a memory cell. In a typical memory device, a plurality of such memory cells are arranged on a plane (cross-point memory cell array) or vertically stacked with respect to the plane (stacked memory cell array), thereby achieving an increase in capacity. In either case, each of a plurality of memory cells included in the memory cell array is located at a corresponding one of the intersections of two conductors called word lines and bit lines, and the respective locations are specified by applying appropriate signals to the corresponding one of the word lines and the corresponding one of the bit lines. The memory cells each typically include two devices, namely a memory device and a select device. For example, in a NAND flash memory, the storage device includes a floating gate and the selection device includes a field effect transistor. In a resistive random access memory (resistance RAM: ReRAM), the memory device includes a high resistance film, and the selection device includes, for example, an MSM (metal-semiconductor-metal) diode or an MIM (metal-insulator-metal) diode.

Incidentally, in the storage device, in addition to increasing the capacity, high reliability is also desired. In order to ensure long-term reliability of the memory device, it is important for the above reasons that the cumulative power-on time that the selection device included in the memory cell can withstand exceeds the cumulative power-on time of the memory device.

For example, as shown in fig. 7, the electrical characteristics of the selection device (selection device 1100) may be evaluated by a circuit that directly couples the selection device and the field effect transistor (field effect transistor 1200) to each other. The magnitude and duration of the supply voltage Vin applied to the circuit shown in fig. 7 is controlled by an externally coupled DC or AC signal source auto-scanning device. The current value I is monitored by a multimeter or by an accessory function of the signal source autoscan device.

The maximum current (Icomp) flowing through the select device 1100 is controlled by the gate voltage (Vg) of the field effect transistor 1200. If the characteristics of the field-effect transistor 1200 are measured in advance, the voltage (Vds) between the drain electrode and the source electrode is known with the current (I) flowing, which enables the device voltage (Vsel) of the selection device 1100 to be estimated using the following equation (5).

[ formula 5]

V＝V-V·····(5)

Here, Vth represents a threshold voltage when the selection device 1100 changes from the off-state to the on-state, and Ith represents a threshold current. In order to change the state of the nonvolatile memory device, a current of a certain current or more needs to flow, and the sign of the current is similar to the maximum current (Icomp).

In a cross-point memory cell array, the area occupied by one memory cell is limited. Therefore, the approximate value of the current density obtained by dividing the maximum current (Icomp) by the electrode area often exceeds the allowable value of standard semiconductors such as silicon (Si) and germanium (Ge). Therefore, in a selection device such as an MSM diode and an MIM diode (hereinafter referred to as a selection diode device), each of the semiconductor film and the insulating film often includes a so-called OTS material including at least one chalcogen element selected from sulfur (S), selenium (Se), and tellurium (Te). Fig. 8 shows current-voltage characteristics of a selection diode device having a semiconductor film or an insulating film formed using an OTS material (hereinafter referred to as an OTS film). As shown in fig. 8, the selection diode device having the OTS film exhibits a negative differential resistance property. The boundary voltage value at which the sign of the differential resistance changes from positive to negative is the threshold voltage Vth, and the current value thereof is the threshold current Ith. The negative differential resistance property is a characteristic property of the OTS film exhibiting the phase transition, and is also interpreted as a property of an operation (filament formation) of narrowing a flow path (current path) of a current passing through the OTS film.

Although it is difficult to accurately demonstrate the operation of narrowing the current path, the threshold voltage and the leakage current after the molding are often characteristically changed to be different from those before the molding. Note that the leakage current is a current equal to or smaller than a threshold value of a current flowing in a case where the selection diode device is in an off state. Generally, in a select diode device having an OTS film, it is considered that most of the area of the OTS film is occupied by an amorphous phase immediately after film formation. The area occupied by the amorphous phase is superior in nonlinear and electrically insulating properties. Therefore, in the state before the formation, the leakage current flowing through the select diode device is very small.

In contrast, in the selected diode device after molding, in general, the leakage current increases and the threshold voltage decreases. This is considered to be because a part of the amorphous phase included in the OTS film forms crystals during molding, thereby forming a region (filament) having high conductivity. The filament serves as a flow path for electric current flowing through the OTS film, and also serves as a main flow path (heat flow path) for heat flow flowing in the thickness direction of the OTS film.

Fig. 9 and 10 show results of measuring the resistance of the selection device 1100 in the off state before (fig. 9) and after (fig. 10) the forming in the circuit shown in fig. 7. Note that the off-resistance before forming was measured at Vsel 4V, and the off-resistance after forming was measured at Vsel 3V. The horizontal axis of each of the characteristic diagrams shown in fig. 9 and 10 indicates the reciprocal 1/Splug of the sectional area (Splug) of the cathode electrode, and the smaller the sectional area (Splug) of the cathode electrode, the more rightward the sectional area (Splug) of the cathode electrode, the more leftward the sectional area (Splug) of the cathode electrode. The resistance is inversely proportional to the cross-sectional area of the current path. In fig. 9, the resistance value in the off state before molding is plotted on a line rising rightward; therefore, the results in fig. 9 indicate that the cross-sectional area (Splug) of the cathode electrode is proportional to the cross-sectional area of the current path. This means that the leakage current flows relatively uniformly on the cathode electrode. In contrast, in fig. 10, the resistance in the off-state after molding is not always proportional to the cross-sectional area (Splug) of the cathode electrode. This means that a filament having a certain cross-sectional area (current path) was formed in an amorphous phase by molding, and this proved that an operation of narrowing the current path (filament formation) occurred. The leakage current flows unevenly in the amorphous phase, specifically, the leakage current is concentrated in the filament; therefore, the correlation between the resistance value in the off state and the cross-sectional area (Splug) of the cathode electrode is reduced.

In a memory device having a nonvolatile property such as a ReRAM, a filament formed by molding can be easily observed. This is because irreversible changes in the crystal structure inside the memory device are involved, thus causing traces of the filament to remain in a portion of the ReRAM material included in the memory layer, which makes it possible to confirm the filament by, for example, SEM images or X-ray absorption spectroscopy. In contrast, it is difficult to directly observe the filament formed in the select diode device even using SEM images, X-ray absorption spectra, electron microscopes, or the like, and the presence of the filament is confirmed only indirectly as shown in fig. 9 and 10 described above. This is because the selection diode is formed using a phase change material having volatility, such as an OTS material. In the selective diode, the change in crystal structure caused by the formation is not permanent, and the change in crystal structure is considered to gradually return from an easily-observed crystal structure having a low electrical insulating property to a crystal structure which is not completely amorphous but is difficult to observe having a high electrical insulating property.

incidentally, from Boeer's theory that clarifies the relationship between the negative differential resistance and the filament by a mathematical method, it is apparent from the current-voltage characteristics shown in fig. 8 that the local increases in temperature and current density are the cause of the formation of the negative differential resistance and the filament. Fig. 11 and 12 show the temperature distribution (fig. 11) and current density distribution (fig. 12) inside a selected diode device calculated based on Boeer's theory of joule heating, where s is normalized power, R/R is normalized radial coordinate, (T-TR)/Θ is normalized temperature, and j/jn is normalized current density. As described above, the filament serves as a current path flowing through the inside of the selection diode device in the film thickness direction of the OTS film, and as a heat flow path. Thus, the cross-sectional area of the filament is the cross-sectional area of the current path and the cross-sectional area of the heat flow path, and each cross-sectional area can be approximated by a rhhm 2, where rhhm is the half-width at half-maximum of each distribution. As can be seen from fig. 11 and 12, as the electric power input to the selection diode device increases, the temperature and the current density of the central portion of the selection diode device increase toward infinity. This phenomenon is generally known as "thermal breakdown" and is a phenomenon that inevitably occurs in materials whose electrical conductivity exponentially increases with respect to temperature, such as semiconductors and insulators. In the selective diode device, a material whose crystal structure performs reversible phase change to some extent is used, and even if the inside of the selective diode device is at an ultra-high temperature, a relatively long-term resistance to degradation in cycle characteristics can be achieved. Therefore, in the select diode device, a chalcogenide element such as sulfur (S), selenium (Se), or tellurium (Te) is used instead of a standard crystalline semiconductor such as silicon (Si) or germanium (Ge).

Fig. 13 shows the current-voltage characteristics of a typical selection diode device having an OTS film in an amorphous state between a pair of electrodes opposed to each other. Fig. 13 additionally shows four curves, each indicating the temperature inside the select diode device estimated from the product of the current and the voltage indicative of the negative differential resistance. The four curves correspond to isothermal curves in the case where the highest temperatures (T (r ═ 0)) of the diode devices were selected to be 100 ℃, 200 ℃, 400 ℃, and 1000 ℃. Generally, a temperature of about 400 ℃ is considered the upper limit of the practical safe operating range for OTS materials. The small thermal conductivity of OTS materials is believed to be a significant cause of the occurrence of cycle degradation of the diodes of the select devices, and as can be seen from Boeer's theory, an increase in temperature in the joule heated region tends to increase the crystallization and melting temperatures of OTS materials.

As described above, in order to ensure long-term reliability of the memory device, it is necessary to select the accumulated power-on time that the diode device can withstand to exceed the accumulated power-on time of the memory device, which however proves to be difficult to achieve from the viewpoint of joule heat. Furthermore, the maximum current used in a non-volatile memory device is outside the safe operating range of the select device diode, which is the reason for the rate limitation on the long-term reliability of the memory device. Further, in the configuration of the typical selection diode device described above, it is difficult to control the shape of the filament, and variations in threshold voltage and threshold current among the plurality of selection diode devices are increased. This limits the array size of the memory cell array.

In contrast, in the selection device 10 according to the present embodiment, the heat bypass layer 14 having a thermal conductivity higher than that of the OTS layer 13 is provided around the OTS layer 13 between the lower electrode 11 and the upper electrode 12 opposed to each other.

Fig. 14 shows current-voltage characteristics of an example formed using the following method as an example of the selection device 10 according to the present embodiment.

(examples)

First, the cathode electrode (lower electrode 11) including the elemental composition of TiN was cleaned by reverse sputtering. Next, the OTS layer 13 including B40C13Te17-N30 (atomic%), for example, having a thickness of 30nm was formed on TiN by reactive sputtering while flowing nitrogen gas into the film formation chamber. Subsequently, after etching the OTS layer 13 side to have a diameter of 60nm, a thermal bypass layer 14 including BAs is formed around the OTS layer 13, the thermal bypass layer 14 having an inner diameter of 60nm, an outer diameter of 100nm and a thickness of 30 nm. Finally, an anode (upper electrode 12) including a W film is formed. The final device size is 100nm phi. Note that, in this example, the thermal resistance value is adjusted so that the threshold current does not greatly differ from the threshold current of the typical selection device (selection diode device) used in the current-voltage characteristic diagram shown in fig. 13.

As in fig. 13, fig. 14 additionally shows four curves, each indicating the temperature inside the selection device estimated from the product of the current and the voltage indicating the negative differential resistance. The four curves correspond to isothermal curves in the case where the maximum temperatures (T (r ═ 0)) of the device 10 are selected to be 100 ℃, 200 ℃, 400 ℃, and 1000 ℃. The thermal resistance Rh of the thermal bypass layer 14 provided around the OTS layer 13 has an effect on both the threshold voltage Vth and the threshold current Ith of the select device.

Compared with the typical selection diode device shown in fig. 13, the selection device 10 according to the present embodiment has a large ratio (Rs/Rh) of internal thermal resistance (Rs) to thermal resistance (Rh), which consequently increases the threshold voltage. This is believed to be because the thermal resistance of the metal-semiconductor interface (the interface between the lower electrode 11 and the OTS layer 13 and between the upper electrode 12 and the OTS layer 13) is improved by shunting the heat flow to the thermal bypass layer 14. In particular, it is believed that the barrier height and ideality factor, which determine the value of the schottky contact resistance, can withstand high temperatures during operation of the selector, which makes it possible to maintain these values before and after molding. As a result, although not shown here, the variations in the threshold voltage Vth and the threshold current Ith are each reduced by 20% or more. That is, controlling the thermal resistance Rh to match the value of the internal resistance Rs makes it possible to greatly reduce variations in the threshold voltage Vth and the threshold current Ith of the selection device 10.

Furthermore, in FIG. 14, the isothermal curves at 100 deg.C, 200 deg.C, 400 deg.C, and 1000 deg.C are shifted toward larger current-voltage products. This indicates that providing the thermal bypass layer 14 causes the thermal resistance (Rh) of the select device 10 to decrease. That is, it can be seen that in the selection device 10, heat generation in the OTS layer 13 in the on state is reduced by the OTS layer 13 becoming a current path and the heat bypass layer 14 becoming a heat flow path, and the actual safe operating range of the OTS layer 13 (for example, the range occupied by the isothermal curve at 400 ℃) is expanded. Further, the selection device 10 can have a margin of maximum current of 100 μ a or more while maintaining the cycle characteristics of 10E7 or more cycles.

Fig. 15 shows the temperature characteristics of the internal resistance Rs in the selection device 10 after the molding, and shows the internal resistance Rs of the selection device 10 obtained from the current-voltage characteristics shown in fig. 14. The internal resistance Rs is expressed in terms of the device temperature T. The OTS layer 13 according to the present embodiment undergoes a phase transition at a specific phase transition temperature (Tt 1 and Tt2 in fig. 15) while maintaining a solid phase. Here, a crystal phase which becomes stable at a temperature exceeding Tt1 is referred to as a high-temperature stable phase, and a crystal phase which becomes stable at a temperature of Tt2 or less is referred to as a low-temperature stable phase. Phase transition between solid phases is a phenomenon different from solid-liquid phase transition (liquid-solid transition) used by, for example, a phase change memory including germanium (Ge), antimony (Sb), and tellurium (Te), and is called polycrystalline transition (polycrystallization). In the OTS layer 13, the internal resistance is large in the case where the temperature is low (in the low-temperature stable phase or the normal-temperature stable phase), and the internal resistance is small in the case where the temperature is high (in the normal-temperature stable phase or the high-temperature stable phase). The discontinuity in internal resistance is manifested as a polycrystalline transition temperature. In the case where the selection device 10 including the OTS layer 13 containing boron (B) and carbon (C) as described above is driven, switching between the on state and the off state of the selection device 10 is determined by, for example, whether the operating temperature is equal to or higher than Tt2 or equal to or lower than Tt 2.

Assuming that the electrode applied to the selection device 10 is I × vsel (w), the operating temperature of the selection device 10 is approximately expressed by the following equation (6). In order to prevent the crystal structure of the selective device 10 from being broken, it is desirable to limit the operating temperature to not more than the polymorphic transition temperature Tt1, for example.

[ formula 6]

T＝T+RIV·····(6)

Qualitative expressions of the threshold voltage Vth and the threshold current Ith are approximated using the above-described equations (1) to (6), and thus the qualitative expressions are expressed by the following equations (7) and (8), respectively. As can be seen from equation (7), the threshold voltage Vth is proportional to the ratio (Rs/Rh) of the internal resistance (Rs) and the thermal resistance (Rh). In addition, as can be seen from equation (8), the threshold current Ith is inversely proportional to the thermal resistance (Rh). It should be noted that equations (7) and (8) include many omissions in the derivation process and are therefore not mathematically exact expressions. Further, χ is a parameter representing the effect of thermionic emission, and is defined by the following equation (9).

[ formula 7]

Further, it can be seen that in order to reduce the variation in the threshold voltage, it is sufficient to control Rs/Rh to a fixed value. In order to reduce the variation in the threshold current, the thermal resistance Rh needs to be controlled to a fixed value. The above equation (1) shows that Rs is inversely proportional to the cross-sectional area of the current path. In addition, equation (4) shows that the value of the thermal resistance Rh is inversely proportional to the cross-sectional area of the heat flow path. In the selection device 10 according to the present embodiment, almost the entire OTS layer 13 is used as a current path. This is because the shaping causes the amorphous structure to change to a polycrystalline crystalline structure identified by a low temperature stable phase or an ordinary temperature stable phase, which causes the OTS layer 13 to act as a permanent and stable filament. In addition, the entire thermal bypass layer 14 serves as a thermal flow path. That is, the cross-sectional area of the current path is determined by the inner diameter of the heat bypass layer, and the cross-sectional area of the heat flow path is determined by the difference between the outer diameter and the inner diameter of the heat bypass layer.

Note that the characteristics shown in fig. 15 can also be confirmed in a typical selective diode device using boron (B) and carbon (C) as materials of the OTS layer. However, in a typical select diode device, the characteristics of the select diode device degrade in a short time due to degradation of the OTS layer.

As described above, in the selection device 10 according to the present embodiment, the thermal bypass layer 14 is provided around the OTS layer 13, which causes heat generated in the on state to selectively flow through the thermal bypass layer 14 and causes the temperature rising in the OTS layer 13 to decrease. As a result, the safe operation range of the selection device 10 is expanded, and variations in the threshold voltage Vth and the threshold current Ith are reduced. This makes it possible to improve the reliability of the selection device 10 and the memory cell array 100 including the selection device 10.

in addition, in the present embodiment, in the case where a plurality of selection devices 10 are used as in the memory cell array 100 shown in fig. 10, the electrothermal insulating layer 15 is provided between the adjacent selection devices 10. This makes it possible to prevent thermal interference between adjacent selection devices 10 and to further improve the reliability of the memory cell array 100.

Next, second and third embodiments and modifications of the present disclosure will be described. Hereinafter, components similar to those of the first embodiment are denoted by the same reference numerals, and descriptions thereof are appropriately omitted.

<2, second embodiment >

Fig. 16 shows a cross-sectional configuration of a selection device (selection device 20) according to a second embodiment of the present disclosure. As in the selection device 10 in the first embodiment described above, the selection device 20 selectively operates, for example, an optional memory device (memory device 40) among a plurality of memory devices arranged in a memory cell array having a cross-point array structure (for example, the memory cell array 100). The selection device 20 is coupled in series with the memory device 40 and the OTS layer 13 is arranged between the lower electrode 11 and the upper electrode 12 opposite to each other. The present embodiment differs from the first embodiment in that the thermal bypass layer 24 is continuously disposed around the lower electrode 11, the upper electrode 12, and the OTS layer 13.

As shown in fig. 16, in the present embodiment, the thermal bypass layer 24 provided around the OTS layer 13 extends to the lower electrode 11 and the upper electrode 12, thereby reducing the thermal contact resistance between the lower electrode 11 and the thermal bypass layer 24 and between the upper electrode 12 and the thermal bypass layer 24. This makes it possible to further expand the secure operating range of the selection device 20 and the memory cell array (e.g., the memory cell array 100) including the selection device 20.

<3, third embodiment >

Fig. 17 is a perspective view of the OTS layer 33 and the thermal bypass layer 34 included in the selection device (selection device 30) according to the third embodiment of the present disclosure. As in the selection device 10 in the first embodiment described above, the selection device 30 selectively operates, for example, an optional memory device (memory device 40) among a plurality of memory devices arranged in a memory cell array having a cross-point array structure (for example, the memory cell array 100). The selection device 30 is coupled in series with the memory device 40 and the OTS layer 33 is arranged between the lower electrode 11 and the upper electrode 12 opposite to each other. The present embodiment differs from the first and second embodiments in that the OTS layer 33 extends in one direction (e.g., in the direction of the word line WL or the direction of the bit line BL), and the thermal bypass layer 34 is provided on both sides of the extended OTS layer 33.

As shown in fig. 17, in the present embodiment, the OTS layer 33 and the thermal bypass layer 34 extend, for example, in the direction of the word line WL or the direction of the bit line BL. In this configuration, for example, in the case where the OTS layer 33 and the thermal bypass layer 34 extend in the direction of the word line WL, the effect of the thermal bypass layer 34 in the direction of the bit line BL is limited, but a thermal bypass layer suitable for a stacked memory cell array (memory cell array 300, see fig. 20) described later is realized.

In the selection device 30 according to the present embodiment, the above equations (1), (3), and (4) can be converted into equivalent expressions (resistance per unit length and thermal resistance per unit length) substituted by the widths WOTS and Wbypass of the OTS layer 33 and the thermal bypass layer 34 instead of the cross-sectional areas SOTS and Sbypass. In addition, in the present embodiment, the heat bypass layer 34 also serves as the electrothermal insulation layer 15 described above, which makes it possible to omit the electrothermal insulation layer 15. This makes it possible to reduce the cell size of the memory cell (e.g., memory cell 4).

<4, modification >

(modification 1)

Fig. 18 schematically shows a cross-sectional configuration of a selection device (selection device 60) according to a modification of the present disclosure. As in the selection device 10 in the first embodiment described above, the selection device 60 selectively operates, for example, an optional memory device (memory device 40) among a plurality of memory devices arranged in a memory cell array having a cross-point array structure (for example, the memory cell array 100). As in the selection device 10, the selection device 60 according to the present modification includes the thermal bypass layer 64A around the OTS layer 13 disposed between the lower electrode 11 and the upper electrode 12 opposed to each other, and includes the thermal bypass layer 64B (second thermal bypass layer) inside the OTS layer 13 (for example, in the central portion of the OTS layer 13).

Both the thermal bypass layer 64A and the thermal bypass layer 64B have characteristics similar to those of the thermal bypass layer 14, and are preferably formed using the materials described in the first embodiment. In addition, the thermal bypass layer 64A and the thermal bypass layer 64B may be formed using the same material or may be formed using different materials.

As described above, forming the OTS layer 13 into an annular shape and providing the heat bypass layer 64B in the central portion of the annular shape makes it possible to achieve a more uniform temperature distribution inside the OTS layer 13. This makes it possible to further stabilize the size of the current path formed in the OTS layer 13.

In the case where the selection device 60 according to the present modification corresponds to the above equation (3) or the like, the cross-sectional area (Sbypass) of the thermal bypass layer is the sum of the thermal bypass layer 64A provided around the OTS layer 13 and the thermal bypass layer 64B provided in the central portion. In addition, the configuration of the present modification is applicable not only to the selection device of a cylindrical shape but also to the selection device 30 described in the third embodiment in which, for example, the OTS layer 33 extends in one direction. Specifically, as in the thermal bypass layer 64B in the present modification, for example, the thermal bypass layer is formed in the central portion of the OTS layer so as to extend in the same direction as the OTS layer 33. Therefore, effects similar to those of the present modification can be achieved.

(modification 2)

fig. 19 is a perspective view of the configuration of a memory cell array 200 according to a modification of the present disclosure. As with memory cell array 100, memory cell array 200 is a cross-point memory cell array. In the memory cell array 200 according to the present modification, the selection devices 10 extend along the respective word lines WL extending in a common direction to each other. The memory devices 40 extend along bit lines BL extending in a direction different from the extending direction of the word lines WL (for example, in a direction perpendicular to the extending direction of the word lines WL). In addition, the selection device 10 and the memory device 40 are stacked at each intersection of the plurality of word lines WL and the plurality of bit lines BL while interposing the intermediate electrode 50 between the selection device 10 and the memory device 40.

As described above, in the case where the memory cell 1 includes the storage layer and the OTS layer 13 (and the thermal bypass layer 14), as in the present modification, the intermediate electrode 50 is preferably provided between the memory device 40 (storage layer) and the selection device 10(OTS layer and thermal bypass layer 14).

As described above, in the case where the memory cell 1 includes the memory layer and the OTS layer 13 (and the thermal bypass layer 14), the intermediate electrode 50 also serves as one of a pair of electrodes between which the memory layer is interposed and one electrode (here, the upper electrode 12) of the selection device 10. For example, the intermediate electrode 50 preferably includes a material that prevents the chalcogen element included in the OTS layer 13 and the memory layer from diffusing due to the application of an electric field. This is because, for example, the memory layer includes a transition metal element as an element which performs a memory operation and maintains a written state, but in the case where the transition metal element diffuses into the OTS layer 13 due to an applied electric field, switching characteristics may be degraded. Therefore, the intermediate electrode 50 preferably includes a barrier material having barrier properties against diffusion and ion conduction of the transition metal element. Examples of barrier materials include tungsten (W), tungsten nitride (WN), titanium nitride (TiN), carbon (C), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), titanium Tungsten (TiW), and silicide.

as described above, the selection device 10 and the memory device 40 are provided not only at the intersections but also to extend along the word lines WL and the bit lines BL, respectively, which makes it possible to form the OTS layer 13 or the memory layer simultaneously with the layer becoming the bit lines BL or the word lines WL, for example, and to perform the shape processing together by the photolithography process. This makes it possible to reduce the number of processes.

(modification 3)

Fig. 20 is a perspective view of an example of the configuration of a memory cell array 300 having a three-dimensional structure according to a modification of the present disclosure. Fig. 21 shows a detailed cross-sectional configuration in the Y-axis direction at one intersection of the memory cell array 300. The respective word lines WL extend in a common direction with each other (in the X-axis direction in fig. 20). The respective bit lines BL extend in a direction different from the extending direction of the word lines WL (for example, in a direction perpendicular to the extending direction of the word lines WL (in the Z-axis direction in fig. 20)) and common to each other. In the memory cell array 300 having a three-dimensional structure, word lines WL and bit lines BL are alternately stacked in the Y-axis direction (in the order of word lines WL, bit lines BL, and word lines WL in fig. 20), and memory cells 1 are formed at respective positions between the stacked word lines WL and bit lines BL. That is, the memory cell array 300 according to the present modification is a cross-point memory cell array, and is a stacked memory cell in which a plurality of memory cells 1 are stacked in the Y-axis direction.

In the present modification, the selection device 10 is provided along the word line WL and the bit line BL above each word line WL and each bit line BL. Memory devices 40 are disposed along the word lines WL and the bit lines BL below the respective word lines WL and the respective bit lines BL. As a result, the selection device 10 and the memory device 40 are stacked at the intersection of the word line WL and the bit line BL to form the memory cell 1. In the present modification, each of the intermediate electrodes 50 provided between the word line WL and the memory device 40, between the bit line BL and the memory device 40, and between the selection device 10 and the memory device 40 also serves as a corresponding one of the lower electrode 11 and the upper electrode 12 of the selection device 10 and a pair of electrodes of the memory device 40. That is, the OTS layer 13 and the memory layer 41 are stacked at the intersections of the word lines WL and the bit lines BL while interposing the intermediate electrode 50 between the OTS layer 13 and the memory layer 41. The memory layer 41 includes, for example, an ion source layer 42 and a resistance change layer 43. The resistance variable layer 43 is disposed on the intermediate electrode 50 side.

The ion source layer 42 includes a movable element that forms a conduction path in the resistance change layer 43 by applying an electric field. Examples of the movable element include a transition metal element (in groups 4 to 6 of the periodic table) and a chalcogen element, and the ion source layer 42 includes one or two or more of these elements. In addition, the ion source layer 42 preferably includes oxygen (O), nitrogen (N), and elements other than the above elements. Examples of the elements other than the above include Al, Cu, zirconium (Zr), and hafnium (Hf). In addition to the above elements, the ion source layer 42 may include, for example, manganese (Mn), cobalt (Co), iron (Fe), nickel (Ni), platinum (Pt), Si, or the like.

The resistance change layer 43 includes, for example, an oxide or a nitride of a metal element or a non-metal element, and has a resistance value that changes when a predetermined voltage is applied between a pair of electrodes of the memory device 40.

In the memory cell array 300, corresponding sockets (a BL socket 311 and a WL socket 312) are provided in respective layers of the stacked word lines WL and bit lines BL. The BL socket 311 and the WL socket 312 are coupled to a memory cell selection circuit and a read/write interface circuit (not shown), for example, on the periphery of the memory cell array 300.

It is to be noted that modifications 2 and 3 describe an example in which the selection device 10 described in the first embodiment is used as a selection device, but the selection device 20, 30, or 60 described in the second and third embodiments or modification 1 may be used.

Although the present disclosure has been described with reference to the first to third embodiments and the modifications, the contents of the present disclosure are not limited to the above-described embodiments and the like, and may be modified in various ways. It should be noted that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than those described herein.

It should be noted that the present disclosure may have the following configuration.

(1)

A selection device, comprising:

A first electrode;

A second electrode opposed to the first electrode;

A semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and

A first heat bypass layer provided in at least a part of a periphery of the semiconductor layer between the first electrode and the second electrode and having a higher thermal conductivity than the semiconductor layer.

(2)

The selection device according to (1), wherein the semiconductor layer further includes at least one second element selected from oxygen (O) and nitrogen (N).

(3)

The selection device according to (1) or (2), wherein the first thermal bypass layer extends to a side of the first electrode and the second electrode.

(4)

The selection device according to any one of (1) to (4), wherein the first thermal bypass layer includes an alloy including any one of silicon oxide (SiO2) or silicon nitride (Si3N4) doped with carbon (C), boron (B), or phosphorus (P), aluminum oxide (Al2O3), cerium oxide (CeO2), zirconium oxide (ZrO2), silicon carbide (SiC), beryllium oxide (BeO), zinc oxide (ZnO), titanium oxide (TiO2), Boron Arsenide (BAs), antimony boride (BSb), Boron Phosphide (BP), and Boron Nitride (BN).

(5)

The selection device according to any one of (1) to (4), wherein a product of a thermal conductivity and a cross-sectional area of the first heat bypass layer is larger than a product of a thermal conductivity and a cross-sectional area of the semiconductor layer.

(6)

The selection device according to any one of (1) to (5), wherein the semiconductor layer has an annular shape and the second heat bypass layer is provided at a central portion of the annular shape.

(7)

The selection device according to any one of (1) to (6), wherein the semiconductor layer is changed to the low-resistance state by setting an application voltage to a predetermined threshold voltage or more and the semiconductor layer is changed to the high-resistance state by reducing the application voltage to be lower than the predetermined threshold voltage without a phase change between the amorphous phase and the crystalline phase.

(8)

A memory device is provided with a plurality of memory cells, each of the plurality of memory cells including a memory device and a selection device coupled to the memory device,

The selection device includes:

A first electrode;

A second electrode opposed to the first electrode;

A semiconductor layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and

A first heat bypass layer provided in at least a part of a periphery of the semiconductor layer between the first electrode and the second electrode and having a higher thermal conductivity than the semiconductor layer.

(9)

The memory device according to (8), wherein an electrothermal insulating layer is provided between adjacent selection devices.

(10)

The memory device according to (9), wherein an electrothermal insulating layer is provided between adjacent plural memory cells.

(11)

the memory device according to (9) or (10), wherein the electrothermal insulating layer comprises an alloy including a material included in the semiconductor layer, silicon oxide (SiO2), or silicon nitride (Si3N 4).

(12)

The memory apparatus according to any one of (8) to (11), wherein the memory device is any one of a phase-change memory device, a resistance-change memory device, and a magnetoresistive memory device.

(13)

The storage device according to any one of (8) to (12), wherein two or more of the plurality of memory cells are stacked.

This application claims priority to japanese prior patent application JP2017-091113, filed on day 5/1 of 2017 to the present patent office, the entire contents of which are incorporated herein by reference.

It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors within the scope of the appended claims or their equivalents.