阅读说明：本技术 一种dc综合时序优化方法、装置、设备及存储介质 (DC comprehensive time sequence optimization method, device, equipment and storage medium ) 是由 庄戌堃 于 2021-06-20 设计创作，主要内容包括：本发明公开了一种DC综合时序优化方法、装置、设备及存储介质。所述方法包括：初始化DC综合参数和时序分析参数；执行DC综合操作以生成综合结果及综合报告；响应于执行完DC综合操作,则基于所述综合报告、以及所述时序分析参数以确定是否存在重大时序违反；响应于存在重大时序违反,则基于预设调整规则对DC综合进行参数调整并重新执行DC综合操作,其中,所述预设调整规则为基于多个预设调整项目的预设优先级排序每次调整优先级最高的预设调整项目；响应于不存在重大时序违反,则输出本次DC综合操作对应的综合结果。本发明的方案实现DC综合时自动时序优化,无需工程师干预或者人工调整,能够自动输出最优结果,极大节省了时间,提高工作效率。(The invention discloses a DC comprehensive time sequence optimization method, a device, equipment and a storage medium. The method comprises the following steps: initializing DC comprehensive parameters and time sequence analysis parameters; performing a DC synthesis operation to generate a synthesis result and a synthesis report; in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters; in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items; and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists. The scheme of the invention realizes automatic time sequence optimization during DC synthesis, does not need intervention of engineers or manual adjustment, can automatically output the optimal result, greatly saves time and improves working efficiency.)

1. A method for DC integrated timing optimization, the method comprising:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists.

2. The method of claim 1, wherein the step of initializing DC synthesis parameters and timing analysis parameters comprises:

initializing DC comprehensive parameters, wherein the initializing DC comprehensive parameters comprise initializing library file selection, clock setting, resetting setting, input and output delay, comprehensive area, input and output load, line load model, maximum conversion time, maximum fan-out number and key path grouping, and the clock setting comprises clock period, clock duty ratio, clock jitter and multi-clock period;

initializing timing analysis parameters includes initializing clock cycles.

3. The method of claim 2, wherein the step of determining whether a significant timing violation exists based on the consolidated report and the timing analysis parameters in response to performing a DC consolidation operation comprises:

fifteen percent of the clock period is calculated as a comparison value,

reading the slack value of the Violated option from the comprehensive report by utilizing a report timing command and judging whether the slack value is a negative number or not;

in response to the slack value being negative, comparing the absolute value of the slack value to the comparison value;

in response to the absolute value of the slack value being greater than the comparison value, confirming that there is a significant timing violation of the DC synthesis operation;

in response to the absolute value of the slack value being less than or equal to the comparison value, confirming that the DC synthesis operation is free of significant timing violations.

4. The method of claim 1, wherein the plurality of preset adjustment items comprise adjusting a DC synthesis compile option, modifying an input-output delay item, and modifying an input-output driving capability item, wherein the modifying an input-output driving capability item comprises modifying an input-output load and modifying a maximum fan-out number.

5. The method of claim 4, wherein the predetermined priority order is sequentially from high to low for adjusting the DC synthesis compile option, modifying the I/O delay term, and modifying the I/O driving capability term.

6. The DC synthesis timing optimization method according to claim 4, wherein the DC synthesis coding options include three coding modes of low, medium and high.

7. The method of claim 4, wherein the input-output delay in the modified input-output delay term is in a range of 30% to 50% of a clock cycle.

8. An apparatus for DC integrated timing optimization, the apparatus comprising:

the initialization module is used for initializing DC comprehensive parameters and time sequence analysis parameters;

the comprehensive module is used for executing DC comprehensive operation to generate a comprehensive result and a comprehensive report when the DC comprehensive completion parameter is initialized;

a timing analysis module for determining whether a significant timing violation exists based on the consolidated report and the timing analysis parameters when the DC consolidation operation is performed;

the parameter adjusting module is used for carrying out parameter adjustment on the DC synthesis based on a preset adjusting rule and re-executing the DC synthesis operation when the major time sequence violation exists, wherein the preset adjusting rule is a preset adjusting item which is sorted based on the preset priority of a plurality of preset adjusting items and has the highest adjusting priority each time;

and the output module is used for outputting a comprehensive result corresponding to the DC comprehensive operation when no major time sequence violation exists.

9. A computer device, comprising:

at least one processor; and

a memory storing a computer program executable in the processor, the processor executing the program to perform the DC synthetic timing optimization method of any one of claims 1 to 7.

10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, performs the DC synthetic timing optimization method of any one of claims 1 to 7.

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a DC comprehensive timing optimization method, apparatus, device, and storage medium.

Background

With the development of science and technology, more and more stringent requirements are put forward on the functionality, stability and the like of the chip, so that the chip is larger and larger in scale and more complex in logic. Meanwhile, due to market competition, the time requirement for the whole chip design is shorter and shorter. In the chip Design process, a Design company (Synopsys company, circuit synthesis tool) is used to convert an RTL (Register Transfer Level) code designed by a front-end engineer into a gate-Level netlist, and the gate-Level netlist is handed to a back-end engineer for back-end Design, which is a ring starting from the top in the chip Design. If the DC synthesis has a problem, the RTL cannot be converted into a correct gate-level netlist, and a correct back-end design cannot be performed, which directly results in chip-on-chip failure. Therefore, the DC synthesis often needs to be repeatedly modified by an engineer to optimize the area, power consumption, time sequence and the like, and especially for large-scale and ultra-large-scale logic design, a large amount of time is consumed in the DC synthesis optimization, so that the automatic optimization of the DC synthesis is very necessary.

The conventional DC integration process includes the following steps: firstly, an engineer designs a constraint file according to RTL codes designed by front-end designers to perform DC synthesis to generate a gate-level netlist, then checks a synthesis result according to a report generated at the same time, checks whether the time sequence is violated, and if so, the engineer needs to analyze problems, modify constraints and perform DC synthesis again according to the report. However, with the higher requirements on the performance of the chip, the chip design has very large and complex logic and algorithm, when the logic is larger and the algorithm is more complex, the larger the code amount of the RTL is, the more time is required for the corresponding DC to convert the RTL into a gate-level netlist, after the DC completes one-time synthesis, if there are problems such as timing violation and the like, an engineer is required to modify the constraints for re-synthesis, and repeating the constraint modification for synthesis wastes a lot of time, thereby reducing the efficiency.

Disclosure of Invention

In view of the above, it is necessary to provide a DC comprehensive timing optimization method, apparatus, device and storage medium for solving the problems of manpower consumption and low efficiency of the conventional manual DC comprehensive optimization.

According to a first aspect of the present invention, there is provided a DC integrated timing optimization method, the method comprising:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists.

In some embodiments, the step of initializing DC synthesis parameters and timing analysis parameters comprises:

initializing DC comprehensive parameters, wherein the initializing DC comprehensive parameters comprise initializing library file selection, clock setting, resetting setting, input and output delay, comprehensive area, input and output load, line load model, maximum conversion time, maximum fan-out number and key path grouping, and the clock setting comprises clock period, clock duty ratio, clock jitter and multi-clock period;

initializing timing analysis parameters includes initializing clock cycles.

In some embodiments, the step of determining whether there is a significant timing violation based on the consolidated report and the timing analysis parameters in response to performing a DC consolidation operation comprises:

fifteen percent of the clock period is calculated as a comparison value,

reading the slack value of the Violated option from the comprehensive report by utilizing a report timing command and judging whether the slack value is a negative number or not;

in response to the slack value being negative, comparing the absolute value of the slack value to the comparison value;

in response to the absolute value of the slack value being greater than the comparison value, confirming that there is a significant timing violation of the DC synthesis operation;

in response to the absolute value of the slack value being less than or equal to the comparison value, confirming that the DC synthesis operation is free of significant timing violations.

In some embodiments, the plurality of preset adjustment items include adjusting a DC synthesis compile option, modifying an input output delay item, and modifying an input output drive capability item, wherein the modifying the input output drive capability item includes modifying an input output load and modifying a maximum fan-out number.

In some embodiments, the preset priority order is that priorities of adjusting the DC synthesis compiling option, modifying the input and output delay items, and modifying the input and output driving capability items are sequentially changed from high to low.

In some embodiments, the DC synthesis compilation option includes three compilation modes, low, medium, and high.

In some embodiments, the input-output delay in the modified input-output delay item ranges from 30% to 50% of the clock period.

According to a second aspect of the present invention, there is provided a DC integrated timing optimization apparatus, the apparatus comprising:

the initialization module is used for initializing DC comprehensive parameters and time sequence analysis parameters;

the comprehensive module is used for executing DC comprehensive operation to generate a comprehensive result and a comprehensive report when the DC comprehensive completion parameter is initialized;

a timing analysis module for determining whether a significant timing violation exists based on the consolidated report and the timing analysis parameters when the DC consolidation operation is performed;

the parameter adjusting module is used for carrying out parameter adjustment on the DC synthesis based on a preset adjusting rule and re-executing the DC synthesis operation when the major time sequence violation exists, wherein the preset adjusting rule is a preset adjusting item which is sorted based on the preset priority of a plurality of preset adjusting items and has the highest adjusting priority each time;

and the output module is used for outputting a comprehensive result corresponding to the DC comprehensive operation when no major time sequence violation exists.

According to a third aspect of the present invention, there is also provided a computer apparatus comprising:

at least one processor; and

a memory storing a computer program operable on a processor, the processor executing the program to perform the aforementioned DC integrated timing optimization method, the method comprising the steps of:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists.

According to a fourth aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, performs the aforementioned DC integrated timing optimization method, the method comprising the steps of:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists.

According to the DC comprehensive time sequence optimization method, whether major time sequence violation exists is determined through the comprehensive report and the time sequence analysis parameters, parameter adjustment is carried out on the DC comprehensive on the basis of the preset adjustment rule for the condition that the major time sequence violation exists, the DC comprehensive operation is executed again, the comprehensive result is output until the major time sequence violation does not occur after the comprehensive operation, automatic time sequence optimization during the DC comprehensive is achieved, engineer intervention or manual adjustment is not needed during the operation of a system, the optimal result can be output automatically, time is saved greatly, and the working efficiency is improved.

In addition, the invention also provides a DC comprehensive time sequence optimization device, a computer device and a computer readable storage medium, which can also realize the technical effects and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic flow chart of a DC integrated timing optimization method according to an embodiment of the present invention;

FIG. 2 is a logic diagram of DC integrated timing optimization provided by one embodiment of the present invention;

FIG. 3 is a flow chart of a DC integrated timing optimization method according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of a DC integrated timing optimization apparatus according to another embodiment of the present invention;

fig. 5 is an internal structural view of a computer device according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In one embodiment, referring to fig. 1, the present invention provides a DC integrated timing optimization method, including the following steps:

s100, initializing DC comprehensive parameters and time sequence analysis parameters;

s200, executing a DC comprehensive operation to generate a comprehensive result and a comprehensive report;

s300, in response to the DC comprehensive operation is executed, determining whether a significant time sequence violation exists based on the comprehensive report and the time sequence analysis parameters;

s400, in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time based on the preset priority sequence of a plurality of preset adjustment items;

and S500, responding to the condition that no major time sequence violation exists, and outputting a comprehensive result corresponding to the DC comprehensive operation.

According to the DC comprehensive time sequence optimization method, whether major time sequence violation exists is determined through the comprehensive report and the time sequence analysis parameters, parameter adjustment is carried out on the DC comprehensive on the basis of the preset adjustment rule for the condition that the major time sequence violation exists, the DC comprehensive operation is executed again, the comprehensive result is output until the major time sequence violation does not occur after the comprehensive operation, automatic time sequence optimization during the DC comprehensive is achieved, engineer intervention or manual adjustment is not needed during the operation of a system, the optimal result can be output automatically, time is saved greatly, and the working efficiency is improved.

In yet another embodiment, the step of initializing the DC synthesis parameters and the timing analysis parameters comprises:

initializing DC comprehensive parameters, wherein the initializing DC comprehensive parameters comprise initializing library file selection, clock setting, resetting setting, input and output delay, comprehensive area, input and output load, line load model, maximum conversion time, maximum fan-out number and key path grouping, and the clock setting comprises clock period, clock duty ratio, clock jitter and multi-clock period;

initializing timing analysis parameters includes initializing clock cycles.

In yet another embodiment, step S300 includes the sub-steps of:

fifteen percent of the clock period is calculated as a comparison value,

reading the slack value of the Violated option from the comprehensive report by utilizing a report timing command and judging whether the slack value is a negative number or not;

in response to the slack value being negative, comparing the absolute value of the slack value to the comparison value;

in response to the absolute value of the slack value being greater than the comparison value, confirming that there is a significant timing violation of the DC synthesis operation;

in response to the absolute value of the slack value being less than or equal to the comparison value, confirming that the DC synthesis operation is free of significant timing violations.

In yet another embodiment, the plurality of preset adjustment items include adjusting a DC synthesis compile option, modifying an input-output delay item, and modifying an input-output drive capability item, wherein the modifying the input-output drive capability item includes modifying an input-output load and modifying a maximum fan-out number.

In another embodiment, the preset priority order is that the priorities of adjusting the DC synthesis compiling option, modifying the input and output delay items, and modifying the input and output driving capability items are sequentially changed from high to low.

In yet another embodiment, the DC synthesis compilation option includes three compilation modes, low, medium and high.

In yet another embodiment, the input-output delay in the modified input-output delay entry ranges from 30% to 50% of the clock period.

In another example, to facilitate understanding of the technical solution of the present invention, please refer to fig. 2, the concept of the present invention mainly consists of several aspects:

first part, initialization parameters: the primary function of the initialization parameters is to initialize various parameter settings, including synthesis parameters to the DC synthesis and analysis parameters to the results analysis. The parameters for DC synthesis mainly comprise library file selection, clock setting (clock period, clock duty ratio, clock jitter, multi-clock period and the like), reset setting, input and output delay, synthesis area, input and output load, line load model, maximum conversion time, maximum fan-out number, key path grouping and the like; the parameters given to the result analysis mainly include clock cycles, and the parameters of the result analysis are mainly used to calculate timing information.

A second part, carrying out comprehensive operation by a DC comprehensive tool, carrying out DC comprehensive for one time after the DC comprehensive tool receives the initialized parameters, and carrying out DC comprehensive after the parameters are subsequently modified;

and analyzing results, reading the comprehensive results and the comprehensive report, checking whether the time sequence meets the requirements, if not, performing corresponding parameter adjustment, and feeding back to the DC for comprehensive operation until the optimal result is output. Specifically, the way to check whether the timing is satisfied is: receiving analysis parameter information given during initialization, calculating a time sequence requirement required by current design, reading a result for analysis after the DC synthesis is subjected to synthesis operation, and adjusting constraint parameters according to the result if the requirement is not met, and feeding back the constraint parameters to the DC synthesis for synthesis again; if the requirements are met, the comprehensive result is output.

The method is mainly realized by combining a DC tcl statement (comprising a conditional branch statement and a loop statement), and controls a corresponding flow to jump. In the parameter initializing part, a template can be initialized, an engineer can select and add initial parameters according to the current RTL design, after the addition is completed, when the parameters are transmitted to a DC comprehensive tool, the DC comprehensive tool can automatically generate a TCL script language which can be identified by a DC according to the parameters, and necessary statements are added (for example, a dot touch is added to a clock signal and a reset signal), then the DC is controlled to start comprehensive work, after the integration is completed, a timing result is output through a report timing command, the result can be read during result analysis, if the timing violation is read during result analysis (the slack is a negative value), at the moment, parameter correction can be performed in a point range according to the size of the slack; otherwise, outputting the comprehensive result.

It is generally believed that if the magnitude of the Violated (i.e., the absolute value in the case of negative values of the slack) exceeds 15% of the current clock cycle, a significant timing violation is expected and the result analysis readjustment parameter needs to be fed back to the DC synthesis for re-synthesis. If the timing does not meet the requirements, a significant timing violation occurs, and the analysis of the results can be fed back to the DC synthesis by adjusting parameters (in order of priority) through the following preset adjustment items:

presetting an adjustment item 1: adjusting a compiling option, namely a compile-map _ effect (low | medium | high) command, selecting different compiling requirements, wherein a compiling result and a compiling time are different, a medium-level medium is recommended to be used initially, and a high-level high can obtain the best effect but has the longest compiling time; if the requirements have not been met, the build _ ultra may be used.

Presetting an adjustment item 2: the input and output delay is modified, the influence of the input and output delay on the time sequence is significant, the default can be generally set to 40% of the current clock cycle, when the system is initialized to operate, a range can be preset according to the experience of a back-end engineer, for example, 30% -50% of the current clock cycle, and the optimal selection of the area and the time sequence can be carried out within the range.

The adjustment item 3 is preset, the input and output driving capability is modified, a default driving capability exists generally, a plurality of driving capability ranges and fan-out number ranges can be set according to experience of rear-end engineers, and optimal selection is carried out in the ranges.

For example, assuming that a major timing violation is found after the first DC synthesis, at this time, if the initial default compiling option is medium, the compiling option is modified to high, if the major timing violation still exists during the second DC synthesis, the i/o delay is modified to be the item with the highest priority, the i/o delays with various values can be modified, and the DC synthesis can be performed after each modification to attempt to eliminate the major timing violation, and similarly, if the i/o delays are modified, the i/o driving capability is modified and the second DC synthesis is performed again in a similar manner, if the major timing violation is not eliminated during the modification of the i/o delays. And through parameter modification of the preset adjustment items, analyzing results and feeding back to the DC synthesis for time sequence optimization, and obtaining an optimal result after the DC synthesis is carried out again. If the above cannot meet the timing requirement, an engineer is required to check whether the initialization parameter is correctly set, and if the initialization parameter is correctly set, a front-end engineer is required to be fed back to modify the RTL code.

Specifically, referring to fig. 3, after the front-end designer completes the RTL design, the DC synthesis engineer may refer to experiences of the front-end designer in designing related design contents such as clocks, resets, and the like, and then input information to the initialization module according to the experience of the back-end designer regarding related contents required by the timing sequence, and during initialization, the information is summarized and added to the template, and is transmitted to the DC synthesis tool, and the DC synthesis tool receives the information, and then adds some statement commands necessary for DC synthesis, generates a TCL file that the DC can execute, and starts to perform the first DC synthesis. After the DC integration is completed, the DC integration report is read during result analysis, whether the violated (slack is a negative value) exists is checked, whether the size of the violated meets the requirement of 15% is judged, and if the violated size meets the requirement, a result is output; if the time sequence requirement is not met, adjusting parameters are fed back to the DC synthesis module according to the priority levels of the compiling options, the input and output delays and the driving capability, and the second and third synthesis … … are carried out until the time sequence requirement is met, and the result is output. If the requirements cannot be met, the front-end engineer can modify the RTL code and try DC synthesis again.

The method of the invention at least has the following beneficial technical effects:

(1) the whole process is controlled to skip and run through the DC-TCL, DC comprehensive operation and time sequence optimization can be automatically run after initialization parameters are output, adjustment parameters are timely fed back to the DC through the slack information of an automatic retrieval comprehensive report, a closed loop is formed, and the time sequence optimization of the DC is automatically completed.

(2) After primary initialization setting is completed, DC comprehensive work and time sequence optimization work can be automatically carried out, the whole process is manually participated, chip development time is greatly saved, and work efficiency is improved.

In another embodiment, please refer to fig. 4, the present invention further provides a DC integrated timing optimization apparatus 60, which includes:

an initialization module 61, configured to initialize the DC synthesis parameters and the timing analysis parameters;

a synthesis module 62, configured to, when the DC synthesis completion parameter is initialized, perform a DC synthesis operation to generate a synthesis result and a synthesis report;

a timing analysis module 63, configured to determine whether there is a significant timing violation based on the synthesis report and the timing analysis parameters when the DC synthesis operation is completed;

a parameter adjusting module 64, configured to, when there is a significant timing violation, perform parameter adjustment on the DC synthesis based on a preset adjusting rule and re-execute the DC synthesis operation, where the preset adjusting rule is a preset adjusting item with the highest adjusting priority in each order based on a preset priority ranking of a plurality of preset adjusting items;

and the output module 65 is configured to output a comprehensive result corresponding to the current DC comprehensive operation when there is no major timing violation.

According to the DC comprehensive time sequence optimization device, whether a major time sequence violation exists or not is determined through the comprehensive report and the time sequence analysis parameters, parameter adjustment is carried out on the DC comprehensive on the basis of the preset adjustment rule for the condition that the major time sequence violation exists, the DC comprehensive operation is executed again, the comprehensive result is output until the major time sequence violation does not occur after the comprehensive operation, automatic time sequence optimization during the DC comprehensive operation is realized, engineer intervention or manual adjustment is not needed during the operation of a system, the optimal result can be output automatically, the time is greatly saved, and the working efficiency is improved.

It should be noted that, for specific limitations of the DC integrated timing optimization apparatus, reference may be made to the above limitations of the DC integrated timing optimization method, which is not described herein again. The respective blocks in the above-described DC integrated timing optimization apparatus can be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

According to another aspect of the present invention, a computer device is provided, the computer device may be a server, and the internal structure thereof is shown in fig. 5. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements the DC synthetic timing optimization method described above, in particular the method comprising the steps of:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists. According to a further aspect of the present invention, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the DC synthetic timing optimization method described above, in particular comprising performing the steps of:

initializing DC comprehensive parameters and time sequence analysis parameters;

performing a DC synthesis operation to generate a synthesis result and a synthesis report;

in response to performing a DC synthesis operation, determining whether there is a significant timing violation based on the synthesis report and the timing analysis parameters;

in response to the existence of the major time sequence violation, performing parameter adjustment on the DC synthesis based on a preset adjustment rule and re-executing the DC synthesis operation, wherein the preset adjustment rule is a preset adjustment item with the highest adjustment priority in each time of preset priority ranking based on a plurality of preset adjustment items;

and outputting a comprehensive result corresponding to the DC comprehensive operation in response to the fact that no major time sequence violation exists.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.