阅读说明：本技术 制造半导体结构的方法 (Method for fabricating semiconductor structure ) 是由 丘世仰 于 2021-04-28 设计创作，主要内容包括：本发明公开了一种制造半导体结构的方法,包含以下操作。提供沿第一方向延伸的基板。形成横跨基板的沟槽以定义第一主动区及第二主动区。在沟槽中形成底部隔离结构,其中底部隔离结构暴露基板的侧壁的一部分。氧化基板暴露的侧壁以在底部隔离结构上形成顶部隔离结构,其中顶部隔离结构延伸到基板中。形成嵌入顶部隔离结构的导电结构。分别在第一主动区及第二主动区中形成第一晶体管及第二晶体管。本发明的方法可以减少具有反熔丝结构和晶体管的半导体结构的尺寸,从而实现高装置密度。(A method of fabricating a semiconductor structure includes the following operations. A substrate is provided that extends in a first direction. A trench is formed across the substrate to define a first active region and a second active region. A bottom isolation structure is formed in the trench, wherein the bottom isolation structure exposes a portion of the sidewalls of the substrate. The exposed sidewalls of the substrate are oxidized to form top isolation structures on the bottom isolation structures, wherein the top isolation structures extend into the substrate. A conductive structure is formed that is embedded in the top isolation structure. A first transistor and a second transistor are formed in the first active region and the second active region, respectively. The method of the present invention can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate extending along a first direction;

forming a trench across the substrate to define a first active region and a second active region;

forming a bottom isolation structure in the trench, wherein the bottom isolation structure exposes a portion of a sidewall of the substrate;

oxidizing the exposed sidewalls of the substrate to form top isolation structures on the bottom isolation structures, wherein the top isolation structures extend into the substrate;

forming a conductive structure embedded in the top isolation structure; and

a first transistor and a second transistor are formed in the first active region and the second active region, respectively.

2. The method of claim 1, wherein the source/drain regions of the first transistor and the second transistor each have a lower surface that is below a lower surface of the conductive structure.

3. The method of claim 2, wherein the top isolation structure and the bottom isolation structure collectively separate the conductive structure from the source/drain regions of the first transistor and the second transistor.

4. The method of claim 1, wherein the trench has a width that is greater than a width of the conductive structure.

5. The method of claim 1, wherein forming the first transistor and the second transistor comprises:

forming a gate structure on the substrate of the first active region and the second active region; and

forming source/drain regions in the substrate of the first and second active regions, wherein the source/drain regions are located on opposite sides of the top isolation structure.

6. The method of claim 5, further comprising forming a plurality of contact plugs connected to the source/drain regions, the gate structure, and the conductive structure of the first transistor and the second transistor, respectively.

7. A method of fabricating a semiconductor structure, comprising:

providing a substrate comprising a plurality of active regions extending along a first direction, wherein the plurality of active regions are separated from each other by shallow trench isolation structures;

forming a trench across the plurality of active regions and the shallow trench isolation structure;

forming an antifuse structure in the trench, wherein the antifuse structure includes an isolation structure overlying the trench and a conductive structure embedded in the isolation structure; and

forming a transistor in each active region, wherein the transistor is separated from the conductive structure by the isolation structure.

8. The method of claim 7, wherein forming the antifuse structure comprises:

forming a bottom portion of the isolation structure in the trench, wherein the bottom portion of the isolation structure has a height that is less than a depth of the trench;

forming a top portion of the isolation structure, wherein the top portion extends laterally into the substrate; and

forming the conductive structure on the isolation structure.

9. The method of claim 7, wherein forming the transistor comprises:

forming a gate structure on the substrate of each active region; and

forming a source/drain region in the substrate of each of the active regions, wherein the source/drain region is adjacent to the gate structure and has a lower surface located below a lower surface of the conductive structure.

10. The method of claim 9, further comprising forming a plurality of contact plugs respectively connected to the source/drain regions, the gate structure, and the conductive structure.

Technical Field

The present invention relates to a method of fabricating a semiconductor structure. More particularly, the present invention relates to a method of fabricating a semiconductor structure having an antifuse structure.

Background

Fuse (fuse) elements are commonly used in semiconductor devices, such as semiconductor memories or logic devices. The antifuse has electrical characteristics opposite to those of the fuse, and can repair a defective cell by replacing the defective cell with a redundant cell.

Typically, an antifuse needs to be controlled by a control gate adjacent to it. Therefore, a memory cell (unit cell) is defined as 1T1C, representing a transistor (gate) and a capacitor (antifuse). However, as the number of antifuses increases, the conventional 1T1C structure occupies a large area. To achieve high density memory cells or redundancy, the memory cells should be as small as possible.

Disclosure of Invention

An object of the present invention is to provide a method of manufacturing a semiconductor structure, which can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.

According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate extending in a first direction. A trench is formed across the substrate to define a first active region and a second active region. The exposed sidewalls of the substrate are oxidized to form top isolation structures on the bottom isolation structures, wherein the top isolation structures extend into the substrate. A conductive structure is formed that is embedded in the top isolation structure. A first transistor and a second transistor are formed in the first active region and the second active region, respectively.

According to some embodiments of the present invention, the source/drain regions of the first transistor and the second transistor each have a lower surface that is below the lower surface of the conductive structure.

According to some embodiments of the present invention, the top isolation structure and the bottom isolation structure collectively separate the conductive structure from the source/drain regions of the first transistor and the second transistor.

According to some embodiments of the invention, the width of the trench is greater than the width of the conductive structure.

According to some embodiments of the present invention, forming the first transistor and the second transistor includes forming a gate structure on the substrate in the first active region and the second active region; and forming source/drain regions in the substrate of the first and second active regions, wherein the source/drain regions are located on opposite sides of the top isolation structure.

According to some embodiments of the present invention, the method further comprises forming a plurality of contact plugs respectively connected to the source/drain regions, the gate structures and the conductive structures of the first transistor and the second transistor.

According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate including a plurality of active regions extending along a first direction, wherein the active regions are separated from each other by shallow trench isolation structures. Forming a trench crossing the active region and the shallow trench isolation structure. An antifuse structure is formed in the trench, wherein the antifuse structure includes an isolation structure overlying the trench and a conductive structure embedded in the isolation structure. Transistors are formed in each active region, wherein the transistors are separated from the conductive structures by isolation structures.

According to some embodiments of the present invention, forming the antifuse structure comprises forming a bottom portion of an isolation structure in the trench, wherein a height of the bottom portion of the isolation structure is less than a depth of the trench; forming a top portion of the isolation structure, wherein the top portion extends laterally into the substrate; and forming a conductive structure on the isolation structure.

According to some embodiments of the present invention, forming transistors includes forming a gate structure on the substrate in each active region; and forming a source/drain region in the substrate in the active region, wherein the source/drain region is adjacent to the gate structure and has a lower surface located below the lower surface of the conductive structure.

According to some embodiments of the present invention, the method includes forming a plurality of contact plugs respectively connected to the source/drain regions, the gate structure, and the conductive structure.

Compared with the prior art, the method for manufacturing the semiconductor structure has the following beneficial effects: a pair of anti-fuse structures is formed between two adjacent transistors and can be blown at the same time. Accordingly, the method can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.

Drawings

Aspects of the invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments of the present invention.

Fig. 2-4 are top views of various steps in a process for fabricating a semiconductor structure according to some embodiments of the present invention.

Fig. 5A, 6A, 7A, 8A, 9A, and 10A are cross-sectional views taken along line a-a' of fig. 4 at various steps in a process for fabricating a semiconductor structure according to some embodiments of the present invention.

Fig. 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional views taken along line B-B' of fig. 4 at various steps in a process for fabricating a semiconductor structure according to some embodiments of the present invention.

Fig. 11 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

Description of the main reference numerals:

10-method; 12,14,16,18,20, 22-operation; 100-a semiconductor; 102,104, 106-active region; 102 a-a first active region; 102 b-a second active region; 108-a side wall; 110-shallow trench isolation structures; 120-a mask layer; 200-an isolation structure; 200' -an isolation layer; 202-bottom isolation structures; 204-top isolation structure; 210-a conductive structure; 210S,312S,322S — lower surface; 302 a-a first transistor; 302 b-a second transistor; 310, 320-gate structures; 312, 322-source/drain regions; 400-contact plug; A-A ', B-B' -line segment; AF1, AF 2-antifuse structure; d1-first direction; d2-second direction; h1, H1' -depth; h2-height; OP 1-opening; t1-trench; w1, W2-Width.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such examples are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "below," "beneath," "above," "over," and the like, may be used herein for ease of describing the relative relationship of one element or feature to another element or feature as illustrated in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when the drawings are turned over 180 degrees, the relationship between one element and another may change from "below" to "above" or "over". Spatially relative descriptors used herein should be interpreted as such.

Fig. 1 is a flow chart illustrating a method 10 of fabricating a semiconductor structure according to some embodiments of the present invention. Method 10 includes operation 12, operation 14, operation 16, operation 18, operation 20, and operation 22. It should be noted that the method shown in fig. 1 is merely an example and is not intended to limit the present invention. Accordingly, additional operations may be performed before, during, and/or after the method illustrated in fig. 1, and only some other operations are briefly described herein. Fig. 2-4 and 5A-11 are top and cross-sectional views, respectively, of steps in a process for fabricating a semiconductor structure according to method 10 of fig. 1.

Please refer to fig. 1 and fig. 2. In operation 12 of fig. 1, a substrate 100 is provided that extends in a first direction D1. The substrate 100 may include a plurality of active regions 102,104 and 106 extending along a first direction D1. Adjacent active regions are separated by a shallow trench isolation structure 110. For example, as shown in fig. 2, the shallow trench isolation structure 110 is located between and separates the active region 102 and the active region 104. In some embodiments, the substrate 100 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium or the like, a silicon-on-insulator (SOI) substrate, or the like. In some embodiments, the shallow trench isolation structure 110 comprises Tetraethoxysilane (TEOS), silicon oxide, silicon nitride, silicon oxynitride, or fluoride doped silicate (FSG).

Referring to fig. 3, a mask layer 120 is formed on the substrate 100 to cover the active regions 102,104,106 and the sti structure 110. In some embodiments, the masking layer 120 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable materials, or combinations thereof. The mask layer 120 may be formed on the substrate 100 by a suitable deposition method including a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or a combination thereof. In some embodiments, the masking layer 120 is patterned and has an opening OP1 to expose the underlying structure. The mask layer 120 may be patterned by an appropriate method, for example, using a photolithography patterning (photolithography) process and an etching process. Accordingly, an opening OP1 is formed in the mask layer 120 to expose the active regions 102,104 and 106 and a portion of the sti structure 110.

Please refer to fig. 1 and fig. 4. In operation 14 of fig. 1, a trench T1 is formed across the substrate 100. In some embodiments, the active regions 102,104,106 and the portion of the sti structure 110 exposed by the opening OP1 (shown in fig. 3) are etched to form a trench T1 in the substrate 100. The trench T1 extends along the second direction D2, crossing the active regions 102,104 and 106 and the sti structure 110, such that the active regions 102,104 and 106 are divided into a plurality of segments. For example, the trench T1 crosses the active region 102 to define a first active region 102a and a second active region 102 b.

Fig. 5A and 5B are cross-sectional views taken along line a-a 'and line B-B' of fig. 4, respectively. As shown in fig. 5A, the trench T1 exposes the sidewall 108 of the substrate 100. The substrate 100 and a portion of the shallow trench isolation structure 110 may be etched by a suitable etching process to form the trench T1. In some embodiments, the depth H1 of the trench T1 in the active region 102 (as shown in fig. 5A) is deeper than the depth H1' in the shallow trench isolation structure 110 (as shown in fig. 5B). In the following operation, a cross-sectional view of the active region 102 and the adjacent shallow trench isolation structure 110 is taken as an example.

Next, in operation 16 of fig. 1, a bottom isolation structure 202 is formed in the trench T1. Fig. 6A to 7B illustrate the detailed steps of performing operation 16 according to an embodiment of the present invention. Fig. 6A, 7A and 6B, 7B are cross-sections taken along line a-a 'and B-B' of fig. 4, respectively.

Referring to fig. 6A and 6B, the trench T1 is filled with an insulating material, thereby forming an isolation layer 200'. In some embodiments, isolation layer 200' comprises silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), or fluoride doped silicate (FSG). In some examples, the material of the isolation layer 200' is the same as the material of the shallow trench isolation structure 110. The isolation layer 200' may be formed by a suitable deposition method including a CVD process, an ALD process, a PVD process, or combinations thereof. In some embodiments, an isolation material may be formed in the trench T1 and cover the top surface of the masking layer 120, and then a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed to form the isolation layer 200'.

Next, referring to fig. 7A and 7B, the isolation layer 200' is recessed to form a bottom isolation structure 202. The recess isolation layer 200' exposes a portion of the sidewall 108 of the substrate 100 to be oxidized in a subsequent step. In some embodiments, the bottom isolation structure 202 is formed by using an appropriate anisotropic (anistropic) etching process (e.g., a dry etching process). In some embodiments, the height H2 of the bottom isolation structure 202 is less than the depth H1 of the trench T1 in the substrate 100.

Please refer to fig. 1 and fig. 8A-8B. In operation 18 of fig. 1, the exposed sidewalls 108 of the substrate 100 are oxidized to form top isolation structures 204 on the bottom isolation structures 202, wherein the top isolation structures 204 extend into the substrate 100. In some embodiments, the top isolation structure 204 is formed by performing a thermal oxidation process to oxidize the exposed sidewalls 108 of the substrate 100 (as shown in fig. 7A). As shown in fig. 8A, the top isolation structure 204 extends laterally into the substrate 100. Specifically, the top isolation structure 204 is formed on the bottom isolation structure 202 and has an opening exposing a portion of the top surface of the bottom isolation structure 202. As such, the top isolation structure 204 and the bottom isolation structure 202 collectively form the isolation structure 200 to cover the sidewalls and bottom of the trench T1.

Please refer to fig. 1 and fig. 9A-9B. In operation 20 of fig. 1, a conductive structure 210 is formed that is embedded in the isolation structure 200. In some embodiments, the conductive structure 210 is formed by a suitable deposition method, including a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or a combination thereof. Conductive structures 210 are disposed on the exposed top surface of the bottom isolation structure 202 shown in fig. 8A. Specifically, the bottom portions of the sidewalls of the conductive structures 210 are covered by the top isolation structures 204. That is, the top isolation structure 204 separates the conductive structure 210 from the substrate 100. As shown in fig. 9A, the width W2 of the conductive structure 210 is less than the width W1 of the trench T1. In some embodiments, the conductive structure 210 comprises a conductive material (e.g., polysilicon, metal alloy), other suitable materials, and/or combinations thereof.

Referring to fig. 10A and 10B, after the conductive structure 210 is formed, the mask layer 120 is removed (as shown in fig. 9A and 9B). Specifically, the mask layer 120 is removed by an etching process, such as a dry etching process or a wet etching process, to expose the top surface of the substrate 100. .

Please refer to fig. 1 and fig. 11. In operation 22 of fig. 1, a first transistor 302a and a second transistor 302 are formed in the first active region 102a and the second active region 102b, respectively. As shown in fig. 11, the first transistor 302a includes a gate structure 310 and source/drain regions 312, and the second transistor 302b includes a gate structure 320 and source/drain regions 322. In some embodiments, the first transistor 302a and the second transistor 302b are formed in a p-well region (not shown) of the substrate 100. Source/drain regions 312 and 322 are located on opposite sides of the isolation structure 200, adjacent to the gate structures 310 and 320, respectively. The source/drain regions 312 and 322 have lower surfaces 312s and 322s, respectively, located below the lower surface 210s of the conductive structure 210, so that the conductive structure is completely isolated from the p-well region of the substrate 100 to prevent a leakage problem (leakage current).

The formation of the first transistor 302a may include forming a gate structure 310 on the substrate 100 of the first active region 102a and forming source/drain regions 312 in the substrate 100 of the first active region 102 a. For example, the formation of the gate structure 310 may include a suitable deposition method, such as a CVD process, a PVD process, or the like. In some embodiments, the gate structure 310 comprises polysilicon, a metal such as aluminum (Al), copper (Cu), or tungsten (W), other conductive materials, or combinations thereof. In addition, the source/drain regions 312 may be formed by performing an ion implantation (ion implantation) process, and the doping depth must be deeper than the lower surface 210s of the conductive structure 210. In some embodiments, the source/drain regions 312 are doped with an N-type dopant, such as phosphorous or arsenic. The gate structure 320 and the source/drain regions 322 of the second transistor 302b may be formed of the same materials and have the same formation as the first transistor 302a, and thus are not described again. It should be noted that other transistors (not shown) may also be formed in other active regions (e.g., active regions 104, 106) by the above-described process.

In some embodiments, after forming the first transistor 302a and the second transistor 302b, the method further comprises forming a plurality of contact plugs connected to the source/drain regions 312,322 and the gate structures 310,320 of the first and second transistors 302a, 302b, respectively, and the conductive structure 210. For example, the contact plug 400 is grounded and connected to the source/drain regions 312 and 322, respectively, which are far from the isolation structure 200.

With continued reference to fig. 11, the isolation structure 200 separates the conductive structure 210 from the source/drain regions 312 and 322 of the first transistor 302a and the second transistor 302 b. A pair of antifuse structures AF1 and AF2 are formed between transistors 302a and 302 b. Conductive structure 210 serves as a top plate (top plate) for anti-fuse structures AF1 and AF 2. The source/drain regions 312 and 322 serve as bottom plates (bottom plates) for the anti-fuse structures AF1 and AF 2. Isolation structure 200, and in more detail top isolation structure 204, acts as a dielectric layer between the top and bottom plates of antifuse structures AF1 and AF 2. Specifically, the anti-fuse structure AF1 includes a conductive structure 210, an isolation structure 200, and a source/drain region 312 shared with the transistor 302 a. Similarly, the anti-fuse structure AF2 includes a conductive structure 210, an isolation structure 200, and a source/drain region 322 shared with the transistor 302 b. A voltage may be applied across the antifuses AF1 and AF2 (i.e., source/drain regions 312,322 and conductive structure 210) to cause a breakdown of the dielectric layer, which results in a rupture of the dielectric layer.

As described above, according to an embodiment of the present invention, a method of manufacturing a semiconductor structure is provided. In the fabrication of the semiconductor structure of the present invention, isolation structures separate the substrate into a plurality of active regions. Conductive structures are then embedded from the top surface of the isolation structure and transistors are formed in the active regions on opposite sides of the isolation structure. Therefore, a pair of anti-fuse structures is formed between two adjacent transistors and can be blown (blown out) at the same time. In other words, the method of the present invention can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.