阅读说明：本技术 电阻式存储装置以及其制作方法 (Resistive memory device and manufacturing method thereof ) 是由 刘宇恒 符云飞 黄志坚 黄国良 谈文毅 于 2020-05-12 设计创作，主要内容包括：本发明公开一种电阻式存储装置以及其制作方法,其中该电阻式存储装置包括第一电极、第二电极、第一金属氧化物层、第二金属氧化物层以及多层绝缘体结构。第一金属氧化物层于垂直方向上设置于第一电极与第二电极之间。第二金属氧化物层于垂直方向上设置于第一金属氧化物层与第二电极之间。多层绝缘体结构于垂直方向上设置于第一金属氧化物层与第二金属氧化物层之间。第一金属氧化物层包括多个第一金属原子,第二金属氧化物层包括多个第二金属原子,而多层绝缘体结构包括多个第三金属原子。各第三金属原子与各第二金属原子相同,且第三金属原子在多层绝缘体结构中的原子百分比于垂直方向上逐渐改变。(The invention discloses a resistive memory device and a manufacturing method thereof, wherein the resistive memory device comprises a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer and a multilayer insulator structure. The first metal oxide layer is arranged between the first electrode and the second electrode in the vertical direction. The second metal oxide layer is arranged between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction. The first metal oxide layer includes a plurality of first metal atoms, the second metal oxide layer includes a plurality of second metal atoms, and the multilayer insulator structure includes a plurality of third metal atoms. Each third metal atom is the same as each second metal atom, and the atomic percentage of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.)

1. A resistive memory device, comprising:

a first electrode;

a second electrode;

a first metal oxide layer disposed between the first electrode and the second electrode in a vertical direction, wherein the first metal oxide layer includes a plurality of first metal atoms;

a second metal oxide layer disposed between the first metal oxide layer and the second electrode in the vertical direction, wherein the second metal oxide layer includes a plurality of second metal atoms; and

a multilayer insulator structure disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction, wherein the multilayer insulator structure includes a plurality of third metal atoms, each of the third metal atoms is the same as each of the second metal atoms, and an atomic percentage (at.%) of the plurality of third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

2. The resistive memory structure of claim 1 wherein an atomic percentage of the plurality of second metal atoms in the second metal oxide layer is higher than the atomic percentage of the plurality of third metal atoms in the multilayer insulator structure.

3. The resistive memory structure of claim 1 wherein the multilayer insulator structure has opposing first and second surfaces in the vertical direction, the first surface being connected to the first metal oxide layer and the second surface being connected to the second metal oxide layer.

4. The resistive memory structure of claim 3 wherein the atomic percentage of the plurality of third metal atoms in the multilayer insulator structure increases from the first surface to the second surface.

5. The resistive memory structure of claim 3 wherein the multilayer insulator structure further comprises a plurality of fourth metal atoms, each of the fourth metal atoms being the same as each of the first metal atoms, wherein the atomic percentage of the plurality of first metal atoms in the first metal oxide layer is higher than the atomic percentage of the plurality of fourth metal atoms in the multilayer insulator structure, and the atomic percentage of the plurality of fourth metal atoms in the multilayer insulator structure decreases from the first surface to the second surface.

6. The resistive memory structure of claim 1 wherein the thickness of the multilayer insulator structure in the vertical direction is greater than the thickness of the first metal oxide layer in the vertical direction and the thickness of the second metal oxide layer in the vertical direction.

7. The resistive memory structure of claim 1 wherein a first layer of the multilayer insulator structure is disposed between a second layer of the multilayer insulator structure and the first metal oxide layer in the vertical direction, and an atomic percentage of the plurality of third metal atoms in the second layer is higher than an atomic percentage of the plurality of third metal atoms in the first layer.

8. The resistive memory structure of claim 7 wherein the atomic percentage of the plurality of third metal atoms in the first layer is present in a first region in the first layer and the length of the first region in the vertical direction is greater than or equal to 90% of the thickness of the first layer in the vertical direction.

9. The resistive memory structure of claim 7 wherein the atomic percentage of the plurality of third metal atoms in the second layer is present in a second region in the second layer, and the length of the second region in the vertical direction is greater than or equal to 90% of the thickness of the second layer in the vertical direction.

10. The resistive memory structure of claim 7 wherein a third layer of the multi-layer insulator structure is disposed between the second layer and the second metal oxide layer of the multi-layer insulator structure in the vertical direction, and an atomic percentage of the plurality of third metal atoms in the third layer is higher than the atomic percentage of the plurality of third metal atoms in the second layer.

11. The resistive memory structure of claim 7 wherein the multi-layer insulator structure further comprises a plurality of fourth metal atoms, each of the fourth metal atoms being the same as each of the first metal atoms, wherein the atomic percentage of the plurality of fourth metal atoms in the first layer is higher than the atomic percentage of the plurality of fourth metal atoms in the second layer.

12. The resistive memory structure of claim 11 wherein a third layer of the multi-layer insulator structure is disposed between the second layer of the multi-layer insulator structure and the second metal oxide layer in the vertical direction, and the atomic percentage of the plurality of fourth metal atoms in the second layer is higher than the atomic percentage of the plurality of fourth metal atoms in the third layer.

13. The resistive memory structure of claim 1 wherein the first metal oxide layer is free of the second metal atoms and the second metal oxide layer is free of the first metal atoms.

14. A method for manufacturing a resistive memory device includes:

forming a first electrode;

forming a first metal oxide layer on the first electrode, wherein the first metal oxide layer includes a plurality of first metal atoms;

forming a multi-layered insulator structure on the first metal oxide layer;

forming a second metal oxide layer on the multilayer insulator structure, wherein the second metal oxide layer comprises a plurality of second metal atoms, the multilayer insulator structure comprises a plurality of third metal atoms, and each of the third metal atoms is the same as each of the second metal atoms; and

forming a second electrode on the second metal oxide layer, wherein the multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction, and an atomic percentage (at.%) of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

15. The method of claim 14, wherein said multilayer insulator structure is formed before said second metal oxide layer.

16. The method of claim 14, wherein a first layer of the multi-layer insulator structure is formed on the first metal oxide layer using a first fabrication process, a second layer of the multi-layer insulator structure is formed on the first layer of the multi-layer insulator structure using a second fabrication process, and the second fabrication process is performed after the first fabrication process.

17. The method of claim 16, wherein the atomic percentage of the third metal atoms in the second layer is higher than the atomic percentage of the third metal atoms in the first layer.

18. The method of claim 17, wherein a third layer of the multi-layer insulator structure is formed on the second layer of the multi-layer insulator structure by a third process, the third process is performed after the second process, and an atomic percentage of the third metal atoms in the third layer is higher than the atomic percentage of the third metal atoms in the second layer.

19. The method of claim 16, wherein the multi-layer insulator structure further comprises a plurality of fourth metal atoms, each of the fourth metal atoms being the same as each of the first metal atoms, wherein the atomic percentage of the plurality of first metal atoms in the first metal oxide layer is higher than the atomic percentage of the plurality of fourth metal atoms in the multi-layer insulator structure, and the atomic percentage of the plurality of fourth metal atoms in the first layer is higher than the atomic percentage of the plurality of fourth metal atoms in the second layer.

20. The method of claim 19, wherein a third layer of the multi-layer insulator structure is formed on the second layer of the multi-layer insulator structure by a third process, the third process is performed after the second process, and the atomic percentage of the fourth metal atoms in the second layer is higher than the atomic percentage of the fourth metal atoms in the third layer.

Technical Field

The present invention relates to a resistive memory device and a method for fabricating the same, and more particularly, to a resistive memory device having a multi-layer insulator structure and a method for fabricating the same.

Background

Semiconductor memories are semiconductor devices used for storing data in computers or electronic products, and can be broadly classified into volatile memories (vollatile) and non-volatile memories (non-vollatile). Volatile memory refers to computer memory in which stored data disappears when power to the computer is interrupted, while non-volatile memory has the characteristic of not losing stored data due to power interruption. Resistive Random Access Memory (RRAM) is a nonvolatile memory that has characteristics of low operating voltage, low power consumption, and high writing speed, and is considered as a memory structure that can be applied to many electronic devices.

Disclosure of Invention

The invention provides a resistive memory device and a manufacturing method thereof, which utilize a multi-layer insulator structure with gradually changed metal atom concentration to improve the relevant characteristics of the resistive memory device.

An embodiment of the present invention provides a resistive memory device, which includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multi-layer insulator structure. The first metal oxide layer is arranged between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is arranged between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction. The first metal oxide layer includes a plurality of first metal atoms, the second metal oxide layer includes a plurality of second metal atoms, and the multilayer insulator structure includes a plurality of third metal atoms. Each third metal atom is the same as each second metal atom, and the atomic percentage of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

An embodiment of the present invention provides a method for manufacturing a resistive memory device, including the following steps. A first electrode is formed. A first metal oxide layer is formed on the first electrode. The first metal oxide layer includes a plurality of first metal atoms. A multi-layer insulator structure is formed on the first metal oxide layer. A second metal oxide layer is formed on the multi-layer insulator structure. The second metal oxide layer includes a plurality of second metal atoms, the multilayer insulator structure includes a plurality of third metal atoms, and each third metal atom is the same as each second metal atom. And forming a second electrode on the second metal oxide layer. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction, and an atomic percentage of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

Drawings

FIG. 1 is a diagram illustrating a resistive memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating the operation of a resistive memory device according to a first embodiment of the present invention;

FIG. 3 is a diagram illustrating a resistive memory device according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating the operation of a resistive memory device according to a second embodiment of the present invention;

FIG. 5 to FIG. 9 are schematic diagrams illustrating a method for fabricating a resistive memory device according to an embodiment of the present invention, wherein

FIG. 6 is a schematic view of the situation following FIG. 5;

FIG. 7 is a schematic view of the situation following FIG. 6;

FIG. 8 is a schematic view of the situation following FIG. 7;

FIG. 9 is a schematic view of the situation following FIG. 8;

FIG. 10 is a diagram of a resistive memory device according to a third embodiment of the present invention.

Description of the main elements

10 dielectric layer

20 first electrode

30 first metal oxide layer

40 multilayer insulator structure

41 first layer

42 second layer

43 third layer

50 second metal oxide layer

60 second electrode

91 first manufacturing process

92 second manufacturing process

93 third process

101 resistive memory device

102 resistive memory device

103 resistive memory device

CF conductive filament

L1 length

L2 length

L3 length

M1 first Metal atom

M2 second metal atom

M3 third Metal atom

M4 fourth metal atom

R1 first region

R2 second region

R3 third region

S1 first surface

S2 second surface

T30 thickness

T40 thickness

T41 thickness

T42 thickness

T43 thickness

T50 thickness

In the Z vertical direction

Detailed Description

The following detailed description of the invention has disclosed sufficient detail to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered as illustrative and not restrictive. It will be apparent to persons skilled in the relevant art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.

Before further description of the various embodiments, specific terminology used throughout the following description is set forth.

The meaning of the terms "on …", "above …" and "above …" should be read in the broadest manner such that "on …" means not only "directly on" something but also includes the meaning of being on something with other intervening features or layers in between, and "above …" or "above …" means not only "above" or "over" something, but may also include the meaning of being "above" or "over" something with no other intervening features or layers in between (i.e., directly on something).

Ordinal numbers such as "first," "second," and the like, used in the specification and the claims to modify a claim element are not by itself intended to imply any previous ordinal number with respect to the claim element, nor the order in which a claim element is ordered to another claim element or a method of manufacture, and are used solely to distinguish one claim element having a certain name from another claim element having a same name, unless otherwise specifically stated.

The term "forming" or "disposing" is used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a resistive memory device 101 according to a first embodiment of the invention. As shown in fig. 1, the resistive memory device 101 includes a first electrode 20, a second electrode 60, a first metal oxide layer 30, and a second metal oxide layer 50. The first electrode 20 and the second electrode 60 are disposed correspondingly in a vertical direction Z, and the first metal oxide layer 30 and the second metal oxide layer 50 are disposed between the first electrode 20 and the second electrode 60 in the vertical direction Z. In some embodiments, the first metal oxide layer 30 and the second metal oxide layer 50 can be regarded as a switching medium (switching medium) in the resistive memory device 101, and the resistance value of the resistive memory device 101 can be changed by applying a suitable voltage to the first electrode 20 or/and the second electrode 60, so that the resistive memory device 101 can be switched between a High Resistance State (HRS) and a Low Resistance State (LRS), thereby implementing the operation modes of the memory device such as data storage, data reading, and resetting.

In some embodiments, the first electrode 20, the first metal oxide layer 30, the second metal oxide layer 50, and the second electrode 60 may be sequentially stacked in the vertical direction Z, so that the lower surface of the first metal oxide layer 30 may directly contact the first electrode 20, the upper surface of the first metal oxide layer 30 may directly contact the lower surface of the second metal oxide layer 50, and the upper surface of the second metal oxide layer 50 may directly contact the second electrode 60, but not limited thereto. In addition, the material composition of the first metal oxide layer 30 may be different from that of the second metal oxide layer 50. For example, the first metal oxide layer 30 may include a plurality of first metal atoms M1, the second metal oxide layer 50 may include a plurality of second metal atoms M2, and the first metal atoms M1 may be different from the second metal atoms M2. In some embodiments, the first metal oxide layer 30 may include a composition of formula B_zO_tWherein B represents the first metal atom M1, O represents an oxygen atom, and z and t represent the atomic number of the first metal atom M1 and the oxygen atom in the chemical formula of the metal oxide, respectively, but not limited thereto. Furthermore, in some embodiments, the second metal oxide layer 50 may include a chemical formula of A_xO_yWherein a represents the second metal atom M2, O represents an oxygen atom, and x and y represent the number of atoms of the second metal atom M2 and the oxygen atom in the chemical formula of the metal oxide, respectively, but not limited thereto.

In some embodiments, the first metal oxide layer 30 may be substantially the oxide of the first metal atom M1 (e.g., B1 described above), except for the influence of diffusion near the interface where the first metal oxide layer 30 and the second metal oxide layer 50 contact each other_zO_t) And the second metal oxide layer 50 may be substantially all of the second metalOxide of atom M2 (e.g. A as described above)_xO_y). In other words, the second metal atom M2 may not be disposed in the first metal oxide layer 30 and the first metal atom M1 may not be disposed in the second metal oxide layer 50, or the second metal atom M2 may not be disposed in a region of the first metal oxide layer 30 occupying 90% or more of its volume and the first metal atom M1 may not be disposed in a region of the second metal oxide layer 50 occupying 90% or more of its volume, but is not limited thereto. In some embodiments, the first metal atom M1 and the second metal atom M2 may include zinc (Zn), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), or other suitable metal atoms. In some embodiments, the first electrode 20 and the second electrode 60 may each comprise a conductive material, such as platinum (Pt), tungsten (W), silver (Ag), copper (Cu), titanium, tantalum, alloys thereof, conductive nitrides thereof, or other suitable conductive materials. In addition, the first electrode 20 and the second electrode 60 can be regarded as an anode or a cathode in the resistive memory device 101, but not limited thereto.

Please refer to fig. 2. Fig. 2 is a schematic diagram illustrating an operation of the resistive memory device according to the first embodiment of the invention. As shown in fig. 2, in some embodiments, a plurality of Conductive Filaments (CF) may be formed in the first metal oxide layer 30 and the second metal oxide layer 50 by applying a suitable voltage to the first electrode 20 or/and the second electrode 60. The conductive path between the first electrode 20 and the second electrode 60 is formed by the conductive filament CF connected to each other, so that the resistive memory device can be changed from a high resistance state to a low resistance state. In some embodiments, the conductive filament may be formed by oxygen vacancies (oxygen vacancies) in the first metal oxide layer 30 and the second metal oxide layer 50, but not limited thereto. In some embodiments, other types of conductive filaments (e.g., conductive filaments formed from metal ions) may be used to achieve the above-described operation.

In some embodiments, the difference between the first metal atoms M1 in the first metal oxide layer 30 and the second metal atoms M2 in the second metal oxide layer 50 results in the difference between the oxygen vacancies generated when the voltage is applied to the first metal oxide layer 30 and the second metal oxide layer 50, which results in the difference between the number or/and distribution of the conductive wires in the first metal oxide layer 30 and the second metal oxide layer 50. For example, when the oxygen vacancies are less likely to be formed in the oxide of the first metal atom M1, the number of the conductive filaments CF formed in the first metal oxide layer 30 is relatively small, so that only point-to-point contact conditions are formed between the conductive filaments CF in the first metal oxide layer 30 and the conductive filaments CF in the second metal oxide layer 50, which are less favorable for controlling the operating voltage or/and the operating current of the resistive memory device and negatively affect the operating performance (e.g., endurance) of the resistive memory device.

The following description mainly details the differences between the embodiments, and the descriptions of the same parts are not repeated herein for the sake of simplicity. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Please refer to fig. 3. Fig. 3 is a schematic diagram of a resistive memory device 102 according to a second embodiment of the invention. As shown in fig. 3, the resistive memory device 102 includes a first electrode 20, a second electrode 60, a first metal oxide layer 30, a second metal oxide layer 50, and a multi-layer insulator structure 40. The first metal oxide layer 30 is disposed between the first electrode 20 and the second electrode 60 in the vertical direction Z. The second metal oxide layer 50 is disposed between the first metal oxide layer 30 and the second electrode 60 in the vertical direction Z. The multilayer insulator structure 40 is disposed between the first metal oxide layer 30 and the second metal oxide layer 50 in the vertical direction Z. The first metal oxide layer 30 includes a plurality of first metal atoms M1, the second metal oxide layer 50 includes a plurality of second metal atoms M2, and the multilayer insulator structure 40 includes a plurality of third metal atoms M3. Each third metal atom M3 is the same as each second metal atom M2, and the atomic percentage (at.%) of the third metal atoms M3 in the multilayer insulator structure 40 gradually changes in the vertical direction Z. By providing the multi-layer insulator structure 40 having the concentration of the third metal atoms M3 gradually changing in the vertical direction Z between the first metal oxide layer 30 and the second metal oxide layer 50, the formation of conductive filaments in the resistive memory device 102 can be adjusted during operation, and thus the related characteristics of the resistive memory device 102 can be improved.

In some embodiments, the multilayer insulator structure 40 may have a first surface S1 and a second surface S2 opposite to each other in the vertical direction Z, the first surface S1 may be directly connected to the first metal oxide layer 30 in contact therewith, and the second surface S2 may be directly connected to the second metal oxide layer 50 in contact therewith, but not limited thereto. In some embodiments, the atomic percentage of the second metal atoms M2 in the second metal oxide layer 50 may be higher than the atomic percentage of the third metal atoms M3 in the multilayer insulator structure 40, and the atomic percentage of the third metal atoms M3 in the multilayer insulator structure 40 may gradually increase from the first surface S1 to the second surface S2. In other words, the atomic percent of the third metal atoms M3 in the regions of the multilayer insulator structure 40 closer to the second metal oxide layer 50 may be higher than the atomic percent of the third metal atoms M3 in the regions of the multilayer insulator structure 40 farther from the second metal oxide layer 50, but the atomic percent of the third metal atoms M3 in each region of the multilayer insulator structure 40 is lower than the atomic percent of the second metal atoms M2 in the second metal oxide layer 50.

In some embodiments, the multilayer insulator structure 40 may include a plurality of metal oxide insulator layers (e.g., a first layer 41, a second layer 42, and a third layer 43 shown in fig. 3) disposed on top of each other in the vertical direction Z. For example, the first layer 41 of the multi-layer insulator structure 40 may be disposed between the second layer 42 of the multi-layer insulator structure 40 and the first metal oxide layer 30 in the vertical direction Z, the third layer 43 of the multi-layer insulator structure 40 may be disposed between the second layer 42 of the multi-layer insulator structure 40 and the second metal oxide layer 50 in the vertical direction Z, the first layer 41 of the multi-layer insulator structure 40 may be in contact with the first metal oxide layer 30 to be directly connected, the second layer 42 of the multi-layer insulator structure 40 may be in direct contact with the first layer 41 and the third layer 43, respectively, and the third layer 43 of the multi-layer insulator structure 40 may be in contact with the second metal oxide layer 50 to be directly connected, but not limited thereto.

In some embodiments, the third metal atoms M3 in the multilayer insulator structure 40 may be distributed among the layers of the multilayer insulator structure 40, and the atomic percentage of the third metal atoms M3 in the multilayer insulator structure 40 may gradually increase from the first surface S1 to the second surface S2 in the vertical direction Z. For example, the atomic percent of third metal atoms M3 in second layer 42 may be higher than the atomic percent of third metal atoms M3 in first layer 41, while the atomic percent of third metal atoms M3 in third layer 43 may be higher than the atomic percent of third metal atoms M3 in second layer 42, and the atomic percent of third metal atoms M3 in second layer 42 may be lower than the atomic percent of second metal atoms M2 in second metal oxide layer 50.

In some embodiments, the multilayer insulator structure 40 may further include a plurality of fourth metal atoms M4, each fourth metal atom M4 may be the same as each first metal atom M1, and the atomic percentage of the first metal atoms M1 in the first metal oxide layer 30 may be higher than the atomic percentage of the fourth metal atoms M4 in the multilayer insulator structure 40. In some embodiments, the fourth metal atoms M4 in the multilayer insulator structure 40 may be distributed among the layers of the multilayer insulator structure 40, and the atomic percentage of the fourth metal atoms M4 in the multilayer insulator structure 40 may gradually decrease from the first surface S1 to the second surface S2 in the vertical direction Z. For example, the atomic percent of fourth metal atoms M4 in first layer 41 may be higher than the atomic percent of fourth metal atoms M4 in second layer 42, while the atomic percent of fourth metal atoms M4 in second layer 42 may be higher than the atomic percent of fourth metal atoms M4 in third layer 43, and the atomic percent of fourth metal atoms M4 in first layer 41 may be lower than the atomic percent of first metal atoms M1 in first metal oxide layer 30. In other words, in some embodiments, each layer (e.g., the first layer 41, the second layer 42, and the third layer 43) of the multi-layer insulator structure 40 may include a metal oxide layer composed of the third metal element M3 and the fourth metal element M4, respectively, but the atomic percentages of the third metal element M3 and the fourth metal element M4 in each layer may not be the same. In some embodiments, the multilayer insulator structure 40 may be formed from only two metal oxide insulator layers (e.g., the first layer 41 and the second layer 42 described above) or may be formed from more than four metal oxide insulator layers.

In some embodiments, first layer 41 of multilayer insulator structure 40 may comprise a chemical formula of A_x-x1B_x1O_y1The second layer 42 of the multi-layer insulator structure 40 may comprise a metal oxide of the formula a_x-x2B_x2O_y2The third layer 43 of the multi-layer insulator structure 40 may comprise a metal oxide of formula a_x-x3B_x3O_y3The first metal oxide layer 30 may include a metal oxide of the formula B_zO_tAnd the second metal oxide layer 50 may include a metal oxide of the formula a_xO_yBut not limited thereto. In the above chemical formulas, A represents the above second metal atom M2 or third metal atom M3, B represents the above first metal atom M1 or fourth metal atom M4, and O represents an oxygen atom. In addition, x1 and y1 represent the atomic number of the fourth metal atom M4 and the oxygen atom in the chemical formula of the metal oxide in the first layer 41 of the multilayer insulator structure 40, respectively, and x-x1 is the atomic number of the third metal atom M3 in the chemical formula of the metal oxide in the first layer 41 of the multilayer insulator structure 40; x2 and y2 represent the atomic number of the fourth metal atom M4 and the oxygen atom in the chemical formula of the metal oxide in the second layer 42 of the multi-layer insulator structure 40, respectively, and x-x2 is the atomic number of the third metal atom M3 in the chemical formula of the metal oxide in the second layer 42 of the multi-layer insulator structure 40; x3 and y3 represent the atomic number of the fourth metal atom M4 and the oxygen atom in the chemical formula of the metal oxide in the third layer 43 of the multi-layer insulator structure 40, respectively, and x-x3 represents the atomic number of the third metal atom M3 in the chemical formula of the metal oxide in the third layer 43 of the multi-layer insulator structure 40. In some embodiments, x1 can be greater than x2, and x2 can be greater than x3, so x-x1 can be less than x-x2, and x-x2 can be greater than x3Less than x-x3, and y1, y2, y3, and y may be equal to each other, but not limited thereto. In some embodiments, at least two of y1, y2, y3, and y may be unequal to each other, as desired by design.

In some embodiments, the first layer 41 of the multi-layer insulator structure 40 may be substantially all of the formula a, except for the effects that may be caused by diffusion effects near the interface where the first metal oxide layer 30, the first layer 41, the second layer 42, the third layer of the multi-layer insulator structure 40, and the second metal oxide layer 50 contact each other_x-x1B_x1O_y1The second layer 42 of the multi-layer insulator structure 40 may be substantially all of the formula a_x-x2B_x2O_y2And the third layer 43 of the multi-layer insulator structure 40 may be substantially all of the formula a_x-x3B_x3O_y3The metal oxide of (1). For example, the atomic percentages of the third metal atom M3 and the fourth metal atom M4 in the first layer 41 (e.g., in the chemical formula A)_x-x1B_x1O_y1Atomic percent of) may be present in a first region R1 in the first layer 41, the atomic percent of the third metal atom M3 and the fourth metal atom M4 in the second layer 42 (e.g., in formula a)_x-x2B_x2O_y2Atomic percent of (a) may be present in a second region R2 in second layer 42, and the atomic percent of third metal atoms M3 and fourth metal atoms M4 in third layer 43 (e.g., in formula a)_x-x3B_x3O_y3Atomic percent of (a) may be present in a third region R3 in the third layer 43, and the first region R1, the second region R2, and the third region R3 may not be directly connected, but not limited thereto. In some embodiments, the compound has the formula A_x-x1B_x1O_y1May be uniformly distributed in the first region R1 of the first layer 41 and has a chemical formula a_x-x2B_x2O_y2May be uniformly distributed in the second region R2 of the second layer 42 and has the chemical formula a_x-x3B_x3O_y3May be uniformly distributed in the second region R3 of the third layer 43,but not limited thereto. In some embodiments, the length L1 of the first region R1 in the vertical direction Z may be greater than or equal to 90% of the thickness T41 of the first layer 41 in the vertical direction Z, the length L2 of the second region R2 in the vertical direction Z may be greater than or equal to 90% of the thickness T42 of the second layer 42 in the vertical direction Z, and the length L3 of the third region R3 in the vertical direction Z may be greater than or equal to 90% of the thickness T43 of the third layer 43 in the vertical direction Z, but not limited thereto.

In addition, in some embodiments, the thickness T40 of the multilayer insulator structure 40 in the vertical direction Z may be greater than the thickness T30 of the first metal oxide layer 30 in the vertical direction Z and the thickness T50 of the second metal oxide layer 50 in the vertical direction Z, the thickness T41, the thickness T42 and the thickness T43 may be greater than or equal to the thickness T30 and the thickness T50, respectively, and the length L1, the length L2 and the length L3 may also be greater than or equal to the thickness T30 and the thickness T50, respectively, but not limited thereto. It should be noted that the atomic percentages of the above elements in each layer can be measured by using an Energy Dispersive Spectrometer (EDS) or other suitable analysis method or/and analysis instrument. In addition, the resistive memory device of the present invention may include a variable resistive random access memory (ReRAM) or other types of resistive memories.

Please refer to fig. 4. Fig. 4 is a schematic diagram illustrating an operation of a resistive memory device according to a second embodiment of the invention. As shown in fig. 4, in some embodiments, by disposing the multi-layer insulator structure 40 having the concentration of the third metal atoms M3 and the concentration of the fourth metal atoms M4 gradually changing in the vertical direction Z between the first metal oxide layer 30 and the second metal oxide layer 50, the distribution of the conductive wires CF formed during operation can be in a triangular or funnel-shaped distribution, so as to improve the related characteristics of the resistive memory device 102, such as the control of the operating voltage or/and the operating current of the resistive memory device and the related operation performance (e.g., endurance) thereof, but not limited thereto.

Please refer to fig. 5 to 9. Fig. 5 to 9 are schematic diagrams illustrating a method for manufacturing a resistive memory device according to an embodiment of the invention, wherein fig. 6 is a schematic diagram illustrating a situation after fig. 5, fig. 7 is a schematic diagram illustrating a situation after fig. 6, fig. 8 is a schematic diagram illustrating a situation after fig. 7, and fig. 9 is a schematic diagram illustrating a situation after fig. 8. As shown in fig. 9, the method for manufacturing the resistive memory device 102 may include the following steps. First, the first electrode 20 is formed. A first metal oxide layer 30 is formed on the first electrode 20. The first metal oxide layer 30 includes a plurality of first metal atoms M1. A multi-layer insulator structure 40 is formed on the first metal oxide layer 30. A second metal oxide layer 50 is formed on the multilayer insulator structure 40. The second metal oxide layer 50 includes a plurality of second metal atoms M2, the multilayer insulator structure 40 includes a plurality of third metal atoms M3, and each third metal atom M3 is the same as each second metal atom M2. A second electrode 60 is formed on the second metal oxide layer 50. The multilayer insulator structure 40 is disposed between the first metal oxide layer 30 and the second metal oxide layer 50 in the vertical direction Z, and the atomic percentage of the third metal atoms M3 in the multilayer insulator structure 40 gradually changes in the vertical direction Z.

Further, the manufacturing method of the present embodiment may include, but is not limited to, the following steps. First, as shown in fig. 5, a first electrode 20, a first metal oxide layer 30 and a first layer 41 of a multi-layer insulator structure 40 are sequentially formed on a dielectric layer 10. In some embodiments, the dielectric layer 10 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and the dielectric layer 10 may be formed on a substrate (not shown), which may include a semiconductor substrate such as a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or other suitable substrate, but is not limited thereto. In addition, before the first electrode 20 is formed, devices (such as transistors) or/and circuits (not shown) may be formed on the substrate, and the first electrode 20 may be electrically connected to the devices or/and circuits on the substrate through a conductive structure (not shown) in the dielectric layer 10. In some embodiments, the method for fabricating the resistive memory device may be integrated with a back end of line (BEOL) fabrication process in a semiconductor fabrication process, but is not limited thereto.

In some embodiments, the first layer 41 of the multilayer insulator structure 40 can be formed on the first metal oxide layer 30 by a first fabrication process 91, and the first fabrication process 91 can include a deposition process such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, or other suitable film formation processes. The first metal oxide layer 30 and the first electrode 20 may be formed by a suitable film formation process, but the first process 91 for forming the first layer 41 of the multilayer insulator structure 40 and/or the conditions (e.g., reactants, targets, etc.) of the first process 91 may be different from the film formation process for forming the first metal oxide layer 30 and/or the conditions of the film formation process.

Then, as shown in fig. 5-6, the second layer 42 of the multi-layer insulator structure 40 is formed on the first layer 41 of the multi-layer insulator structure 40, and the second layer 42 of the multi-layer insulator structure 40 can be formed on the first layer 41 of the multi-layer insulator structure 40 by a second fabrication process 92, wherein the second fabrication process 92 is performed after the first fabrication process 91. Thereafter, as shown in fig. 6-7, the third layer 43 of the multi-layer insulator structure 40 is formed on the second layer 42 of the multi-layer insulator structure 40, and the third layer 43 of the multi-layer insulator structure 40 can be formed on the second layer 42 of the multi-layer insulator structure 40 by a third fabrication process 93, and the third fabrication process 93 is performed after the second fabrication process 92. In other words, each layer in the multilayer insulator structure 40 may be formed using a corresponding film formation fabrication process. In some embodiments, the first manufacturing process 91, the second manufacturing process 92, and the third manufacturing process 93 in fig. 5 to 7 may be the same type of manufacturing process, and the first layer 41, the second layer 42, and the third layer 43 with different composition ratios may be obtained by adjusting the manufacturing process conditions. In some embodiments, the second and third fabrication processes 92 and 93 may each include a deposition process such as a CVD process, a PVD process, an ALD process, or other suitable film formation processes.

Then, as shown in fig. 8, a second metal oxide layer 50 and a second electrode 60 are sequentially formed on the multi-layered insulator structure 40. In other words, the multilayer insulator structure 40 may be formed before the second metal oxide layer 50, and the multilayer insulator structure 40 is not an interface layer formed between the first metal oxide layer 30 and the second metal oxide layer 50 by diffusion. Thereafter, as shown in fig. 8 to 9, a patterning process may be performed on the second electrode 60, the second metal oxide layer 50, the multi-layer insulator structure 40, the first metal oxide layer 30 and the first electrode 20 to form a resistive memory device 102 on the dielectric layer 10. In some embodiments, the second electrode 60, the second metal oxide layer 50, the multi-layer insulator structure 40, the first metal oxide layer 30, and the first electrode 20 may also be patterned by different patterning processes according to design requirements, and the patterning process corresponding to each layer may also be performed before forming other material layers on the layer, but not limited thereto.

Please refer to fig. 10. Fig. 10 is a schematic diagram of a resistive memory device 103 according to a third embodiment of the invention. As shown in fig. 10, in the resistive memory device 103, the first layer 41 of the multi-layer insulator structure 40 may directly contact the first metal oxide layer 30, and the second layer 42 of the multi-layer insulator structure 40 may directly contact the second metal oxide layer 50. In other words, the multi-layered insulator structure 40 may be formed of only two metal oxide insulator layers, and the multi-layered insulator structure 40 in this case may also achieve an operational effect similar to that shown in fig. 4 described above.

In summary, in the resistive memory device and the method for fabricating the same of the present invention, the distribution of the conductive wires during the operation of the resistive memory device can be adjusted by disposing the multi-layered insulator structure with gradually changing metal atom concentration between two different metal oxide layers, thereby improving the related characteristics of the resistive memory device.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.