阅读说明：本技术 任意波形产生器验证平台 (Arbitrary waveform generator verification platform ) 是由 蔡水河 余承君 于 2021-10-13 设计创作，主要内容包括：本发明涉及测试技术领域,公开了一种任意波形产生器验证平台,用于检测一待测物,包含一主机、一任意波形产生器、一测试环境、一示波器以及一波形资料库。该任意波形产生器耦接于该主机,用来根据该主机产生的一第一控制讯号,产生多个输入波形。该测试环境耦接于该任意波形产生器,用来接收该多个输入波形。该待测物安装于该测试环境中,用来根据该多个输入波形和该主机产生的一第二控制讯号,产生多个输出波形。该示波器耦接于该测试环境和该主机,用来根据该主机产生的一第三控制讯号,测量该多个输出波形。该波形资料库耦接于该主机,用来储存该多个输出波形。本发明可以来协助IC设计商进行更准确、全面的检测及故障分析。(The invention relates to the technical field of testing, and discloses an arbitrary waveform generator verification platform which is used for detecting an object to be tested and comprises a host, an arbitrary waveform generator, a testing environment, an oscilloscope and a waveform database. The arbitrary waveform generator is coupled to the host and used for generating a plurality of input waveforms according to a first control signal generated by the host. The test environment is coupled to the arbitrary waveform generator for receiving the plurality of input waveforms. The object to be tested is arranged in the test environment and used for generating a plurality of output waveforms according to the plurality of input waveforms and a second control signal generated by the host. The oscilloscope is coupled to the test environment and the host, and is used for measuring the output waveforms according to a third control signal generated by the host. The waveform database is coupled to the host and used for storing the output waveforms. The invention can assist IC designers to carry out more accurate and comprehensive detection and fault analysis.)

1. An arbitrary waveform generator verification platform for detecting an object to be tested, comprising:

a host computer, for generating a first control signal, a second control signal and a third control signal according to a command;

an arbitrary waveform generator, coupled to the host, for generating a plurality of input waveforms according to the first control signal;

a test environment, coupled to the arbitrary waveform generator and the host, for receiving the plurality of input waveforms and the second control signal; the object to be tested is arranged in the test environment and generates a plurality of output waveforms according to the plurality of input waveforms and the second control signal;

an oscilloscope, coupled to the test environment and the host, for measuring the output waveforms according to the third control signal; and

and the waveform database is coupled with the host and used for storing the output waveforms.

2. The arbitrary waveform generator validation platform of claim 1,

the host is also used for generating the first control signal according to at least one configuration parameter;

the arbitrary waveform generator is further used for generating a plurality of test waveforms corresponding to the at least one configuration parameter according to the first control signal;

The oscilloscope is further used for measuring the plurality of test waveforms; and

the waveform database is further used for storing the at least one configuration parameter and the plurality of test waveforms.

3. The arbitrary waveform generator validation platform of claim 2,

the waveform database is further used for storing the plurality of test waveforms into a plurality of simulation waveforms;

the host is further used for acquiring the plurality of simulation waveforms from the waveform database according to the at least one configuration parameter;

the host is also used for inputting the analog waveforms to an analog circuit to generate an analog result; and

the waveform database is further used for storing the simulation circuit and the simulation result.

4. The arbitrary waveform generator verification platform of claim 3 wherein the waveform repository stores the plurality of simulated waveforms as comma separated value files.

5. The arbitrary waveform generator validation platform of claim 3, wherein the host is further to: acquiring the plurality of simulation waveforms and the simulation result from the waveform database according to the at least one configuration parameter; inputting the plurality of analog waveforms to the test environment; controlling the object to be tested to generate a plurality of output waveforms according to the plurality of analog waveforms; controlling the oscilloscope to measure the plurality of output waveforms respectively; and verifying the output waveforms according to the simulation result to generate a verification result.

6. The arbitrary waveform generator validation platform of claim 1, wherein the host is further configured to wire to the arbitrary waveform generator, the test environment, and the oscilloscope; the arbitrary waveform generator is also used for transmitting a first connection code to the host computer so as to confirm the successful connection; the test environment is also used for transmitting a second connection code to the host computer so as to confirm the connection success; and the oscilloscope is also used for transmitting a third connection code to the host computer to confirm the successful connection.

7. The arbitrary waveform generator validation platform according to any of claims 1-6, wherein the host comprises:

a user interface for receiving the instruction and at least one configuration parameter; and

a processor, coupled to the user interface, the waveform database, the arbitrary waveform generator, the test environment, and the oscilloscope, for performing operations of the host.

8. The arbitrary waveform generator verification platform of claim 2 wherein the at least one configuration parameter comprises at least one of a format, an amplitude, a dc offset value, and a differential offset value indicative of a configuration voltage of at least one of the plurality of input waveforms.

9. The arbitrary waveform generator verification platform of claim 2 wherein the at least one configuration parameter comprises at least one of a fine tuning delay, a process delay, a carrier scale, a sampling rate, a base band sampling rate, and a carrier frequency, for indicating a configuration timing of at least one of the plurality of input waveforms.

10. The arbitrary waveform generator verification platform of claim 1 wherein the test environment is an on-board wafer environment and the object under test is a wafer or an integrated circuit.

Technical Field

The invention relates to the technical field of testing, in particular to an arbitrary waveform generator verification platform.

Background

The IC manufacturing process is to design the Circuit by software program and simulate the IC performance, and to produce and manufacture the IC by the upstream semiconductor manufacturer and then to ship the IC to the downstream system manufacturer for system integration under the condition of confirming the IC performance to be expected. However, the simulated environment provided by the circuit design software is relatively simple and may not reflect the actual environment faithfully, so the manufactured IC needs to be further integrated into a circuit device or system to observe the actual IC performance. Taking the display device and the driver IC thereof as an example, even if the design specifications are confirmed before the driver IC is shipped, there may be unknown (or known but neglected) influence factors in the environment of the display device, resulting in the problem that the driver IC performs less than expected and has poor compatibility.

Failure Analysis (Failure Analysis) is an Analysis of the root cause of IC Failure that is not expected to be due to environmental influences, design defects in the IC itself, semiconductor process variations, or a combination thereof.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the method aims to solve the technical problem that detection is inaccurate due to incomplete consideration of a method for performing simulation test on an IC through software in the prior art. The invention provides a verification platform to assist IC designers in more accurate and comprehensive detection and fault analysis.

The technical scheme adopted by the invention for solving the technical problems is as follows: an arbitrary waveform generator verification platform for detecting an object to be detected comprises a host computer for generating a first control signal, a second control signal and a third control signal according to an instruction; an arbitrary waveform generator, coupled to the host, for generating a plurality of input waveforms according to the first control signal; a test environment, coupled to the arbitrary waveform generator and the host, for receiving the plurality of input waveforms and the second control signal; the object to be tested is arranged in the test environment and generates a plurality of output waveforms according to the plurality of input waveforms and the second control signal; an oscilloscope, coupled to the test environment and the host, for measuring the output waveforms according to the third control signal; and a waveform database, coupled to the host, for storing the plurality of output waveforms.

Further, the host is further configured to generate the first control signal according to at least one configuration parameter; the arbitrary waveform generator is further used for generating a plurality of test waveforms corresponding to the at least one configuration parameter according to the first control signal; the oscilloscope is further used for measuring the plurality of test waveforms; and the waveform database is further used for storing the at least one configuration parameter and the plurality of test waveforms.

Further, the waveform database is further used for storing the plurality of test waveforms as a plurality of simulation waveforms; the host is further used for acquiring the plurality of simulation waveforms from the waveform database according to the at least one configuration parameter; the host is also used for inputting the analog waveforms to an analog circuit to generate an analog result; and the waveform database is also used for storing the simulation circuit and the simulation result.

Further, the waveform database stores the plurality of analog waveforms as comma-separated value files.

Further, the host is further configured to: acquiring the plurality of simulation waveforms and the simulation result from the waveform database according to the at least one configuration parameter; inputting the plurality of analog waveforms to the test environment; controlling the object to be tested to generate a plurality of output waveforms according to the plurality of analog waveforms; controlling the oscilloscope to measure the plurality of output waveforms respectively; and verifying the output waveforms according to the simulation result to generate a verification result.

Further, the host is also used for connecting the arbitrary waveform generator, the test environment and the oscilloscope; the arbitrary waveform generator is also used for transmitting a first connection code to the host computer so as to confirm the successful connection; the test environment is also used for transmitting a second connection code to the host computer so as to confirm the connection success; and the oscilloscope is also used for transmitting a third connection code to the host computer to confirm the successful connection.

Further, the host includes:

a user interface for receiving the instruction and the at least one configuration parameter; and

a processor, coupled to the user interface, the waveform database, the arbitrary waveform generator, the test environment, and the oscilloscope, for performing operations of the host.

Further, the at least one configuration parameter includes at least one of a format, an amplitude, a dc offset value, and a differential offset value, which is indicative of a configuration voltage of at least one of the plurality of input waveforms.

Further, the at least one configuration parameter includes at least one of a fine delay, a process delay, a carrier scale, a sampling rate, a base-band sampling rate, and a carrier frequency, for indicating a configuration timing of at least one of the plurality of input waveforms.

Further, the test environment is an on-board wafer environment, and the object under test is a wafer or an integrated circuit.

The invention has the following beneficial effects:

compared with the prior art, the verification platform for the arbitrary waveform generator can realize the following steps: (1) establishing a waveform database; (2) establishing an analog circuit and an analog result; and (3) verifying the simulation result. First, the purpose of creating a waveform library is to provide a plurality of input waveforms and a plurality of simulated waveforms that are approximately present in a real environment, thereby simulating the real environment of the display device. Second, the purpose of building analog circuits and simulation results is to provide IC designers with materials for failure analysis and design improvement, thereby providing solutions and suggestions for driving IC performance issues that are not as expected and have poor compatibility. Finally, the purpose of verifying the simulation result is to confirm that the performance of the driver IC meets expectations and to truly solve the problem of poor compatibility; that is, if the simulation result can be repeatedly verified, it can be reasonably inferred that the system Failure (Systematic Failure) of the display device and the driving IC has been actually solved, thereby eliminating the Individual Failure (industrial Failure) caused by the variation of the semiconductor process.

Drawings

The invention is further illustrated with reference to the following figures and examples.

FIG. 1 is a functional block diagram of an arbitrary waveform generator verification platform according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of an output channel setting interface of an arbitrary waveform generator according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an input waveform interface according to an embodiment of the invention.

FIG. 4 is a schematic diagram of waveforms measured by an oscilloscope according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating a process of creating a waveform database according to an embodiment of the invention.

FIG. 6 is a flow chart of a process for establishing a simulation circuit and simulation results according to an embodiment of the present invention.

FIG. 7 is a flow chart of a process of verifying simulation results according to an embodiment of the invention.

FIG. 8 is a loop diagram of an operational verification platform according to an embodiment of the present invention.

In the figure:

1: verification platform for arbitrary waveform generator

10 main unit

11 user interface

12, processor

13 waveform database

Arbitrary waveform generator

15 testing environment

16 object to be measured

17 oscilloscope

AC/AC amplifier

AMP _ O1: output channel one

AMP _ O2: output channel two

DIR _ O1: output channel three

DIR _ O2 output channel four

AWG _ CTR: a first control signal

COB _ CTR: the second control signal

OSC _ CTR third control signal

CONF configuration parameters

CMD instruction

DC-DC amplifier

IC-SIM analog circuit

RST _ SIM simulation results

RST verification result

W _ IN input waveform

W _ OUT output waveform

W _ SIM-analog waveform

W _ TEST TEST waveform.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.

As shown in fig. 1, the arbitrary waveform generator verification platform 1 for detecting an object under test 16 includes a host computer 10, a waveform database 13, an arbitrary waveform generator 14, a test environment 15 and an oscilloscope 17. The host 10 is configured to generate a first control signal AWG _ CTR, a second control signal COB _ CTR, and a third control signal OSC _ CTR according to a command CMD. The arbitrary waveform generator 14 is coupled to the host 10 and configured to generate a plurality of input waveforms W _ IN according to the first control signal AWG _ CTR. The test environment 15 is coupled to the arbitrary waveform generator 14 and the host 10, and is configured to receive a plurality of input waveforms W _ IN and a second control signal COB _ CTR. The dut 16 is installed IN the testing environment 15 and generates a plurality of output waveforms W _ OUT according to the input waveforms W _ IN and the second control signal COB _ CTR. The oscilloscope 17 is coupled to the test environment 15 and the host 10, and is configured to measure a plurality of output waveforms W _ OUT according to a third control signal OSC _ CTR. The waveform database 13 is coupled to the host 10 for storing a plurality of output waveforms W _ OUT. The host 10 includes a user interface 11 and a processor 12. The user interface 11 is adapted to receive a command CMD and at least one configuration parameter CONF. The processor 12 is coupled to the user interface 11, the waveform database 13, the arbitrary waveform generator 14, the test environment 15 and the oscilloscope 17, and is configured to perform operations of the host computer 10. In one embodiment, the waveform database 13 may be a memory integrated within the host 10. In one embodiment, the user interface 11 may be a peripheral input/output interface of a computer, such as but not limited to at least one of a screen, a keyboard, and a mouse.

In one embodiment, the testing environment 15 is a Chip On Board (COB) environment, and the dut 16 is a Chip or an Integrated Circuit (IC). The object under test 16 is, for example, but not limited to, a driver chip for a display device, and the on-board chip environment is used to simulate the environment of the display device.

In one embodiment, the host 10 is further configured to generate a first control signal AWG _ CTR according to at least one configuration parameter CONF; the arbitrary waveform generator 14 is further configured to generate a plurality of TEST waveforms W _ TEST corresponding to at least one configuration parameter CONF according to the first control signal AWG _ CTR; the oscilloscope 17 is also used to measure a plurality of TEST waveforms W _ TEST; and the waveform database 13 is further configured to store at least one configuration parameter CONF and a plurality of TEST waveforms W _ TEST. Through the above operations, the arbitrary waveform generator verification platform 1 can establish and store a plurality of TEST waveforms W _ TEST with arbitrary waveforms in the waveform database 13, and the IC designer can input at least one configuration parameter CONF through the user interface 11 to obtain a plurality of TEST waveforms W _ TEST with arbitrary waveforms stored in the waveform database 13 for the IC designer to research and develop the IC.

As shown IN fig. 2, IN the present embodiment, the at least one configuration parameter CONF includes at least one of a mode, a format, an amplitude, a dc offset value and a differential offset value, which is used to indicate a configuration voltage of one of the output waveforms (i.e. the TEST waveform W _ TEST or the input waveform W _ IN of fig. 1) of the arbitrary waveform generator 14. In the present embodiment, the at least one configuration parameter CONF includes at least one of a Fine Delay (Fine Delay), a Course Delay (Course Delay), a Carrier Scale (Carrier Scale), a sampling rate, a baseband sampling rate, and a Carrier frequency, which is used to indicate a configuration timing of one of the plurality of output waveforms of the arbitrary waveform generator 14.

IN practical applications, an IC designer may set at least one configuration parameter CONF, i.e., set an output waveform (i.e., the TEST waveform W _ TEST or the input waveform W _ IN of fig. 1) of an output channel of the arbitrary waveform generator 14, through the user interface 11 (shown IN fig. 1). For example, the IC designer may set the voltage-related configuration parameters CONF through the user interface 11: the mode is 14 bits, the format is Non Return to Zero (NRZ) or Return to Zero (RZ), the amplitude is 300.0 millivolts (mV), the voltage offset is 500.0 millivolts, the differential offset is 0 volts, the original (Direct) or internal (Interpolation) value is used, the terminal voltage is 0 volts, and the AC amplifier AC output, the DC amplifier DC output, or the short circuit output is selected. The IC designer can set the timing-related configuration parameters CONF through the user interface 11: the fine delay is 0 picoseconds (picosecond), the process delay is 0 picoseconds, the carrier scale is 1, the sampling rate is 8 gigasamples per second (GSa/s), the base band sampling rate is 8 gigasamples per second, and the carrier frequency is 2 gigahertz (GHz). Also, the IC designer can select one of the output channels AMP _ O1, AMP _ O2, DIR _ O1 and DIR _ O2 included IN the arbitrary waveform generator 14 through the user interface 11 to output the set output waveform (i.e., the TEST waveform W _ TEST or the input waveform W _ IN of FIG. 1).

Taking a driving IC for a display device as an example, an IC designer may set a Common Mode Voltage (VCM) magnitude, a Voltage of Input Differential Signals (VID) magnitude, a spreading ratio of a high-speed signal, Inter Symbol Interference (ISI), and the like through the user interface 11. In this way, the arbitrary waveform generator 14 can generate an arbitrary waveform that the driver IC encounters in the display device, thereby simulating the environment in the display device.

As shown in fig. 3, in the present embodiment, the waveform database 13 is further configured to store a plurality of TEST waveforms W _ TEST as a plurality of analog waveforms W _ SIM. In one embodiment, the waveform database 13 stores a plurality of analog waveforms W _ SIM as Comma-Separated Values (CSV) files.

In practical applications, the IC designer can convert the analog TEST waveforms W _ TEST into digital analog waveforms W _ SIM through the user interface 11 (shown in FIG. 1) and store the converted waveforms. As shown in FIG. 3, the IC designer can set the file format to CSV and the file path to "C: \" Users \ Test1.CSV "through the user interface 11, and then select the" store to file "button to store the simulated waveform W _ SIM.

In one embodiment, the host 10 is further configured to obtain a plurality of simulated waveforms W _ SIM from the waveform database 13 according to at least one configuration parameter CONF. The host 10 is further configured to input a plurality of analog waveforms W _ SIM to an analog circuit IC _ SIM to generate an analog result RST _ SIM. And the waveform database 13 is also used to store the simulation circuit IC _ SIM and the simulation result RST _ SIM. As shown in FIG. 3, if the simulated waveform W _ SIM already exists in the waveform database 13, the IC designer can browse the waveform database 13 through the user interface 11, select the simulated waveform W _ SIM with the file path "C: \ Users \ Test1. csv", and then select the "transfer to Instrument" button to import the simulated waveform W _ SIM into the simulation circuit IC _ SIM. In one embodiment, the IC designer may select the "send to Instrument" button via the user interface 11 to import the analog waveform W _ SIM into the test environment 15 and the DUT 16, thereby simulating the environment in the display device and the operation of the driver IC.

As shown in fig. 4, the host 10 is further configured to: acquiring a plurality of simulation waveforms W _ SIM and simulation results RST _ SIM from a waveform database 13 according to at least one configuration parameter CONF; inputting a plurality of analog waveforms W _ SIM to a test environment 15; controlling the object to be tested 16 to generate a plurality of output waveforms W _ OUT according to the plurality of analog waveforms W _ SIM; controlling the oscilloscope 17 to measure a plurality of output waveforms W _ OUT respectively; and verifying the output waveforms W _ OUT according to the simulation result RST _ SIM to generate a verification result RST. As shown IN fig. 4, the waveform (input waveform W _ IN or output waveform W _ OUT) measured by the oscilloscope 17 is not a theoretical square wave, and thus is closer to the input waveform W _ IN encountered by the driving IC IN the real environment of the display device or the output waveform W _ OUT actually generated by the driving IC; furthermore, the IC designer may observe the eye pattern measured by the oscilloscope 17, determine whether the input waveform W _ IN or the output waveform W _ OUT meets the expected specification, and further determine whether the IC design needs to be modified or provide modification suggestions to the designer of the display device.

In short, according to the embodiments of fig. 1 to 4, the arbitrary waveform generator verification platform 1 may implement: (1) establishing a waveform database; (2) establishing an analog circuit and an analog result; and (3) verifying the simulation result. First, the waveform library 13 is built IN order to provide a plurality of input waveforms W _ IN and a plurality of simulated waveforms W _ SIM that exist approximately IN the real environment, thereby simulating the real environment of the display device. Secondly, the purpose of building the simulation circuit IC _ SIM and the simulation result RST _ SIM is to provide materials for the IC designer to perform failure analysis and improve the design, thereby providing solutions and suggestions for the problem that the driving IC performs less than expected and has poor compatibility. Finally, the purpose of verifying the simulation result RST _ SIM is to confirm that the performance of the driving IC meets the expectation and can really solve the problem of poor compatibility; that is, if the simulation result RST _ SIM can be repeatedly verified, it can be reasonably inferred that the system Failure (Systematic Failure) of the display device and the driving IC has been actually solved, thereby eliminating the Individual Failure (inductive Failure) caused by the variation of the semiconductor process.

As shown in FIG. 5, the process of creating the waveform database includes the following steps.

Step 51: connecting to any waveform generator, test environment, oscilloscope.

Step 52: and controlling the arbitrary waveform generator to generate a plurality of test waveforms.

Step 53: and controlling the oscilloscope to measure a plurality of test waveforms respectively.

Step 54: a plurality of test waveforms are stored to create a waveform database.

At step 51, the host computer 10 is used to connect to any waveform generator 14, test environment 15 and oscilloscope 17. At step 52, the host 10 is configured to control the arbitrary waveform generator 14 to generate a plurality of TEST waveforms W _ TEST. In step 53, the host computer 10 is configured to control the oscilloscope 17 to measure a plurality of TEST waveforms W _ TEST, respectively. At step 54, the host 10 is used to store a plurality of TEST waveforms W _ TEST to establish the waveform database 13. In one embodiment, between steps 51 and 52, the arbitrary waveform generator 14 is used to transmit a first connection code to the host 10 to confirm the connection is successful; the test environment 15 is used to transmit a second connection code to the host 10 to confirm the connection is successful; and the oscilloscope 17 is used to transmit a third connection code to the host 10 to confirm the connection success. Therefore, through the flow of fig. 5, the purpose of creating a waveform library can be achieved.

As shown in fig. 6, the flow of establishing the analog circuit and the analog result includes the following steps.

Step 61: a plurality of simulation waveforms are obtained from a waveform database according to at least one configuration parameter.

Step 62: a plurality of analog waveforms are input to an analog circuit to produce an analog result.

And step 63: judging whether the simulation result meets the expectation, if not, performing step 64; if so, go to step 65.

Step 64: at least one of the at least one configuration parameter and the analog circuit is adjusted.

Step 65: at least one configuration parameter, a plurality of analog waveforms, an analog circuit and an analog result are stored.

In step 61, the host 10 is configured to obtain a plurality of simulated waveforms W _ SIM from the waveform database 13 according to at least one configuration parameter CONF. At step 62, the host 10 is configured to input a plurality of analog waveforms W _ SIM to the analog circuit IC _ SIM to generate an analog result RST _ SIM. At step 64, the host 10 is configured to adjust at least one of the configuration parameter CONF and the simulation circuit IC _ SIM when the simulation result RST _ SIM is not expected. In step 65, the host 10 is configured to store at least one configuration parameter CONF, a plurality of analog waveforms W _ SIM, an analog circuit IC _ SIM, and an analog result RST _ SIM when the analog result RST _ SIM is expected. Thus, with the flow of fig. 6, the purpose of establishing an analog circuit and an analog result can be achieved.

As shown in fig. 7, the flow of the verification simulation result includes the following steps.

Step 71: according to at least one configuration parameter, a plurality of simulation waveforms are obtained from a waveform database and input to a test environment.

Step 72: and controlling the object to be tested to generate a plurality of output waveforms according to the plurality of analog waveforms.

Step 73: and controlling the oscilloscope to measure a plurality of output waveforms respectively.

Step 74: and verifying the plurality of output waveforms according to the simulation result to generate a verification result.

At step 71, the host computer 10 is configured to obtain a plurality of simulated waveforms W _ SIM from the waveform database 13 and input the waveforms W _ SIM into the test environment 15 according to at least one configuration parameter CONF. At step 72, the host 10 is configured to control the object 16 to generate a plurality of output waveforms W _ OUT according to the plurality of analog waveforms W _ SIM. In step 73, the host computer 10 is configured to control the oscilloscope 17 to measure a plurality of output waveforms W _ OUT, respectively. At step 74, the host 10 is configured to verify the plurality of output waveforms W _ OUT according to the simulation result RST _ SIM to generate a verification result RST. Therefore, the purpose of verifying the simulation result can be achieved by the flow of fig. 7.

As shown in fig. 8, Application Engineering (AE) is directed to the development of circuit devices and ICs, testing and Application of software programs, Application tools, etc. related to the implementation, so as to assist developers and users to operate the circuit devices, ICs and related test instruments and understand the operation status thereof; for example, application engineering can implement the AWG validation platform of the present invention. Failure Analysis (Failure Analysis) is an Analysis of the root cause of circuit device and IC performance that is less than expected in order to understand whether an IC Failure is due to factors in the environment of the circuit device, design defects in the IC itself, semiconductor process variations, or a combination thereof. Research and Development (Research and Development) is the design and improvement of circuit devices and ICs for any possible market demand.

In practical applications, when the IC is shipped to a downstream system vendor for system integration, it is likely that the IC will perform less than expected, and therefore the IC designer will assign the relevant personnel to the field for preliminary failure analysis and debugging (Debug) and collect test data. The collected test data can be imported into an AWG verification platform for the research and development personnel to verify. Through the AWG verification platform, the fault analysis of the IC can be carried out in the environment of a laboratory copy system manufacturer of an IC designer, and further, a solution and a suggestion are provided for the problems that the performance of the IC is not as expected and the compatibility is poor. Furthermore, through the AWG verification platform, the performance of the IC can be verified to meet expectations, and the problem of poor compatibility can be really solved; that is, if the circuit device and IC performance can be repeatedly verified, it can be reasonably inferred that the system failure of the circuit device and IC has indeed been solved, thereby eliminating individual failures due to semiconductor process variations and reducing the risk of mass production. Therefore, the AWG verification platform can form an AE-FA-RD cycle, and assist IC designers to research, develop and improve products so as to accelerate research and development efficiency, improve verification consistency and reduce the risk of mass production.

In summary, the verification platform for the arbitrary waveform generator of the present invention can achieve: (1) establishing a waveform database; (2) establishing an analog circuit and an analog result; and (3) verifying the simulation result. First, the purpose of creating a waveform library is to provide a plurality of input waveforms and a plurality of simulated waveforms that are approximately present in a real environment, thereby simulating the real environment of the display device. Second, the purpose of building analog circuits and simulation results is to provide IC designers with materials for failure analysis and design improvement, thereby providing solutions and suggestions for driving IC performance issues that are not as expected and have poor compatibility. Finally, the purpose of verifying the simulation results is to confirm that the driver IC performs as expected and to reliably solve the problem of poor compatibility.

In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the contents of the specification, and must be determined by the scope of the claims.