阅读说明：本技术 超导集成电路的布局方法 (Layout method of superconducting integrated circuit ) 是由 任洁 辛玲 高小平 王镇 于 2020-04-27 设计创作，主要内容包括：本发明提供一种超导集成电路的布局方法,包括：基于标准单元库建立以器件管脚为数据主体的数据库,数据库包括时序及物理信息；基于数据库进行静态时序分析,得到每个管脚的时序信息；基于各管脚的时序信息及器件的逻辑深度确定各管脚的优先级,对优先级高的管脚进行直连,以构造初始布局结果；基于初始布局结果利用最小通道密度算法检查可布线性,若存在不可布线的通道,将挡住布线的器件移开,留出足够的布线空间后走线；否则直接走线。本发明的超导集成电路的布局方法实现了基于版图的静态时序分析算法,继而利用时序分析结果,考虑电路本身多种物理属性,完成自动布局,节省设计面积,同时布局结果无需额外走线资源。(The invention provides a layout method of a superconducting integrated circuit, which comprises the following steps: establishing a database with device pins as a data main body based on a standard cell library, wherein the database comprises time sequence and physical information; performing static time sequence analysis based on a database to obtain time sequence information of each pin; determining the priority of each pin based on the time sequence information of each pin and the logic depth of the device, and directly connecting the pins with high priority to construct an initial layout result; checking the routability by using a minimum channel density algorithm based on an initial layout result, if a channel which can not be routed exists, removing the device which blocks the routing, and routing after enough routing space is reserved; otherwise, directly routing. The layout method of the superconducting integrated circuit realizes a static time sequence analysis algorithm based on the layout, then utilizes the time sequence analysis result, considers various physical attributes of the circuit, completes automatic layout, saves the design area, and simultaneously does not need additional wiring resources for the layout result.)

1. A layout method of a superconducting integrated circuit, the layout method of the superconducting integrated circuit at least comprising:

1) establishing a database which takes device pins as a data main body based on a standard cell library, wherein the database comprises time sequence and physical information;

2) performing static time sequence analysis based on the database to obtain time sequence information of each pin;

3) determining the priority of each pin based on the time sequence information of each pin and the logic depth of the device, and directly connecting the pins with high priority to construct an initial layout result;

4) checking the routability by using a minimum channel density algorithm based on the initial layout result, and if a channel which can not be routed exists, removing the device which blocks the routing to reserve enough routing space; otherwise, directly executing the next step;

5) and pre-estimating routing by using the wiring space.

2. The layout method of a superconducting integrated circuit according to claim 1, characterized in that: the physical information includes device size and/or pin location.

3. The layout method of a superconducting integrated circuit according to claim 1, characterized in that: the static analysis includes calculating a timing margin of each timing path based on the connection condition of the circuit, thereby obtaining timing information of each pin.

4. The layout method of a superconducting integrated circuit according to claim 3, characterized in that: the smaller the time sequence margin of the pin is, the higher the priority of the corresponding pin is; the deeper the logic depth of the device, the higher the priority of the corresponding pin.

5. The layout method of a superconducting integrated circuit according to claim 4, wherein: and judging the priority of the pin corresponding to the time sequence allowance of the pin being smaller than a first preset value or the logic depth of the device being larger than a second preset value as high.

6. The layout method of a superconducting integrated circuit according to claim 1, characterized in that: the minimum channel density algorithm includes: all wiring channels of the whole chip are divided into unit arrays, all possible wiring channels are estimated according to the layout condition, all the channels through which the estimated wiring passes are guaranteed, the sum of the wiring density is the minimum, and therefore the wiring performance is guaranteed.

7. The layout method of a superconducting integrated circuit according to claim 1, characterized in that: before the device which blocks the wiring is removed in the step 4), the method also comprises the step of optimizing the routability by utilizing various pin distribution positions of the device.

8. The layout method of a superconducting integrated circuit according to claim 1, characterized in that: the wiring is implemented using Josephson transmission lines or active branch elements.

Technical Field

The invention relates to the field of superconducting digital unit design, in particular to a layout method of a superconducting integrated circuit.

Background

The development of CMOS integrated circuits (Electronic Design Automation) has been in the past 50 years, and from school to industry, a layout algorithm can be a mechanical relaxation algorithm from the beginning, and a comprehensive layout algorithm which can simultaneously consider timing, power consumption, wire length and routability can be used at present, so that various performances of a chip are continuously improved. A series of commercial EDA tools such as automatic layout and wiring/static timing sequence analysis designed according to the characteristics of the CMOS integrated circuit greatly promote the high-speed evolution of the integration level of the CMOS integrated circuit, and become an essential ring in the CMOS circuit design.

Because the design rule of the superconducting integrated circuit is greatly different from that of the CMOS circuit, the major difficulty of the superconducting integrated circuit at present is that: a) The method comprises the following steps of a, connecting a plurality of fan-outs, b) not routing metal wiring, c) standard cells are inconsistent in height, 4) most logic gates are checked in sequence, and 5) most standard cells have various pin distribution possibilities, so that a plurality of existing digital CMOS circuit layout algorithms cannot directly meet the requirements of the superconducting integrated circuit, and how to provide a layout algorithm aiming at the superconducting integrated circuit design becomes one of the problems to be solved urgently by technical personnel in the field.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a layout method of a superconducting integrated circuit, which is used to solve the problem of difficult design of the superconducting integrated circuit in the prior art.

To achieve the above and other related objects, the present invention provides a layout method of a superconducting integrated circuit, the layout method at least including:

1) establishing a database which takes device pins as a data main body based on a standard cell library, wherein the database comprises time sequence and physical information;

2) performing static time sequence analysis based on the database to obtain time sequence information of each pin;

3) determining the priority of each pin based on the time sequence information of each pin and the logic depth of the device, and directly connecting the pins with high priority to construct an initial layout result;

4) checking the routability by using a minimum channel density algorithm based on the initial layout result, and if a channel which can not be routed exists, removing the device which blocks the routing to reserve enough routing space; otherwise, directly executing the next step;

5) and pre-estimating routing by using the wiring space.

Optionally, the physical information comprises device size and/or pin location.

More optionally, the static analysis includes calculating a timing margin of each timing path based on the connection condition of the circuit, so as to obtain timing information of each pin.

More optionally, the method for determining the priority of each pin includes: the smaller the time sequence margin of the pin is, the higher the priority of the corresponding pin is; the deeper the logic depth of the device, the higher the priority of the corresponding pin.

More optionally, the priority of the pin corresponding to the timing margin of the pin being smaller than the first preset value or the logic depth of the device being larger than the second preset value is determined as high.

Optionally, the minimum channel density algorithm comprises: all wiring channels of the whole chip are divided into unit arrays, all possible wiring channels are estimated according to the layout condition, all the channels through which the estimated wiring passes are guaranteed, the sum of the wiring density is the minimum, and therefore the wiring performance is guaranteed.

Optionally, before the device blocking the wiring is removed in step 4), a step of optimizing the routability by using various pin distribution positions of the device is further included.

Optionally, the traces are implemented using josephson transmission lines or active branching elements.

As described above, the layout method of the superconducting integrated circuit according to the present invention has the following advantageous effects:

the layout method of the superconducting integrated circuit realizes a static time sequence analysis algorithm based on the layout, then utilizes the time sequence analysis result, considers various physical attributes of the circuit, completes automatic layout, saves the design area, and simultaneously does not need additional wiring resources for the layout result.

Drawings

FIG. 1 is a flow chart showing a layout method of a superconducting integrated circuit according to the present invention.

Description of the element reference numerals

S1-S5

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a layout method of a superconducting integrated circuit, the layout method of the superconducting integrated circuit at least including:

step S1: and establishing a database with device pins as a data main body based on a standard cell library, wherein the database comprises timing sequence and physical information.

Specifically, a database with device pins as a data body is established based on the time sequence and physical model of the standard cell library acquisition unit. The database includes timing and physical information of device pins including but not limited to device dimensions and pin locations, any pin physical information being suitable for use with the present invention.

Step S2: and performing static time sequence analysis based on the database to obtain the time sequence information of each pin.

Specifically, the static time sequence analysis based on the layout is carried out according to the information in the database, and the time sequence allowance of each time sequence path is calculated based on the connection condition of the circuit, so that the time sequence information of each pin is obtained.

Step S3: and determining the priority of each pin based on the time sequence information of each pin and the logic depth of the device, and directly connecting the pins with high priorities to construct an initial layout result.

Specifically, the smaller the timing margin of a pin, the more difficult the corresponding timing control (i.e., the strain of timing), and therefore, the priority of the pin needs to be determined based on the timing margin; the smaller the timing margin of a pin, the higher the priority of the corresponding pin. The logic depth of the device is the depth of the assembly line, the superconducting integrated circuit cannot walk on a metal wire and can only be directly connected by a physical device, and devices related to the assembly line which is closer to the front need to be placed preferentially, so that the priority of the pins needs to be determined based on the logic depth of the devices; the deeper the logic depth of the device, the higher the priority of the corresponding pin.

More specifically, sequencing the time sequence margins corresponding to the pins from small to large, and judging that the priority is high if the time sequence margins are smaller than a first preset value; and sequencing the logic depth of each device from deep to shallow, and judging that the priority of the corresponding pin is high if the logic depth of each device is greater than a second preset value. The first preset value and the second preset value can be set based on actual circuit conditions, which are not described herein.

It should be noted that, the priority may also be determined according to specific situations by combining timing information of each pin and logic depth of the device, including but not limited to considering timing margin and logic depth at the same time, and determining that the priority is high when the timing margin meets a set condition and the logic depth meets the set condition is not described herein, but is not limited to this embodiment.

Step S4: checking the routability by using a minimum channel density algorithm based on the initial layout result, if a channel which can not be routed exists, optimizing the routability by using various pin distribution positions of the device, and then moving away the related device which blocks the routing to reserve a sufficient routing space; otherwise step 5) is performed directly.

Specifically, routability is checked using a minimum channel density algorithm, which includes: all wiring channels of the whole chip are divided into unit arrays, all possible wiring is estimated according to the layout condition, and the minimum sum of wiring density of all estimated wiring channels is ensured. At the moment, the wiring condition can be obtained through the minimum channel density algorithm, if devices or insufficient space exist on the channel, the devices blocking the wiring are moved away, and enough wiring space is reserved; otherwise, directly executing the next step.

As another implementation mode of the invention, before the device for blocking the wiring is removed, the method also comprises the step of adjusting the distribution positions of the pins by utilizing the characteristic that the standard cells of the superconducting integrated circuit have various pin distributions, so as to optimize the routability.

Step S5: and pre-estimating routing by using the wiring space.

Specifically, the wiring is performed using a Josephson Transmission Line (JTL) or an active branch element (Splitter) based on the wiring result of step S4, completing the wiring.

In summary, the present invention provides a layout method of a superconducting integrated circuit, the layout method of the superconducting integrated circuit at least includes: establishing a database which takes device pins as a data main body based on a standard cell library, wherein the database comprises time sequence and physical information; performing static time sequence analysis based on the database to obtain time sequence information of each pin; determining the priority of each pin based on the time sequence information of each pin and the logic depth of the device, and directly connecting the pins with high priority to construct an initial layout result; checking the routability by using a minimum channel density algorithm based on the initial layout result, and if a channel which can not be routed exists, removing the device which blocks the routing to reserve enough routing space; otherwise, directly executing the next step; and pre-estimating routing by using the wiring space. The layout method of the superconducting integrated circuit realizes a static time sequence analysis algorithm based on the layout, then utilizes the time sequence analysis result, considers various physical attributes of the circuit, completes automatic layout, saves the design area, and simultaneously does not need additional wiring resources for the layout result. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.