阅读说明：本技术 一种基于多策略优化的超大规模集成电路多层总体布线方法 (Multi-strategy optimization-based ultra-large-scale integrated circuit multilayer overall wiring method ) 是由 刘耿耿 裴镇宇 郭文忠 郑筱媛 陈国龙 于 2021-06-30 设计创作，主要内容包括：本发明涉及一种基于多策略优化的超大规模集成电路多层总体布线方法,包括步骤S1：在预连接布线阶段,采用虚拟容量的动态调整策略对通道容量进行适当调整缩减；步骤S2：在全局考量下的布线重组阶段找到最拥挤的布线区域,采用布线子区域的自适应扩展策略对其进行自适应扩展,根据布线后的不同拥堵度,对应地调整扩大的范围和扩张速度；步骤S3：在布线时采用虚拟容量的动态调整策略对通道虚拟容量进行动态调整,对不同通道方向上的通道容量进行相互补充,及时补充剩余通道容量较小的布线通道；步骤S4：采用基于A*算法的启发式搜索策略通过A*算法进行启发式搜索和布线。本发明能够提高布线容量的利用率,平衡布线器的布线效率和全局搜索的压力。(The invention relates to a multi-strategy optimization-based VLSI (very large scale integration) multilayer overall wiring method, which comprises the following steps of S1: in the pre-connection wiring stage, a dynamic adjustment strategy of virtual capacity is adopted to properly adjust and reduce the channel capacity; step S2: finding the most crowded wiring area in the wiring recombination stage under the global consideration, adopting a self-adaptive expansion strategy of the wiring sub-area to perform self-adaptive expansion on the wiring sub-area, and correspondingly adjusting the expanded range and the expansion speed according to different congestion degrees after wiring; step S3: during wiring, a dynamic adjustment strategy of virtual capacity is adopted to dynamically adjust the virtual capacity of the channel, the channel capacities in different channel directions are mutually supplemented, and a wiring channel with smaller residual channel capacity is supplemented in time; step S4: and carrying out heuristic search and wiring through the A-algorithm by adopting a heuristic search strategy based on the A-algorithm. The invention can improve the utilization rate of the wiring capacity and balance the wiring efficiency of the wiring device and the pressure of global search.)

1. A multi-strategy optimization based VLSI (very large scale integration) multilayer overall wiring method is characterized by comprising the following steps: the method comprises the following steps:

step S1: in the pre-connection wiring stage, a dynamic adjustment strategy of virtual capacity is adopted to properly adjust and reduce the channel capacity; after a multi-terminal wire mesh is decomposed into a plurality of two-terminal wire meshes through a minimum spanning tree algorithm, the virtual capacity of a wiring channel in the horizontal and vertical directions is reduced to 1/2, and the capacity of the remaining channels in the 45-degree direction and the 135-degree direction is kept unchanged; under the constraint of new channel capacity, directly connecting the simple wire nets with the wire nets at the two ends in an X-structure grid routing mode; the simple wire mesh is a wire segment formed by wire meshes at two ends, and the slope value is 0, -1, +1 or infinity;

step S2: finding the most crowded wiring area in the wiring recombination stage under the global consideration, then adopting a self-adaptive expansion strategy of the wiring sub-area to perform self-adaptive expansion on the wiring sub-area, and correspondingly adjusting the expanded range and the expansion speed according to different congestion degrees after wiring;

step S3: during wiring, a dynamic adjustment strategy of virtual capacity is adopted to dynamically adjust the virtual capacity of the channel, the channel capacities in different channel directions are mutually supplemented, namely the channel capacities in the horizontal direction and the 45-degree direction are dynamically adjusted, and the channel capacities in the vertical direction and the 135-degree direction are dynamically adjusted, so that the residual channel capacities are timely supplemented, namely the wiring channels with small contrast between the horizontal direction and the 45-degree direction and the vertical direction and the 135-degree direction are supplemented;

step S4: and carrying out heuristic search and wiring through the A-algorithm by adopting a heuristic search strategy based on the A-algorithm.

2. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: the step S1 specifically includes the following steps:

step S11: inputting the pin position of each wire net, the channel capacity of a wiring area and a wiring layer corresponding to the pin, namely inputting data given by benchmark;

step S12: judging whether the pin number of the wire net is equal to 2 or not, if so, judging whether the position relation between the two pins meets a right-angle structure or not, if so, connecting the two pins if available wiring resources exist in the wiring area, and if so, continuing to execute the step S13;

step S13: generating an X-structure Steiner tree of each wire net through a particle swarm algorithm;

step S14: decomposing a multi-end wire net into a plurality of two-end wire nets by a minimum spanning tree algorithm, and recording all the two-pin wire nets;

step S15: setting a channel capacity constraint condition of a pre-connection stage, namely reducing the channel capacity in the Manhattan direction in the X structure to a half of the original channel capacity, and keeping the channel capacity in the 45-degree direction and the 135-degree direction unchanged;

step S16: all two-pin nets are pre-connected without violating the set channel capacity constraints.

3. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: in step S3, the mutual complementation of the channel capacities in different channel directions needs to satisfy a constraint condition, where the constraint condition is:

the constraint conditions are shown in formula (1) and formula (2):

d1＝d1+C,d2＝d2-C；d1＜C&&d2＞2C (1)

d1＝d1-C,d2＝d2+C；d1＞2C&&d2＜C (2)

wherein C is a preset channel capacity threshold constant; d1 represents the channel capacity remaining in the horizontal or vertical direction; d2 represents the channel capacity remaining in the 45 degree or 135 degree direction;

as can be seen from the formula, this strategy is triggered only if the remaining channel capacity is less than the threshold and the channel capacity in the other direction is greater than twice the threshold.

4. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: the step S2 specifically includes the following steps:

step S21: searching the most congested wiring unit in the current wiring area;

step S22: self-adaptive expansion is carried out on the most congested wiring subarea, and two unconnected pin nets in the wiring subarea are recorded; the expansion speed of the self-adaptive expansion is determined by the number of the two-pin wire nets in the current wiring area;

step S23: in the expanded wiring subarea, aiming at the unconnected pin nets, a given net in the current subarea is distributed by applying a particle swarm algorithm and an A-x algorithm;

step S24: the steps S22, S23 are repeated until the wiring sub-area is enlarged to the whole overall wiring area.

5. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: the specific contents of finding the most congested routing unit in the current routing area in step S21 are: traversing the whole overall wiring area to find out the most congested wiring unit as a wiring sub-area; in the searching process, comparing the congestion degree of the sub-area selected each time with the congestion degree of the most congested area recorded currently, and if the selected congestion degree is higher, updating the most congested area recorded currently; if the degrees are the same, judging the positions of the two areas in the general wiring area respectively, and selecting the position closer to the center as the most congested area; otherwise, keeping the record unchanged;

judging the congestion degree index of the wiring area, wherein the index is the channel capacity used in the area in an accumulated way; for one wiring unit of the wiring area, calculating the channel capacity of the node in four directions of horizontal direction, 45 degrees, vertical direction and 135 degrees; therefore, the congestion degree calculation manner is as follows:

wherein, N represents the current wiring unit; d (i) represents the number of channel capacity usages of the wiring unit N in the direction i.

6. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: the specific content of the step S22 of performing adaptive expansion on the most congested routing sub-region is:

when the number of the two-pin wire nets in the wiring subarea is less than 50, the size of the extension of the wiring subarea is set to be 3; when the number of the two-pin wire grids in the wiring subarea is more than or equal to 50 and less than 100, the size of the extension of the wiring subarea is set to be 2; when the number of the two-pin wire grids in the wiring subarea is more than or equal to 100 and less than 200, the size of the extension of the wiring subarea is set to be 1.

7. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: in step S23, a particle swarm algorithm is first applied to perform overall optimization, and an extended _ unconnected set is used to store two unconnected pin nets; judging whether the set is empty or not, if so, indicating that the particle swarm algorithm is effectively connected with all the two-pin nets; if not, the particle swarm algorithm cannot effectively connect all the two-pin nets, and the rest two-pin nets continue to be operated by the A-x algorithm.

8. The multi-strategy optimization-based VLSI multi-layer global routing method of claim 1, wherein: in the step S4

The cost function of the a-algorithm is shown in formula (4):

F(x)＝G(x)+H(X) (4)

wherein f (x) represents the final cost estimate from the starting point to the end point through node x in G, (x) represents the actual cost of movement from the starting point to node x in G, and h (x) represents the estimated cost from node x to the end point in G;

taking the Manhattan distance between the starting point with the weight and the current point as the actual cost G (t) of selection, as shown in a formula (5); selecting an X structural path of a current point and a terminal point as a heuristic function H (t), as shown in a formula (6);

wherein w is a weight; stn_xAnd stn_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t; te_xHente_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t;

the specific implementation of the a-algorithm is as follows: using an OPEN table and a CLOSE table; the OPEN table is an OPEN list to be checked and stores the node information needing to be detected in the searching process; the CLOSE table is a closed list that stores nodes that have been added to the shortest path, and these nodes do not need to be paid attention again; when the algorithm starts, two pins of two-end wire nets to be connected are respectively set as a current node and a target node, and the current node is used as a starting point; searching a neighbor node of the current node, and if the neighbor node cannot be reached, namely the path is not feasible, searching a next neighbor node of the current node; if the path is feasible, calculating the F (x) value of the neighbor node and adding the neighbor node into the OPEN table until all the neighbor nodes are searched; deleting the current node from the OPEN table, and putting the current node into a CLOSE table; taking the point with the minimum value of F (x) in the OPEN table as the current node, judging whether the current node is the target node or not, and if not, repeating the searching process; if so, the algorithm stops.

Technical Field

The invention relates to the technical field of computer aided design of integrated circuits, in particular to a multi-strategy optimization-based multi-layer overall wiring method for a very large scale integrated circuit.

Background

Chip design is a delicate and large project around the world, integrating hundreds of billions of "switches" that allow or block the passage of current into a chip that is only the size of a nail cover. From micron level to nanometer level, it is the ultimate for the human being to climb up. In chip design, a very large scale integrated circuit is the key of the design process, and can be used for manufacturing electronic equipment with small volume, light weight, low energy consumption, rich functions and high reliability. While the circuit integration of the initial chip was not high enough to allow developers to manually draw circuits, chips now containing hundreds of millions or even hundreds of billions of transistors still rely on manual drawing, which inevitably leads to many problems and errors. Since 1986, a Design Compiler, an Electronic Design Automation (EDA) tool, was introduced, enabling developers to describe circuits using codes, thereby greatly improving the efficiency of chip fabrication in the field of abstract Design and promoting the formation of chip types with higher complexity.

With the continuous development of chip process technology, the design constraints required in the process of converting codes into logic circuits are not limited to the aspects of time sequence, power consumption, area and the like, and the innovation and the progress of basic circuit physical layout and technical tools are included. Developers must do the placement and routing work, i.e., determine the locations and shapes of the transistors and the connections between the transistors. In designing the layout and wiring, it is necessary to ensure the accuracy of connection of each circuit and to meet the requirements of the manufacturing process, i.e., design rules, constraints, and the like. In addition, the indexes of the circuit, such as time sequence, power consumption and area, need to be optimized, and a balance point is found to seek an optimal solution. Therefore, VLSI requires an increasingly higher design flow and is more precise in wiring technology. Facing the attendant opportunities and challenges, the routing process in VLSI design is particularly important in device fabrication. The wiring result directly affects the integrability and consumption cost of the chip, which is also important in industrial production. Therefore, many manufacturers and researchers in the related industries strive to continuously optimize the wiring process, improve the efficiency of the design link, and create high-quality wiring results, so as to manufacture chips with more powerful functions.

To better address the problem of large and complex routing in VLSI design, the routing process is generally divided into two stages, namely global routing and detailed routing. In the overall wiring, a region where wiring is possible is first divided into wiring units. And performing preliminary wiring connection on the divided wiring units to generate an integral wiring scheme. After a global wiring scheme is provided, the wiring problem in each wiring unit is solved, and detailed wiring is performed according to specific constraints in the wiring units. The overall routing greatly reduces the complexity and redundancy of routing for the following detailed routing process, thereby completing the routing design faster and with higher quality. The good overall wiring contributes to an increase in the efficiency of the overall wiring, thereby contributing to high-quality production of chips using integrated circuits, and it follows that the overall wiring is lightweight throughout the wiring process.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a multi-layer global routing method for a very large scale integrated circuit based on multi-strategy optimization, which avoids the problems of complicated process and local optimization of routing results caused by directly applying the conventional routing algorithm.

The invention is realized by adopting the following scheme: a multi-strategy optimization based VLSI (very large scale integration) multilayer overall wiring method comprises the following steps:

step S1: in the pre-connection wiring stage, a dynamic adjustment strategy of virtual capacity is adopted to properly adjust and reduce the channel capacity; after a multi-end wire mesh is decomposed into a plurality of two-end wire meshes through a minimum spanning tree algorithm, the virtual capacity of a wiring channel in the horizontal and vertical directions is reduced to 1/2, and the channel capacity of the remaining 45-degree direction and 135-degree direction is kept unchanged; directly connecting the simple wire nets with the wire nets at the two ends in an X-structure grid routing mode under the constraint of new channel capacity; the simple wire mesh is a wire segment formed by wire meshes at two ends, and the slope value is 0, -1, +1 or infinity;

step S2: finding the most crowded wiring area in the wiring recombination stage under the global consideration, then adopting a self-adaptive expansion strategy of the wiring sub-area to perform self-adaptive expansion on the wiring sub-area, and correspondingly adjusting the expanded range and the expansion speed according to different congestion degrees after wiring;

step S3: during wiring, a dynamic adjustment strategy of virtual capacity is adopted to dynamically adjust the virtual capacity of the channel, channel capacities in different channel directions are mutually supplemented, namely the horizontal direction and the 45-degree direction are dynamically adjusted, the vertical direction and the 135-degree direction are dynamically adjusted, and the residual channel capacity is supplemented, namely the horizontal direction and the 45-degree direction are compared, and the vertical direction and the 135-degree direction are opposite to a smaller wiring channel;

step S4: and carrying out initiating search and wiring through the A-algorithm by adopting a heuristic search strategy based on the A-algorithm.

Further, the step S1 specifically includes the following steps:

step S11: inputting the pin position of each wire net, the channel capacity of a wiring area and a wiring layer corresponding to the pin, namely inputting data given by benchmark;

step S12: judging whether the pin number of the wire net is equal to 2 or not, if so, judging whether the position relation between the two pins meets a right-angle structure or not, if so, connecting the two pins if available wiring resources exist in the wiring area, and if so, continuing to execute the step S13;

step S13: generating an X-structure Steiner tree of each wire net through a particle swarm algorithm;

step S14: decomposing a multi-end wire net into a plurality of two-end wire nets by a minimum spanning tree algorithm, and recording all the two-pin wire nets;

step S15: setting a channel capacity constraint condition of a pre-connection stage, namely reducing the channel capacity in the Manhattan direction in the X structure to a half of the original channel capacity, and keeping the channel capacity in the 45-degree direction and the 135-degree direction unchanged;

step S16: all two-pin nets are pre-connected without violating the set channel capacity constraints.

Further, the mutually complementing of the channel capacities in the different channel directions in step S3 requires that constraint conditions are satisfied, where the constraint conditions are:

the constraint conditions are shown in formula (1) and formula (2):

d1＝d1+C,d2＝d2-C；d1＜C&&d2＞2C (1)

d1＝d1-C,d2＝d2+C；d1＞2C&&d2＜C (2)

wherein C is a preset channel capacity threshold constant; d1 represents the channel capacity remaining in the horizontal or vertical direction; d2 represents the channel capacity remaining in the 45 degree or 135 degree direction;

as can be seen from the formula, this strategy is triggered only if the remaining channel capacity is less than the threshold and the channel capacity in the other direction is greater than twice the threshold.

Further, the step S2 specifically includes the following steps:

step S21: searching the most congested wiring unit in the current wiring area;

step S22: self-adaptive expansion is carried out on the most congested wiring subarea, and two unconnected pin nets in the wiring subarea are recorded; the expansion speed of the self-adaptive expansion is determined by the number of the two-pin wire nets in the current wiring area;

step S23: in the expanded wiring subarea, aiming at the unconnected pin nets, a given net in the current subarea is distributed by applying a particle swarm algorithm and an A-x algorithm;

step S24: the steps S22, S23 are repeated until the wiring sub-area is enlarged to the whole overall wiring area.

Further, the specific contents of finding the most congested routing unit in the current routing area in step S21 are: through traversing the whole overall wiring area, the most congested wiring unit is searched out in comparison to serve as a wiring sub-area; in the searching process, comparing the congestion degree of the sub-area selected each time with the congestion degree of the most congested area recorded currently, and if the selected congestion degree is higher, updating the most congested area recorded currently; if the degrees are the same, judging the positions of the two areas in the overall wiring area respectively, and selecting the position closer to the center as the most congested area; if not, keeping the record unchanged;

judging the congestion degree index of the wiring area, wherein the index is the channel capacity used in the area in an accumulated way; for one wiring unit of the wiring area, calculating the channel capacity of the node in four directions of horizontal direction, 45 degrees, vertical direction and 135 degrees; therefore, the congestion degree calculation manner is as follows:

wherein, N represents the current wiring unit; d (i) represents the number of channel capacity usages of the wiring unit N in the direction i.

Further, the specific content of the step S22 of adaptively expanding the most congested routing sub-region is:

when the number of the two-pin wire nets in the wiring subarea is less than 50, the expansion size of the wiring subarea is set to be 3; when the number of the two-pin wire grids in the wiring subarea is more than or equal to 50 and less than 100, the size of the extension of the wiring subarea is set to be 2; when the number of the two-pin nets in the wiring sub-area is equal to or greater than 100 and less than 200, the size of the extension of the wiring sub-area is set to 1.

Further, in step S23, a particle swarm algorithm is first applied to perform overall optimization, and a set extended _ unconnected is used to store the unconnected two-pin nets; judging whether the set is empty or not, if so, indicating that the particle swarm algorithm is effectively connected with all the two pin networks; if not, the particle swarm algorithm cannot effectively connect all the two-pin nets, and the rest two-pin nets continue to be operated by the A-x algorithm.

Further, in the step S4

The cost function of the a-algorithm is shown in formula (4):

F(x)＝G(x)+H(X) (4)

wherein f (x) represents the final cost estimate from the starting point to the end point through node x in G, (x) represents the actual cost of movement from the starting point to node x in G, and h (x) represents the estimated cost from node x to the end point in G;

taking the Manhattan distance between the starting point with the weight and the current point as the actual cost G (t) of selection, as shown in formula (5); selecting an X structural path between a current point and an end point as a heuristic function H (t), as shown in formula (6);

wherein w is a weight; stn_xAnd stn_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t; te_xHente_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t;

the specific implementation of the a-algorithm is as follows: using an OPEN table and a CLOSE table; the OPEN table is an OPEN list to be checked and stores node information needing to be detected in the searching process; the CLOSE table is a closed list that stores nodes that have been added to the shortest path, and these nodes do not need to be paid attention again; when the algorithm starts, two pins of two-end wire nets to be connected are respectively set as a current node and a target node, and the current node is used as a starting point; searching a neighbor node of the current node, and searching a next neighbor node of the current node if the neighbor node cannot be reached, namely the path is not feasible; if the path is feasible, calculating the F (x) value of the neighbor node and adding the neighbor node into the OPEN table until all the neighbor nodes are searched; deleting the current node from the OPEN table, and putting the current node into a CLOSE table; taking the point with the minimum value of F (x) in the OPEN table as the current node, judging whether the current node is the target node or not, and if not, repeating the searching process; if so, the algorithm stops.

Compared with the prior art, the invention has the following beneficial effects: the problems of redundant searching process and local optimal wiring result are effectively avoided, different wiring environments are more flexibly dealt with, and the total wiring bus length is further shortened.

Drawings

FIG. 1 is a diagram showing a difference between a Manhattan structure and an X structure according to an embodiment of the present invention, wherein FIG. 1(a) is a diagram showing a Manhattan structure design; FIG. 1(b) is an X-structure design drawing

Fig. 2 is a diagram illustrating a calculation manner of an X structure according to an embodiment of the present invention, in which fig. 2(a) is located at the same horizontal line, fig. 2(b) is located at the same vertical line, fig. 2(c) is a diagram illustrating that a vertical distance is greater than a horizontal distance, fig. 2(d) is a diagram illustrating that a vertical distance is equal to the horizontal distance, and fig. 2(e) is a diagram illustrating that a vertical distance is less than the horizontal distance.

FIG. 3 is a flow chart of an embodiment of the present invention.

Fig. 4 is a flowchart of an a-algorithm according to an embodiment of the present invention.

Fig. 5 is a selection diagram of a different path according to an embodiment of the present invention.

Detailed Description

The invention is further explained below with reference to the drawings and the embodiments.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an", and/or "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of the features, steps, operations, devices, components, and/or combinations thereof.

The embodiment provides a multi-strategy optimization-based VLSI (very large scale integration) multilayer overall wiring method, which comprises the following steps of:

step S1: in the pre-connection wiring stage, a dynamic adjustment strategy of virtual capacity is adopted to properly adjust and reduce the channel capacity; after a multi-end wire mesh is decomposed into a plurality of two-end wire meshes through a minimum spanning tree algorithm, the virtual capacity of a wiring channel in the horizontal and vertical directions is reduced to 1/2, and the channel capacity of the remaining 45-degree direction and 135-degree direction is kept unchanged; directly connecting the simple wire nets with the wire nets at the two ends in an X-structure grid routing mode under the constraint of new channel capacity; the simple wire mesh is a wire segment formed by wire meshes at two ends, and the slope value is 0, -1, +1 or infinity; (the X-structured grid is composed of horizontal lines, vertical lines, 45-degree diagonal lines, and 135-degree diagonal lines)

Step S2: finding the most crowded wiring area in the wiring recombination stage under the global consideration, then adopting a self-adaptive expansion strategy of the wiring sub-area to perform self-adaptive expansion on the wiring sub-area, and correspondingly adjusting the expanded range and the expansion speed according to different congestion degrees after wiring;

step S3: during wiring, a dynamic adjustment strategy of virtual capacity is adopted to dynamically adjust the virtual capacity of the channel, channel capacities in different channel directions are mutually supplemented, namely the horizontal direction and the 45-degree direction are dynamically adjusted, the vertical direction and the 135-degree direction are dynamically adjusted, and the residual channel capacity is supplemented, namely the horizontal direction and the 45-degree direction are compared, and the vertical direction and the 135-degree direction are opposite to a smaller wiring channel;

step S4: and carrying out initiating search and wiring through the A-algorithm by adopting a heuristic search strategy based on the A-algorithm.

In this embodiment, the step S1 specifically includes the following steps:

step S11: inputting the pin position of each wire net, the channel capacity of a wiring area and a wiring layer corresponding to the pin, namely inputting data given by benchmark;

step S12: judging whether the pin number of the wire net is equal to 2 or not, if so, judging whether the position relation between the two pins meets a right-angle structure or not, if so, connecting the two pins if available wiring resources exist in the wiring area, and if so, continuing to execute the step S13;

step S13: generating an X-structure Steiner tree of each wire net through a particle swarm algorithm;

step S14: decomposing a multi-end wire net into a plurality of two-end wire nets by a minimum spanning tree algorithm, and recording all the two-pin wire nets;

step S15: setting a channel capacity constraint condition of a pre-connection stage, namely reducing the channel capacity in the Manhattan direction in the X structure to a half of the original channel capacity, and keeping the channel capacity in the 45-degree direction and the 135-degree direction unchanged;

step S16: all two-pin nets are pre-connected without violating the set channel capacity constraints.

In this embodiment, the mutually complementing of the channel capacities in different channel directions in step S3 requires that constraint conditions be satisfied, where the constraint conditions are:

the constraint conditions are shown in formula (1) and formula (2):

d1＝d1+C,d2＝d2-C；d1＜C&&d2＞2C (1)

d1＝d1-C,d2＝d2+C；d1＞2C&&d2＜C (2)

wherein C is a preset channel capacity threshold constant; d1 represents the channel capacity remaining in the horizontal or vertical direction; d2 represents the channel capacity remaining in the 45 degree or 135 degree direction;

as can be seen from the formula, this strategy is triggered only if the remaining channel capacity is less than the threshold and the channel capacity in the other direction is greater than twice the threshold.

In this embodiment, the step S2 specifically includes the following steps:

step S21: searching the most congested wiring unit in the current wiring area;

step S22: self-adaptive expansion is carried out on the most congested wiring subarea, and two unconnected pin nets in the wiring subarea are recorded; the expansion speed of the self-adaptive expansion is determined by the number of the two-pin wire nets in the current wiring area;

step S23: in the expanded wiring subarea, aiming at the unconnected pin nets, a given net in the current subarea is distributed by applying a particle swarm algorithm and an A-x algorithm;

step S24: the steps S22, S23 are repeated until the wiring sub-area is enlarged to the whole overall wiring area.

In this embodiment, the specific content of finding the most congested routing unit in the current routing area in step S21 is: through traversing the whole overall wiring area, the most congested wiring unit is searched out in comparison to serve as a wiring sub-area; in the searching process, comparing the congestion degree of each selected sub-area with the congestion degree of the most congested area recorded currently, and if the selected congestion degree is higher, updating the most congested area recorded currently; if the degrees are the same, judging the positions of the two areas in the general wiring area respectively, and selecting the position closer to the center as the most congested area; otherwise, keeping the record unchanged;

judging the congestion degree index of the wiring area, wherein the index is the channel capacity used in the area in an accumulated way; for one wiring unit of the wiring area, calculating the channel capacity of the node in four directions of horizontal direction, 45 degrees, vertical direction and 135 degrees; therefore, the congestion degree calculation manner is as follows:

wherein, N represents the current wiring unit; d (i) represents the number of channel capacity usages of the wiring unit N in the direction i.

In this embodiment, the specific content of the step S22 of performing adaptive expansion on the most congested routing sub-region is:

when the number of the two-pin wire nets in the wiring subarea is less than 50, the expansion size of the wiring subarea is set to be 3; when the number of the two-pin wire grids in the wiring subarea is more than or equal to 50 and less than 100, the size of the extension of the wiring subarea is set to be 2; when the number of the two-pin nets in the wiring sub-area is equal to or greater than 100 and less than 200, the size of the extension of the wiring sub-area is set to 1.

In this embodiment, in the step S23, the particle swarm algorithm is first used to perform the overall optimization, and if the particle swarm algorithm cannot effectively connect all the two-pin nets, the remaining two-pin nets continue to be performed using the a-x algorithm.

In this embodiment, the step S4

The cost function of the a-algorithm is shown in formula (4):

F(x)＝G(x)+H(X) (4)

wherein f (x) represents the final cost estimate from the starting point to the end point through node x in G, (x) represents the actual cost of movement from the starting point to node x in G, and h (x) represents the estimated cost from node x to the end point in G;

taking the Manhattan distance between the starting point with the weight and the current point as the actual cost G (t) of selection, as shown in formula (5); selecting an X structural path between a current point and an end point as a heuristic function H (t), as shown in formula (6);

wherein w is a weight; stn_xAnd stn_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t; te_xHente_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t;

the specific implementation of the a-algorithm is as follows: using an OPEN table and a CLOSE table; the OPEN table is an OPEN list to be checked and stores node information needing to be detected in the searching process; the CLOSE table is a closed list that stores nodes that have been added to the shortest path, and these nodes do not need to be paid attention again; when the algorithm starts, two pins of two-end wire nets to be connected are respectively set as a current node and a target node, and the current node is used as a starting point; searching a neighbor node of the current node, and searching a next neighbor node of the current node if the neighbor node cannot be reached, namely the path is not feasible; if the path is feasible, calculating the F (x) value of the neighbor node and adding the neighbor node into the OPEN table until all the neighbor nodes are searched; deleting the current node from the OPEN table, and putting the current node into a CLOSE table; taking the point with the minimum value of F (x) in the OPEN table as the current node, judging whether the current node is the target node or not, and if not, repeating the searching process; if so, the algorithm stops.

Routing is one of the key stages in Very Large Scale Integration (VLSI) physical design. In a complex routing process, the overall routing results directly affect the routing quality. Most of the conventional overall wiring algorithms are based on the manhattan structure, but the manhattan structure has many limitations on the optimization of the wire length of the wiring result. Compared with the Manhattan structure, the X structure is expanded in the winding direction, and two winding directions of 45 degrees and 135 degrees are added. At the same time, the overall wiring is made more complicated by the X-structure proposed. The invention provides a multi-layer overall router of a very large scale integrated circuit based on multi-strategy optimization, which is called MS-XGROUTER. The embodiment provides three strengthening strategies, and the wiring effect of the strengthening strategies is strengthened in different wiring stages. The three strategies proposed by this example are as follows: (1) in order to improve the utilization rate of the wiring capacity, a dynamic adjustment strategy of the virtual capacity is provided, the wiring resources in the horizontal and vertical directions in the initial stage are limited, and channels with less wiring resources are supplemented in the wiring recombination stage; (2) in order to better balance the wiring efficiency of the wiring device and the pressure of global search, a self-adaptive expansion strategy of a wiring sub-region is provided, the expansion speed is controlled according to the number of two pins in the wiring region, and the optimizing pressure of a Particle Swarm Optimization (PSO) is reduced; (3) in order to avoid the wiring result from being trapped in local optimization, a heuristic search strategy based on an A-star algorithm is provided, and a more appropriate wiring path is found by using a heuristic function.

In this embodiment:

overall wiring model:

in the overall wiring design, wire length is a large important indicator of the wiring result, so it is very important in the overall wiring problem to find the shortest path in a given wiring diagram for each net. The overall wiring problem can be described as: for a set of nets N ═ N₁,n₂,...,n_kWhere net n_kAnd the grid graph G (V, E) consists of a pin set V and an edge set E, and a given wire net is wired in the grid graph G (V, E). In G (V, E), for each net, the overall routing needs to find a spanning tree that connects the vertices corresponding to all pins in the net.

To achieve the best routability of the chip while ensuring connectivity of all nets, the routing result should minimize the total overflow of all edges and the required routing bus length. Unlike the conventional manhattan model, the X-structure has two more routing directions, i.e., 45 degree and 135 degree directions, for each routable connection point within the same routing area, in addition to the horizontal and vertical directions, as shown in fig. 1. This makes the wiring design under the X structure more complex, but also significantly improves its physical performance, providing more routing and shorter wiring paths in the same area.

Assuming that each unit side of the X-structured grid is a, thenThe connection between the pin a and pin B points in the same two-pin net, in the manhattan model, has a shortest path length of 2a, as shown in fig. 1 (a). Under the X structure, the shortest path length of the two-pin net isAs shown in fig. 1 (b).

FIG. 2 shows two pins P in the same plane_i(X_i,Y_i) And P_j(X_j,Y_j) Five positional relationships therebetween, and the distances d (P) therebetween for the five positional relationships_i,P_j) The following formula was used for the calculation.

(1) When X is present_i＝X_j,Y_i！＝Y_jWhen d (P)_i,P_j)＝|Y_i-Y_j|；

(2) When X is present_i！＝X_j,Y_i＝Y_jWhen d (P)_i,P_j)＝|X_i-X_j|；

(3) When X is present_i！＝X_j,Y_i！＝Y_jThen, there are the following three cases:

(a) if | X_i-X_j|<|Y_i-Y_j|,

(b) If | X_i-X_j|＝|Y_i-Y_j|,

(c) If | X_i-X_j|>|Y_i-Y_j|,

Overview of the overall flow of MS-XGROUTER:

as shown in fig. 3, the MS-XGRouter overall routing algorithm based on the X-structure multi-layer process is mainly divided into a pre-connection stage, a routing re-assembly stage under global consideration, and a layer allocation stage.

When wiring is started, firstly, a pre-connection stage is carried out, and the main work is to read the current net information and carry out decomposition and pre-connection wiring operation on the current net information; then, through a wiring recombination stage under global consideration, by a series of algorithms and by utilizing the advantages of global search capability, heuristic search and the like, self-adaptive expansion and wiring recombination are carried out on the selected wiring sub-region, so that wiring is realized; and finally, realizing reasonable distribution of the line segments on the wiring layer by a corresponding scheduling strategy in the layer distribution stage. The three optimization strategies proposed by the invention are respectively outlined in the overall flow chart of the MS-XGROUTER routing algorithm of FIG. 3.

3. A pre-connection stage:

in the pre-connection stage, the MS-XGRouter needs to process net information required for the overall routing and build a topology for each net to get the initial routing result. The main flow design of the MS-XGROUTER algorithm is as follows:

(1) reading information such as pin positions of all wire nets and channel capacity of a wiring area;

(2) generating an X-structure Steiner tree of each wire net;

(3) disassembling the multi-pin wire net, and recording all the two-pin wire nets;

(4) setting a channel capacity constraint condition of a pre-connection stage, reducing the channel capacity in the Manhattan direction in the X structure to be half of the original channel capacity, and keeping the channel capacity in the 45-degree direction and the 135-degree direction unchanged;

(5) all two-pin nets are pre-connected without violating the set channel capacity constraints.

It is noted that the manner in which the MS-XGRouter handles the multi-pin net and the two-pin net is different. For the net with the pin number less than 2, the MS-XGRouter does not need to construct a topological structure or decompose the net. For nets with pin counts greater than 2, this is required. In addition, the MS-XGROUTER records the connected two-pin net and the unconnected two-pin net respectively for subsequent stage wiring.

4. Global consideration of the wire reorganization stage:

in the wiring reorganization stage under the global consideration, MS-XGROUTER uses various wiring algorithms to perform net wiring reorganization based on the expansion of the wiring area. The MS-XGROUTER preferentially selects the area with congestion, and records the two-pin wire network needing to be connected. And finally, connecting the two pin nets to be connected by using a particle swarm algorithm and an A-x algorithm in sequence. The algorithm of the wire rearrangement stage under the global consideration is mainly designed as follows:

(1) searching the most congested wiring unit in the current wiring area;

(2) self-adaptive expansion is carried out on the most congested wiring sub-region, and two unconnected pin nets in the wiring sub-region are recorded;

(3) in the expanded routing sub-area, for unconnected pin nets, a given net in the current sub-area is routed using the group-of-particles algorithm and the a-algorithm.

(4) And (4) repeating the step (2) and the step (3) until the wiring sub-area is expanded to the whole overall wiring area.

The expansion speed in step (2) is determined by the number of two-pin nets in the current wiring area. In the step (3), for all the unconnected two-pin nets in the sub-area, the MS-XGROUTER firstly uses a particle swarm algorithm to perform overall optimization. If the particle swarm algorithm cannot effectively connect all the two-pin nets, the remaining two-pin nets continue to be operated by using the A-x algorithm.

5. A layer distribution stage:

the MS-XGRouter used in the present invention is an algorithm based on routing connections in a multi-layer process during the overall routing process, so this stage is mainly used to solve the problem of distribution and scheduling of multiple routing layers during the routing process.

The MS-XGROUTER wiring algorithm overall optimization strategy is as follows:

the MS-XGROUTER wiring algorithm proposed by the embodiment is improved on the basis of the ML-XGROUTER. MS-XGROUTER proposes the following three strategies: (1) dynamic adjustment of virtual capacity; (2) adaptive expansion of wiring sub-regions; (3) and (4) carrying out heuristic search strategy based on A-algorithm. By simultaneously carrying out the three optimization strategies, a certain optimization target is achieved, and the overall wiring efficiency and some important indexes of the final wiring result are improved, so that the distributability of the whole circuit design of the chip is influenced.

(1) (strategy one) dynamic adjustment strategy of virtual capacity:

the purpose of the strategy-virtual capacity dynamic adjustment strategy is to improve the utilization rate of the wiring capacity, thereby exerting the advantages of the X structure as much as possible. Strategy one dynamically adjusts and constrains the virtual capacity of a routing channel, primarily in two parts. The first part is that in the pre-connection stage, after the wire mesh decomposition is finished, the routing algorithm flow reduces the virtual capacity of the routing channel in the horizontal and vertical directions to 1/2, and the channel capacity of the remaining 45-degree direction and 135-degree direction is kept unchanged. The reason for this improvement in MS-XRouter is: the original wiring capacity differs significantly from the horizontal and vertical directions at 45 degrees and 135 degrees. In general, the capacity in the horizontal and vertical directions is much more than 45 degrees and 135 degrees. If the channel capacity in the 45 degree and 135 degree directions is reduced in the pre-connection stage, the advantage of the X structure in terms of the line length will be greatly weakened. The second part is that in the wiring reorganization stage under the global consideration, the channel capacities in different channel directions are mutually supplemented, namely the horizontal direction and the 45-degree direction are dynamically adjusted, the vertical direction and the 135-degree direction are dynamically adjusted, and the wiring channel with smaller residual channel capacity is timely supplemented. The dynamic adjustment of the channel capacity by the MS-XGRouter at this stage is to allow the current best path to be selected when the two-pin nets are connected.

In the wiring reorganization stage under the global consideration, the adjustment of the channel capacity meets the constraint condition preset by the user. The constraint conditions are shown in formula (1) and formula (2).

d1 ═ d1+ C, d2 ═ d 2-C; d1 < C & & d2 > 2C formula (1)

d1 ═ d1-C, d2 ═ d2+ C; d1 > 2C & & d2 < C formula (2)

Wherein C is a preset channel capacity threshold constant; d1 represents the remaining channel capacity in the horizontal or vertical direction; d2 represents the remaining channel capacity in either the 45 degree or 135 degree direction.

As can be seen from the formula, this strategy is triggered only if the remaining channel capacity is less than the threshold and the channel capacity in the other direction is greater than twice the threshold.

(2) (strategy two) adaptive extension strategy of wiring sub-regions:

and the second strategy mainly aims at the wiring recombination stage under the global consideration and provides a new constraint definition for the expansion of the wiring area of the algorithm process.

According to the invention, the most congested wiring unit is searched out as the wiring sub-area by traversing the whole overall wiring area. In the searching process, comparing the congestion degree of the sub-area selected each time with the congestion degree of the most congested area recorded currently, and if the selected congestion degree is higher, updating the most congested area recorded currently; if the degrees are the same, judging the positions of the two areas in the general wiring area respectively, and selecting the position closer to the center as the most congested area; otherwise, the record is kept unchanged.

The index for determining the degree of congestion in the routing area is the channel capacity used cumulatively in the area. It is worth noting that for one routing unit of a routing region, the MS-XGRouter only calculates the channel capacity of the node in four directions, horizontal, 45 degrees, vertical, and 135 degrees. Therefore, the congestion degree calculation manner is as follows.

Wherein, N represents the current wiring unit; d (i) represents the number of channel capacity usages of the wiring unit N in the direction i.

The basic idea of the adaptive expansion strategy of routing sub-regions is: before expansion, the constraint conditions that the number of the two-pin wire nets in the current wiring subarea meets are judged, and the expansion speed under the corresponding conditions is adjusted. The more the number of the two-pin wire nets in the wiring subarea of the algorithm is, the slower the expanding speed is correspondingly; otherwise the faster. The algorithm can better balance the overall wiring efficiency and the pressure of the overall search algorithm, and achieve the expected optimization goal.

Pseudo code for the adaptive extension of strategy two wiring sub-regions is shown below. Assuming Bound is the number of edges of the wiring sub-region that reach the boundary, d is the size of the wiring sub-region extension, twopins records the two-pin nets in the wiring sub-region. The algorithm stops if the wiring sub-region completely covers the entire wiring region. Firstly, recording two-pin nets in the current wiring subarea, and when the number of the two-pin nets in the wiring subarea is less than 50, setting d to be 3. When the number of the two-pin wire grids in the wiring sub-area is more than or equal to 50 and less than 100, d is set to be 2. When the two-pin wire mesh number in the wiring sub-area is more than or equal to 100 and less than 200, d is set to be 1. The MS-XGRouter routes the two-pin net using the particle swarm algorithm and the a-x algorithm only if it is greater than 200. The reason for this is that the advantages of the particle swarm optimization in global optimization can be fully exerted, and the situation of partial optimization is avoided. Similarly, when the particle swarm algorithm cannot obtain an effective routing path, the a-algorithm can obtain an effective routing result in the whole routing area by using the heuristic function of the a-algorithm.

Just by comprehensively utilizing various advantages of the particle swarm algorithm and the A-star algorithm, the routing recombination stage of the MS-XRouter under the global consideration can optimize the wire length as much as possible.

(3) (strategy three) heuristic search strategy based on A-x algorithm:

in a static road network, the a-x algorithm is a commonly used heuristic search algorithm for finding a shortest path. In the overall wiring grid diagram, the part needing each connection is abstracted into one node, and the related cost of the connection between the nodes can be calculated through some functions. In the A-algorithm, the actual movement cost and the estimated cost of the current node are comprehensively considered, and a most suitable path is selected through repeated comparison.

In the a-algorithm, the selection of the path depends on the setting of the cost function. In general, the cost function of the a-algorithm includes two parts, namely, the actual path cost and the estimated cost. Therefore, the cost function of the a-algorithm is shown in equation (4).

F (x) ═ g (x) + h (x) formula (4)

Where f (x) represents the last cost estimate from the starting point to the end point through node x in G, (x) represents the actual cost of movement from the starting point to node x in G, and h (x) represents the estimated cost from node x to the end point in G.

This process is also commonly referred to as heuristics. This is because h (x) is actually an estimate of the remaining distance, not the actual value, and there may be many cost-affecting factors in the path connection process, so its exact value can only be known if the final path is found. Therefore, h (x), also known as a heuristic function, exploits the information of node x to the end point, in conjunction with the weights of the start point to node x to develop a heuristic search. The better the evaluation function f (x) is if more information or more constraints are present, which is also an advantage of the a algorithm over the Breadth First Search (BFS) algorithm, because in the BFS algorithm, its information heuristic h (x) is 0.

In a geometric road network, the manhattan distance between two points is often taken as an estimate. When the actual moving cost g (x) is constant, the valuation function f (x) is restricted and influenced by h (x), that is, the closer the node is to the destination, the smaller the value of h (x), and the smaller the value of f (x), the shortest path is ensured to be searched along the direction of the target point. Assuming that node x has the minimum cost to reach the destination of d (x), there are three choices for H (x): (1) when h (x) < d (x), since the heuristic function value is small, the heuristic information is weak, the search range is large, and the number of searched nodes is relatively large, the search efficiency is low, but an optimal solution can be obtained. (2) When h (x) is d (x), the heuristic function value is the same as the minimum cost, so that the search can be performed according to the shortest path, and the search efficiency is the highest. (3) When h (x) > d (x), the heuristic information is strong, the search range is small, and the number of searched nodes is relatively small, the search efficiency is high, but the optimal solution cannot necessarily be obtained, because the heuristic function value is large.

However, another problem of the efficiency of the algorithm operation is also existed, that is, the more the h (x) heuristic information is, the more the calculation amount is increased, and the time consumption is increased correspondingly, thereby increasing the pressure of the routing algorithm. Therefore, there is a trade-off problem, namely, an appropriate h (x) heuristic information amount is adopted to ensure the accuracy and efficiency of the algorithm searching path.

Different from the heuristic function of the traditional A-star algorithm, the Manhattan distance between the starting point of the MS-XGROUTER with the weight and the current point is used as the actual cost G (t) of selection, as shown in a formula (5). An X structure path between the current point and the terminal point is selected as a heuristic function H (t), as shown in formula (6).

Wherein w is a weight; stn_xAnd stn_yRespectively representing the distances from the starting point to the horizontal direction and the vertical direction of the current node t; te_xHente_yRespectively representing the distances from the start point to the horizontal and vertical directions of the current node t.

For the specific implementation of the a-algorithm, two tables are mainly utilized: OPEN table and CLOSE table. The OPEN table is an OPEN list to be checked and stores node information to be detected in the searching process; the CLOSE table is a closed list that stores those nodes that have been added to the shortest path that do not need to be attended to again. The flow of implementing the a-algorithm is shown in fig. 4.

By utilizing the heuristic search advantage of the A-star algorithm, the defects that the BFS algorithm in the original wiring algorithm ML-XGROUTER always selects the path with the shortest wire length in the wiring process and the search efficiency is poor are effectively overcome. Within a given routing area, the degree of routing congestion is expressed in terms of lighter colors, with darker colors providing higher congestion and vice versa. In the wiring area, there is a two-pin net, and in order to connect the two pins, there are three connection paths: (1) the congestion situation in the current wiring area is not considered, and only the shortest path of the wire length factor is considered, such as path 1 shown in fig. 5; (2) considering no wire length factor, only the shortest path of the congestion situation is emphasized, such as path 3 shown in fig. 5; (3) the shortest path found by comprehensively considering the wire length factor and the congestion degree is shown as a path 2 in fig. 5.

Generally, Path 2, which is considered together, is the optimal solution because it consumes less routing resources than Path 3, resulting in shorter wire lengths through the net, as compared to Path 1, which passes through less congested areas. However, the routing of the path 2 may always be selected, which may fall into a local extremum. Therefore, the three path methods are fully utilized in the overall wiring. In the initial wiring stage, the wiring resources are relatively abundant, so that the route in the route 1 mode can be selected more easily during wiring; in the middle stage of wiring, a path similar to the path 2 is selected, so that the excessive consumption of wiring resources can be avoided as much as possible, and the overflow during the subsequent wiring is prevented; at the end of the route, since most of the routing resources are already in use, it may be preferable to select a route in the form of Path 3 in order to avoid and reduce net overflow as much as possible.

In contrast to the direct use of the a-algorithm, the manhattan architecture only requires traversal of four directions, up, down, left, and right, on the horizontal and vertical routing channels, whereas the a-algorithm used in the present invention changes it to eight directions under the X architecture. Meanwhile, by combining with a PSO algorithm, an overall better solution can be found so as to achieve an optimization target.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.