阅读说明：本技术 显示设备 (Display device ) 是由 金善光 罗釉美 赵康文 于 2021-02-18 设计创作，主要内容包括：公开了一种显示设备,该显示设备包括：发射面板,包括第一发光二极管、第二发光二极管、第三发光二极管和第一电力线,其中,第一发光二极管、第二发光二极管和第三发光二极管具有堆叠的结构,并且第一电力线位于像素区域周围的激光钻孔区域中,并且电连接到第一发光二极管、第二发光二极管和第三发光二极管；以及颜色面板,位于发射面板上,并且包括阻光区域和各自能够透射不同颜色的光的第一颜色区域、第二颜色区域和第三颜色区域,其中,列间隔件位于发射面板与颜色面板之间,并且具有在竖直方向上与激光钻孔区域叠置的至少一部分。(Disclosed is a display device including: an emission panel including first, second, third, and first power lines, wherein the first, second, and third light emitting diodes have a stacked structure, and the first power lines are located in a laser drilling region around a pixel region and are electrically connected to the first, second, and third light emitting diodes; and a color panel on the emission panel and including a light blocking region and first, second, and third color regions each capable of transmitting light of a different color, wherein the column spacer is between the emission panel and the color panel and has at least a portion overlapping the laser drilling region in a vertical direction.)

1. A display device, the display device comprising:

an emission panel including a first light emitting diode, a second light emitting diode, a third light emitting diode, and a first electric line of force, wherein the first light emitting diode, the second light emitting diode, and the third light emitting diode are each arranged in a pixel region and each have a stacked structure including a pixel electrode, a counter electrode, and an intermediate layer having an emission layer, and the first electric line of force is located in a laser drilling region around the pixel region and is electrically connected to the first light emitting diode, the second light emitting diode, and the third light emitting diode; and

a color panel on the emission panel and including a light blocking region and first, second, and third color regions each capable of transmitting light of a different color,

wherein a column spacer is located between the emission panel and the color panel and has at least a portion overlapping the laser drilling region in a vertical direction.

2. The display device of claim 1, wherein the intermediate layer extends from the pixel region to the laser drilling region and includes a via in the laser drilling region,

the counter electrode integrally extends through the pixel region and the laser drilling region, and

the first power line is electrically connected to the counter electrode through the via in the laser drilling region.

3. The display device of claim 2, wherein a thin film encapsulation layer is located on the emission panel,

a filler is located on the color panel facing the emission panel, and

the column spacers are located in the filler material, and the counter electrode and the first power line are electrically connected in the laser drilled region.

4. The display apparatus of claim 3, wherein the column spacers are located in the laser drilled regions.

5. The display apparatus of claim 3, wherein portions of the column spacers overlap the laser drilled regions.

6. The display device according to claim 2, wherein a connection electrode is located on the same layer as the pixel electrode in the laser drilling region,

an upper surface of the connection electrode is electrically connected to the counter electrode, and

the lower surface of the connection electrode is electrically connected to the first power line.

7. The display device according to claim 6, wherein a first insulating layer covering at least a part of the first power line is located on the first power line,

the connection electrode is located on the first insulating layer,

a second insulating layer on the connection electrode, the second insulating layer covering at least a part of the connection electrode and having an opening for the connection electrode,

the intermediate layer covers an outer surface of the second insulating layer, the via hole in the intermediate layer overlaps with the opening for the connection electrode, and

the counter electrode is electrically connected to the first power line through the opening for the connection electrode in the second insulating layer and the via hole in the intermediate layer.

8. The display device according to claim 6, wherein a first insulating layer is located over the first power line, the first insulating layer covering at least a part of the first power line and having an opening for the first power line,

the connection electrode is located on the first insulating layer,

a second insulating layer on the connection electrode, the second insulating layer covering at least a part of the connection electrode and having an opening for the connection electrode,

the intermediate layer covers the second insulating layer and the connection electrode, the via hole in the intermediate layer overlaps with the opening for the first electric line of force and the opening for the connection electrode, and

the counter electrode is electrically connected to the first power line through the opening for the first power line in the first insulating layer, the opening for the connection electrode in the second insulating layer, and the via hole in the intermediate layer.

9. The display device according to claim 2, wherein a thin film transistor is arranged in the pixel region, the thin film transistor is electrically connected to each of the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode, and has a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and

the first power line includes a first conductive layer on the same layer as the source electrode.

10. The display device according to claim 2, wherein a thin film transistor is located in the pixel region, the thin film transistor is electrically connected to each of the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode, and has a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and

the first power line includes a first conductive layer on the same layer as the source electrode and a second conductive layer electrically connected to the first conductive layer.

11. The display device according to claim 1, wherein a conductive protective layer covers the first power line.

12. The display device of claim 1, wherein the color panel comprises:

a light blocking layer corresponding to the light blocking area;

a color conversion transmission layer including a color conversion unit converting incident light into light of other colors and a transmission unit transmitting the incident light; and

a color layer including a plurality of color filters stacked with the color conversion transmission layer.

13. The display device of claim 12, wherein the color conversion unit comprises a plurality of quantum dots.

14. The display device according to claim 1, wherein the plurality of first power lines are spaced apart from each other around the plurality of pixel regions arranged adjacently, and

wherein regions where the laser drilling regions and the column spacers overlap are selectively arranged around the plurality of pixel regions.

15. A display device, the display device comprising:

a first substrate including a plurality of pixel regions and a laser drilling region disposed around each pixel region;

a light emitting diode disposed in the pixel region, electrically connected to the thin film transistor, and having a stacked structure including a pixel electrode, a counter electrode, and an intermediate layer having an emission layer;

a first power line in the laser drilling area and electrically connected to the light emitting diode;

a thin film encapsulation layer covering the pixel region and the laser drilling region;

a second substrate including a light blocking region and first, second, and third color regions each capable of transmitting light of different colors;

a filler covering the first color region, the second color region, the third color region, and the light blocking region; and

a column spacer in the filler material, wherein at least a portion of the column spacer vertically overlaps the laser drilled region.

16. The display device of claim 15, wherein the filler faces the thin film encapsulation layer, and

the counter electrode and the first power line are electrically connected in the laser drilling region.

17. The display apparatus of claim 16, wherein the column spacers are located in the laser drilled regions.

18. The display apparatus of claim 16, wherein portions of the column spacers overlap the laser drilled regions.

19. The display device of claim 15, wherein the intermediate layer extends from the pixel region to the laser drilling region and has a via in the laser drilling region,

the counter electrode integrally extends through the pixel region and the laser drilling region, and

the first power line is electrically connected to the counter electrode through the via in the laser drilling region.

20. The display device according to claim 19, wherein a connection electrode is located on the same layer as the pixel electrode in the laser drilling region,

an upper surface of the connection electrode is electrically connected to the counter electrode, and

the lower surface of the connection electrode is electrically connected to the first power line.

Technical Field

An aspect of one or more example embodiments relates to a display apparatus.

Background

In general, the display device may be used in mobile apparatuses such as smart phones, laptop computers, digital cameras, video cameras, portable information terminals, notebook or tablet personal computers, or in electronic apparatuses such as desktop computers, televisions, outdoor billboards, display devices for exhibitions, instrument panels for vehicles, or head-up displays (HUDs).

The display device includes, for example, a liquid crystal display device which generally utilizes a backlight or a light-emitting display device which generally includes a display element capable of emitting light. The light emitting display device may include a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode.

Recently, various designs have been developed to improve the quality of display devices.

The above information disclosed in this background section is only for enhancement of understanding of the background, and therefore the information discussed in this background section does not necessarily constitute prior art.

Disclosure of Invention

An aspect of one or more example embodiments includes a display device capable of realizing a high-quality image.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the exemplary embodiments presented in accordance with the disclosure.

A display apparatus according to some example embodiments of the present disclosure may include: an emission panel including first, second, third, and first power lines, wherein the first, second, and third light emitting diodes are each disposed in a pixel region and each have a stacked structure including a pixel electrode, a counter electrode, and an intermediate layer having an emission layer, and the first power lines are disposed in a laser drilling region around the pixel region and electrically connected to the first, second, and third light emitting diodes; and a color panel disposed on the emission panel and including a light blocking region and first, second, and third color regions each capable of transmitting light of a different color, wherein the column spacer is disposed between the emission panel and the color panel and has at least a portion overlapping the laser drilling region in a vertical direction.

According to some example embodiments, the intermediate layer may extend from the pixel region to the laser drilling region, and include a via hole in the laser drilling region, the counter electrode may integrally extend through the pixel region and the laser drilling region, and the first power line may be electrically connected to the counter electrode through the via hole in the laser drilling region.

According to some example embodiments, the thin film encapsulation layer may be disposed on the emission panel, the packing may be disposed on the color panel facing the emission panel, and the column spacers may be disposed in the packing, and at least a portion of the column spacers overlap the laser drilling region in which the counter electrode and the first power line are electrically connected.

According to some example embodiments, column spacers may be located in the laser drilled regions.

According to some example embodiments, portions of the column spacers may overlap the laser drilled regions.

According to some example embodiments, the connection electrode may be disposed on the same layer as the pixel electrode in the laser drilling region, an upper surface of the connection electrode may be electrically connected to the counter electrode, and a lower surface of the connection electrode may be electrically connected to the first power line.

According to some example embodiments, a first insulating layer covering at least a portion of the first power line may be disposed on the first power line, the connection electrode may be disposed on the first insulating layer, a second insulating layer may be disposed on the connection electrode, the second insulating layer covers at least a portion of the connection electrode and has an opening for the connection electrode, the intermediate layer may cover an outer surface of the second insulating layer, the via hole in the intermediate layer may overlap the opening for the connection electrode, and the counter electrode may be electrically connected to the first power line through the opening for the connection electrode in the second insulating layer and the via hole in the intermediate layer.

According to some example embodiments, a first insulating layer may be disposed on the first power line, the first insulating layer covering at least a portion of the first power line and having an opening for the first power line, the connection electrode may be disposed on the first insulating layer, a second insulating layer may be disposed on the connection electrode, the second insulating layer covering at least a portion of the connection electrode and having an opening for the connection electrode, the intermediate layer may cover the second insulating layer and the connection electrode, the via hole in the intermediate layer may overlap with the opening for the first power line and the opening for the connection electrode, and the counter electrode may be electrically connected to the first power line through the opening for the first power line in the first insulating layer, the opening for the connection electrode in the second insulating layer, and the via hole in the intermediate layer.

According to some example embodiments, a thin film transistor may be disposed in the pixel region, the thin film transistor is electrically connected to each of the first, second, and third light emitting diodes and has a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and the first power line may include a first conductive layer disposed on the same layer as the source electrode.

According to some example embodiments, a thin film transistor may be disposed in the pixel region, the thin film transistor is electrically connected to each of the first, second, and third light emitting diodes and has a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and the first power line may include a first conductive layer disposed on the same layer as the source electrode and a second conductive layer electrically connected to the first conductive layer.

According to some example embodiments, the conductive protective layer may cover the first power line.

According to some example embodiments, the color panel may include: a light blocking layer corresponding to the light blocking area; a color conversion transmission layer including a color conversion unit converting incident light into light of other colors and a transmission unit transmitting the incident light; and a color layer including a plurality of color filters stacked with the color conversion transmission layer.

According to some example embodiments, the color conversion unit may include a plurality of quantum dots.

According to some example embodiments, the first power lines may be arranged to be spaced apart from each other around a plurality of pixel regions arranged adjacently, and a region in which the laser drilling region and the column spacer overlap may be selectively arranged around the plurality of pixel regions.

A display apparatus according to some example embodiments of the present disclosure includes: a first substrate including a plurality of pixel regions and a laser drilling region disposed around each pixel region; a light emitting diode disposed in the pixel region, electrically connected to the thin film transistor, and having a stacked structure including a pixel electrode, a counter electrode, and an intermediate layer having an emission layer; a first power line disposed in the laser drilling area and electrically connected to the light emitting diode; the thin film packaging layer covers the pixel area and the laser drilling area; a second substrate including a light blocking region and first, second, and third color regions each capable of transmitting light of different colors; a filler covering the first color region, the second color region, the third color region, and the light blocking region; and column spacers arranged in the packing, wherein at least a portion of the column spacers may overlap the laser drilled region in a vertical direction.

According to some example embodiments, the filler may face the thin film encapsulation layer, and at least a portion of the column spacers may overlap the laser-drilled region in which the counter electrode and the first power line are electrically connected.

According to some example embodiments, column spacers may be located in the laser drilled regions.

According to some example embodiments, portions of the column spacers may overlap the laser drilled regions.

According to some example embodiments, the intermediate layer may extend from the pixel region to the laser drilling region and have a via hole in the laser drilling region, the counter electrode may integrally extend through the pixel region and the laser drilling region, and the first power line may be electrically connected to the counter electrode through the via hole in the laser drilling region.

According to some example embodiments, the connection electrode may be disposed on the same layer as the pixel electrode in the laser drilling region, an upper surface of the connection electrode may be electrically connected to the counter electrode, and a lower surface of the connection electrode may be electrically connected to the first power line.

Drawings

The above and other aspects, features and characteristics of certain exemplary embodiments of the disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

fig. 1A and 1B are schematic plan views of a display device according to some example embodiments;

fig. 2A and 2B are equivalent circuit diagrams of pixels that may be included in the display devices of fig. 1A and 1B, according to some example embodiments;

FIG. 3 is a cross-sectional view of a portion of a display device according to some example embodiments;

FIG. 4 is an enlarged cross-sectional view of portion A of the display device of FIG. 3, according to some example embodiments;

FIG. 5 is a plan view illustrating the laser drilled regions and column spacers of FIG. 3 stacked on top of one another according to some example embodiments;

FIG. 6 is a modification of FIG. 3, in accordance with some example embodiments;

FIG. 7 is a plan view illustrating the laser drilled regions and column spacers of FIG. 6 stacked on top of one another according to some example embodiments;

FIG. 8 is a cross-sectional view of a display device according to some example embodiments;

FIG. 9 is a cross-sectional view of a display device according to some example embodiments;

FIG. 10 is a plan view illustrating laser drilling regions and column spacers stacked on top of one another according to some example embodiments; and

fig. 11 and 12 are diagrams of electronic apparatuses including display devices according to some example embodiments.

Detailed Description

Reference will now be made in greater detail to aspects of some example embodiments that are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the example embodiments are described below merely by referring to the figures to explain aspects of the description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b and c" means all or a variation of only a, only b, only c, both a and b, both a and c, both b and c, a, b and c.

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Effects and features of the present disclosure and methods of achieving the same will be apparent with reference to the embodiments and the accompanying drawings described in detail below. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein.

It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component, for example, intervening layers, regions or components may be present. The size of components in the drawings may be exaggerated for convenience of explanation. In other words, since the sizes and thicknesses of elements in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

The X, Y and Z axes are not limited to the three axes of the rectangular coordinate system and may be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

Although terms such as "first," "second," and the like may be used to describe various elements, such elements are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another component.

In the following exemplary embodiments, expressions used in the singular number encompass expressions of plural numbers unless they have a clearly different meaning in context.

In the following example embodiments, it will be understood that terms such as "including" and "having" are intended to indicate the presence of the features or elements disclosed in the present disclosure, and are not intended to exclude the possibility that one or more other features or elements may be present or may be added.

When an embodiment may be implemented differently, the specific process sequence may be performed differently than described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order to that described.

Aspects of some example embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and thus the description thereof will be omitted.

It will be understood that when a layer, region or component is referred to as being connected to another layer, region or component, it can be directly or indirectly connected to the other layer, region or component. That is, for example, there may be intervening layers, intervening regions, or intervening components. For example, it will be understood that when a layer, region or component is referred to as being electrically connected to another layer, region or component, it can be directly or indirectly electrically connected to the other layer, region or component. That is, for example, there may be intervening layers, intervening regions, or intervening components.

Fig. 1A and 1B are schematic plan views of a display device 100 according to some example embodiments.

Referring to fig. 1A, the display apparatus 100 may be an apparatus configured to display an image. The display device 100 includes a first substrate 101 and a second substrate 102. The sealing member 103 may be disposed between the first substrate 101 and the second substrate 102. The sealing member 103 may surround the peripheries of the first and second substrates 101 and 102 and bond the first substrate 101 to the second substrate 102.

The display device 100 includes a display area DA and a peripheral area PA extending around the display area DA (e.g., around the periphery of the display area DA or around the outside of the footprint of the display area DA). The display apparatus 100 may provide some images by using light emitted from a plurality of pixels (e.g., pixels P) arranged in the display area DA.

The display area DA includes a plurality of pixels P connected to data lines DL extending in the Y direction and scan lines SL extending in the X direction crossing the Y direction. Each pixel P may be connected to a driving voltage line PL extending in the Y direction.

Each of the plurality of pixels P may include a display element such as an Organic Light Emitting Diode (OLED). All of the OLEDs included in the plurality of pixels P may emit light of the same color, and the color of each pixel P may be realized by a color filter disposed on an upper portion of the OLED. According to some example embodiments, each pixel P may emit, for example, red, green, blue, or white light through the OLED.

Each pixel P may be electrically connected to a plurality of built-in circuits arranged in the peripheral area PA. For example, the first power line 104, the second power line 105, and a pad (or called "pad") unit 106 may be arranged in the peripheral area PA.

The first power line 104 may be disposed on one side of the display area DA, for example, may be disposed on a lower end of the display apparatus 100. The first power line 104 may be connected to a plurality of driving voltage lines PL that transfer the driving voltage ELVDD to the pixels P.

The second power line 105 may partially surround the display area DA in a ring shape with one side open. The second power line 105 may supply the common voltage ELVSS to the counter electrode of the pixel P.

The pad unit 106 may include a plurality of pads 107, and may be disposed on one side of the first substrate 101. Each of the pads 107 may be connected to a first connection line 108 connected to the first power supply line 104 or a connection wire CW extending to the display area DA. Each of the pads 107 may be electrically connected to a printed circuit board PCB. The printed circuit board terminal unit PCB-P of the printed circuit board PCB may be electrically connected to the pad unit 106.

The printed circuit board PCB may transmit signals or power of the controller to the pad unit 106. The controller may supply the driving voltage ELVDD and the common voltage ELVSS to the first power line 104 and the second power line 105 via the first connection line 108 and the second connection line 109, respectively.

The data driving circuit 110 is electrically connected to the data lines DL. The data signal of the data driving circuit 110 may be supplied to each pixel P through a connection wire CW connected to the pad unit 106 and a data line DL connected to the connection wire CW. Although fig. 1 shows that the data driving circuit 110 is disposed in the printed circuit board PCB, the data driving circuit 110 may be disposed over the first substrate 101 according to some example embodiments. For example, the data driving circuit 110 may be disposed between the pad unit 106 and the first power line 104.

The dam unit 111 may be disposed in the peripheral area PA. When forming the organic encapsulation layer 422 of the thin film encapsulation layer 419 of fig. 3, the dam unit 111 may prevent or reduce the formation of the edge tail of the organic encapsulation layer 422 by blocking the flow of the organic material in the edge direction of the first substrate 101. The dam unit 111 may surround at least a portion of the display area DA. The dam unit 111 may include a plurality of dams. When the dam unit 111 includes a plurality of dams, each dam may be spaced apart from each other. The dam unit 111 may be disposed closer to the display area DA than the sealing member 103.

Although fig. 1A shows one printed circuit board PCB attached to the pad unit 106, a plurality of printed circuit boards PCBs may be attached to the pad unit 106 as shown in fig. 1B. The pad units 106 may be disposed along both sides of the first substrate 101. The pad unit 106 may include a plurality of sub-pad units 106S, and each printed circuit board PCB may be attached to each sub-pad unit 106S.

Fig. 2A and 2B are equivalent circuit diagrams of a pixel P that may be included in the display device 100 of fig. 1A and 1B according to some example embodiments.

Referring to fig. 2A, each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and is configured to transmit a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a certain luminance according to a driving current.

Although fig. 2A shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, embodiments according to the present disclosure are not limited thereto.

Referring to fig. 2B, each pixel P may include an organic light emitting diode OLED and a pixel circuit PC including a plurality of thin film transistors driving the organic light emitting diode OLED. The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a sensing thin film transistor T3, and a storage capacitor Cst.

The scan line SL may be connected to the gate electrode G2 of the switching thin film transistor T2, the data line DL may be connected to the source electrode S2 of the switching thin film transistor T2, and the first electrode CE1 of the storage capacitor Cst may be connected to the drain electrode D2 of the switching thin film transistor T2. Accordingly, the switching thin film transistor T2 supplies the data voltage of the data line DL to the first node N in response to the scan signal Sn from the scan line SL of each pixel P.

The gate electrode G1 of the driving thin film transistor T1 may be connected to the first node N, the source electrode S1 of the driving thin film transistor T1 may be connected to a driving voltage line PL configured to deliver a driving voltage ELVDD, and the drain electrode D1 of the driving thin film transistor T1 may be connected to the anode electrode of the organic light emitting diode OLED. Accordingly, the driving thin film transistor T1 may adjust the amount of current flowing to the organic light emitting diode OLED according to the voltage between the source electrode S1 and the gate electrode G1 of the driving thin film transistor T1 (i.e., the voltage between the driving voltage ELVDD and the first node N).

The sensing control line SSL is connected to the gate electrode G3 of the sensing thin film transistor T3, the source electrode S3 of the sensing thin film transistor T3 is connected to the second node S, and the drain electrode D3 of the sensing thin film transistor T3 is connected to the reference voltage line RL. According to some example embodiments, the sensing thin film transistor T3 may be controlled by the scan line SL instead of the sensing control line SSL.

The sensing thin film transistor T3 may sense a potential of a pixel electrode (e.g., an anode electrode) of the organic light emitting diode OLED. The sensing thin film transistor T3 supplies the pre-charge voltage Vpre from the reference voltage line RL to the second node S or supplies the voltage of the pixel electrode (e.g., anode electrode) of the organic light emitting diode OLED to the reference voltage line RL in response to the sensing signal SSn from the sensing control line SSL during the sensing period.

The first electrode CE1 of the storage capacitor Cst is connected to the first node N, and the second electrode CE2 of the storage capacitor Cst is connected to the second node S. The storage capacitor Cst is charged with a voltage difference between voltages respectively supplied to the first node N and the second node S, and supplies the charged voltage difference as a driving voltage for driving the thin film transistor T1. For example, the storage capacitor Cst may be charged with a voltage difference between the data voltage and the precharge voltage Vpre supplied to the first node N and the second node S, respectively.

The bias electrode BSM may be formed to correspond to the driving thin film transistor T1, and may be connected to the source electrode S3 of the sensing thin film transistor T3. The bias electrode BSM may receive a voltage associated with the potential of the source electrode S3 of the sensing thin film transistor T3, and thus, the driving thin film transistor T1 may be stably. According to some example embodiments, the bias electrode BSM may not be connected to the source electrode S3 of the sensing thin film transistor T3, but may be connected to a separate bias line.

A counter electrode (e.g., a cathode electrode) of the organic light emitting diode OLED receives the common voltage ELVSS. The organic light emitting diode OLED receives the driving current from the driving thin film transistor T1 to emit light.

Although fig. 2B illustrates that each pixel P includes the signal lines SL, SSL, and DL, the reference voltage line RL, and the driving voltage line PL, embodiments according to the present disclosure are not limited thereto. For example, at least one of the signal lines SL, SSL, and DL, the reference voltage line RL, and the driving voltage line PL may be shared by adjacent pixels.

The pixel circuit PC is not limited to the number of thin film transistors and storage capacitors and the circuit design described with reference to fig. 2A and 2B, and the number of thin film transistors and storage capacitors and the circuit design may be variously changed. That is, according to some example embodiments, the number of electronic components shown in fig. 2A and 2B may vary, and additional or fewer electronic components may be present, without departing from the spirit and scope of embodiments according to the present disclosure.

Fig. 3 is a cross-sectional view of a portion of a display device 300 according to some example embodiments.

The display device 300 of fig. 3 may be a cross-sectional view of a portion of the display area DA taken along the line III-III' of fig. 1A. The driving thin film transistor T1 and the storage capacitor Cst in the pixel circuit PC of the above-described pixel P are shown in the display area DA of fig. 3.

Referring to fig. 3, the display apparatus 300 includes an emission panel 400 and a color panel 500.

A plurality of pixel areas PX (e.g., a first pixel area PX1, a second pixel area PX2, and a third pixel area PX3) may be arranged in the emission panel 400. This is merely an example, and the display device 300 may include more pixel areas PX. Although the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 are illustrated as being adjacent to each other in fig. 3, embodiments according to the present disclosure are not limited thereto. The cross sections of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may not be cross sections in the same direction.

The first, second, and third organic light emitting diodes OLED1, OLED2, and OLED3 are respectively arranged corresponding to the first, second, and third pixel regions PX1, PX2, and PX 3. The pixel area PX may correspond to an emission area of the organic light emitting diode OLED. The laser drilling area LD (e.g., the first laser drilling area LD1, the second laser drilling area LD2, or the third laser drilling area LD3) in which the first power line 414 is arranged may be arranged around each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3, respectively. The laser drilling area LD may be a part of the non-pixel area NPX (refer to fig. 5).

Hereinafter, since the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 include elements having the same stack structure, the first pixel area PX1 will be described as an example.

The emission panel 400 includes a first substrate 401. The first substrate 401 may include a material such as glass, ceramic, metal, or polymer. The first buffer layer 402 may be disposed on the first substrate 401. The first buffer layer 402 may block penetration of foreign substances or moisture through the first substrate 401. For example, the first buffer layer 402 may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers.

A bias electrode 403 (BSM in fig. 2B) may be disposed on the first buffer layer 402 to correspond to the driving thin film transistor T1. The bias electrode 403 may overlap the semiconductor layer a1 of the driving thin film transistor T1. A voltage may be applied to bias electrode 403. For example, the bias electrode 403 may be connected to the source electrode (S3 in fig. 2B) of the sensing thin film transistor (T3 in fig. 2B), and the voltage of the source electrode S3 may be applied to the bias electrode 403. In addition, the bias electrode 403 may prevent or reduce external light from reaching the semiconductor layer a 1. Therefore, the characteristics of the driving thin film transistor T1 can be stabilized. According to some example embodiments, the bias electrode 403 may be omitted.

The second buffer layer 404 may cover the bias electrode 403. The second buffer layer 404 may be disposed throughout the entire region of the first substrate 401. The second buffer layer 404 may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers.

The semiconductor layer a1 may be disposed on the second buffer layer 404. The semiconductor layer a1 may include polysilicon, amorphous silicon, an oxide semiconductor, an organic semiconductor material, or the like. According to some example embodiments, the semiconductor layer a1 may include a channel region overlapping with the gate electrode G1 of the driving thin film transistor T1, source and drain regions respectively disposed on both sides of the channel region and including impurities at a higher concentration than that of the channel region. The impurity may include an N-type impurity or a P-type impurity.

The gate insulating layer 405 may cover the semiconductor layer a 1. The gate insulating layer 405 may include an inorganic material such as silicon oxynitride, silicon oxide, and silicon nitride, and may include a single layer or multiple layers. The gate electrode G1 may be disposed on the gate insulating layer 405. The gate electrode G1 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The gate electrode G1 may include a single layer or multiple layers.

The first electrode CE1 of the storage capacitor Cst may be disposed on the same layer as the gate electrode G1. The first electrode CE1 may include the same material as that of the gate electrode G1. For example, according to some example embodiments, the first electrode CE1 and the gate electrode G1 may be deposited or formed as part of the same deposition operation, although embodiments are not limited thereto.

The first interlayer insulating layer 406 may cover the gate electrode G1 and the first electrode CE1 of the storage capacitor Cst. The first interlayer insulating layer 406 may include an inorganic material such as silicon oxynitride, silicon oxide, and silicon nitride. The first interlayer insulating layer 406 may include a single layer or a plurality of layers.

The source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL may be disposed on the first interlayer insulating layer 406. The source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL may include Al, Cu, Ti, etc., and may include a single layer or multiple layers. According to some example embodiments, the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL may include a multilayer of Ti/Al/Ti. The source electrode S1 and the drain electrode D1 may be connected to the source region and the drain region of the semiconductor layer a1 through contact holes, respectively. The source electrode S1 may be connected to the driving voltage line PL.

The second electrode CE2 of the storage capacitor Cst may overlap the first electrode CE1 with the first interlayer insulating layer 406 therebetween to form a capacitance. In this case, the first interlayer insulating layer 406 may perform a function of a dielectric layer of the storage capacitor Cst. The thickness of the first interlayer insulating layer 406 may be designed according to the capacitance value of the storage capacitor Cst.

The protective layer 407 may cover the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL. The protective layer 407 may include an inorganic material such as silicon oxynitride, silicon oxide, and silicon nitride. The protective layer 407 may protect a conductive layer or a line disposed on the first interlayer insulating layer 406.

The first insulating layer 408 may be disposed on the protective layer 407. The first insulating layer 408 may be a planarization layer. The first insulating layer 408 may include an organic material, and the organic material may include an imide polymer, a general commercial polymer such as poly (methyl methacrylate) or polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof. According to some example embodiments, the first insulating layer 408 may include polyimide.

When the protective layer 407 including an inorganic material is omitted, a conductive layer or a line (such as the driving voltage line PL) may be oxidized or corroded by reacting with oxygen permeated from the first insulating layer 408. However, in embodiments in which the protective layer 407 is included as shown, for example, in fig. 3, a conductive layer or line (such as the driving voltage line PL) may not directly contact the first insulating layer 408.

In the first pixel region PX1, the first organic light emitting diode OLED1 may be disposed on the first insulating layer 408. The first organic light emitting diode OLED1 includes a pixel electrode 409, an intermediate layer 410 including an emission layer, and a counter electrode 411.

The pixel electrode 409 may be electrically connected to the drain electrode D1 through a contact hole penetrating the first insulating layer 408. The pixel electrode 409 may be connected to the drain electrode D1 via the conductive protective layer 413. The conductive protection layer 413 may cover the drain electrode D1. The conductive protection layer 413 may be a metal layer configured to prevent or reduce damage to the drain electrode D1.

The pixel electrode 409 may be a (semi-) transparent electrode or a reflective electrode. According to some example embodiments, the pixel electrode 409 may include a reflective layer and a shapeAnd a transparent or semitransparent electrode layer formed on the reflective layer, wherein the reflective layer comprises silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), a composite thereof, and the like. The transparent or semitransparent electrode layer may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) At least one of Indium Gallium Oxide (IGO) and Aluminum Zinc Oxide (AZO). According to some example embodiments, the pixel electrode 409 may be ITO/Ag/ITO.

A second insulating layer 412 may be disposed on the first insulating layer 408. The second insulating layer 412 may be a pixel defining film. The second insulating layer 412 may have an opening OPp for the pixel electrode 409 exposing a portion of the pixel electrode 409, thereby defining an emission area. The second insulating layer 412 may include an organic material such as polyimide or hexamethyldisiloxane.

The intermediate layer 410 may include an emission layer. According to some example embodiments, the intermediate layer 410 may be commonly disposed in the first, second, and third organic light emitting diodes OLED1, OLED2, and OLED3 respectively disposed in the first, second, and third pixel regions PX1, PX2, and PX 3. Accordingly, the first, second, and third organic light emitting diodes OLED1, OLED2, and OLED3 may emit the same color light. For example, the intermediate layer 410 may include an organic emission layer including a fluorescent material or a phosphorescent material emitting blue light.

Functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), etc. may also be selectively disposed above or below the emission layer. The intermediate layer 410 having an emission layer may integrally extend throughout the first, second, and third organic light emitting diodes OLED1, OLED2, and OLED 3.

The counter electrode 411 may be a transparent electrode or a reflective electrode. According to some example embodiments, the counter electrode 411 may be a transparent or translucent electrode, and may include a metal thin film having a small work function, including lithium (Li), calcium (Ca), lithium fluoride (LiF), Ag, Mg, and a composite thereof. In addition, theSuch as ITO, IZO, ZnO, In₂O₃Etc. a Transparent Conductive Oxide (TCO) film may also be disposed over the metal thin film. The counter electrode 411 may extend not only to the display area DA but also to the peripheral area PA outside the display area DA shown in fig. 1. The counter electrode 411 may be disposed on the intermediate layer 410.

The laser drilling area LD (e.g., the first laser drilling area LD1, the second laser drilling area LD2, or the third laser drilling area LD3) in which the first power line 414 is arranged may be arranged around each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3, respectively.

Hereinafter, since the first, second, and third laser drilling regions LD1, LD2, and LD3 include elements having the same stack structure, the first laser drilling region LD1 will be described as an example.

The first power line 414 may be disposed in the first laser drilling area LD 1. The first power line 414 may be a line to which the common voltage ELVSS is applied. Each of the first power lines 414 may extend in the Y direction (see, e.g., fig. 5), and a plurality of the first power lines 414 may be arranged to be spaced apart from each other in the X direction intersecting the Y direction. The first power line 414 may be disposed on the first interlayer insulating layer 406. The first power line 414 may be disposed on the same layer as the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL. The first power line 414 may include a conductive material such as Al, Cu, Ti, or the like, and may be formed of a single layer or a plurality of layers.

At least one of lower wires 415 and 416 may be disposed below first power line 414. For example, the first lower line 415 and the second lower line 416 may be disposed below the first power line 414. The first lower line 415 may be disposed on the same layer as that of the gate electrode G1, and may include the same material as that of the gate electrode G1. The second lower line 416 may be disposed on the same layer as that of the bias electrode 403 and may include the same material as that of the bias electrode 403. When the display device has a relatively large area, a voltage drop due to the self resistance or the internal resistance of the first power line 414 may occur. However, when first power line 414 is electrically connected to first lower line 415 and second lower line 416, a voltage drop due to the self-resistance of first power line 414 may be effectively prevented or reduced (e.g., minimized).

The conductive protection layer 417 may cover a portion of the first power line 414. The conductive protection layer 417 may cover the exposed portion of the first power line 414 to prevent or reduce damage to the first power line 414. The conductive protection layer 417 may include a multi-layer structure, and may be a conductive material or metal having a lower oxidation degree than that of a material disposed on the uppermost layer of the first power line 414, or a conductive material or metal having a higher corrosion resistance than that of a material disposed on the uppermost layer of the first power line 414.

According to some example embodiments, the uppermost layer of the first power line 414 may include copper, and the conductive protection layer 417 may include titanium. According to some example embodiments, the conductive protection layer 417 may include an oxide having conductivity. For example, the conductive protection layer 417 may include ITO, IZO, ZnO, In₂O₃At least one of IGO and AZO.

The first insulating layer 408 may cover the stacked first power lines 414 and the conductive protection layer 417. The connection electrode 418 may be disposed on the first insulating layer 408. The connection electrode 418 may be disposed on the same layer as that of the pixel electrode 409 and may include the same material as that of the pixel electrode 409. The connection electrode 418 may be connected to the first power line 414 through a contact hole penetrating the first insulating layer 408. The connection electrode 418 may be connected to the first power line 414 via the conductive protection layer 417.

The second insulating layer 412 may be disposed on the connection electrode 418. The second insulating layer 412 may have an opening OPc for the connection electrode 418 exposing a portion of the connection electrode 418. The second insulating layer 412 may cover edges of the connection electrode 418, and portions of the connection electrode 418 other than the edges may be exposed to the outside.

The intermediate layer 410 may be disposed on the second insulating layer 412. As described above, the intermediate layer 410 may be commonly disposed in the first, second, and third organic light emitting diodes OLED1, OLED2, and OLED3 respectively disposed in the first, second, and third pixel regions PX1, PX2, and PX 3. The intermediate layer 410 may extend as a single body from the first, second, and third pixel areas PX1, PX2, and PX3 to the first, second, and third laser drilling areas LD1, LD2, and LD3, respectively.

The intermediate layer 410 may include a via hole 410h overlapping with an opening OPc formed in the second insulating layer 412 for connecting the electrode 418. As shown in fig. 4 illustrating an enlarged view of the display device 100, the intermediate layer 410 may include a first functional layer 410a, an emission layer 410b, and a second functional layer 410 c. The through hole 410h may penetrate the first functional layer 410a, the emission layer 410b, and the second functional layer 410 c. The through-hole 410h may be formed through the first functional layer 410a, the emission layer 410b, and the second functional layer 410c by a laser drilling operation. The first functional layer 410a may include an HTL and/or an HIL, and the second functional layer 410c may include an ETL and/or an EIL.

The counter electrode 411 may be disposed on the intermediate layer 410. Like the intermediate layer 410, the counter electrode 411 may extend as a single body from the first, second, and third pixel regions PX1, PX2, and PX3 to the first, second, and third laser drilling regions LD1, LD2, and LD3, respectively.

The counter electrode 411 may be connected to the connection electrode 418 through the through hole 410h and the opening OPc for the connection electrode 418, and the through hole 410h and the opening OPc communicate with each other. The counter electrode 411 may be electrically connected to the first power line 414 via the connection electrode 418 and the conductive protection layer 417. Since the counter electrode 411 has a relatively large area to completely cover the display area DA shown in fig. 1, the resistance of the counter electrode 411 may vary according to the self-resistance of the counter electrode 411 in each area. However, when the first electric force lines 414 passing through the display area DA are electrically connected to the counter electrode 411, a voltage drop due to the self-resistance of the counter electrode 411 may be prevented or reduced.

The first, second, and third organic light emitting diodes OLED1, OLED2, and OLED3 may be easily damaged by moisture, oxygen, or the like from the outside. The thin film encapsulation layer 419 may cover the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED 3.

The thin film encapsulation layer 419 may extend not only to a portion of the display area DA shown in fig. 3 but also from the display area DA to the peripheral area PA shown in fig. 1. The thin film encapsulation layer 419 may include at least one of inorganic encapsulation layers 420 and 421 and at least one organic encapsulation layer 422. According to some example embodiments, the thin film encapsulation layer 419 may be a structure in which a first inorganic encapsulation layer 420, an organic encapsulation layer 422, and a second inorganic encapsulation layer 421 are sequentially stacked.

The first inorganic encapsulation layer 420 may cover the counter electrode 411 and may include silicon oxynitride, silicon oxide, silicon nitride, or the like. According to some example embodiments, other layers, such as a cap layer, may be disposed between the counter electrode 411 and the first inorganic encapsulation layer 420. The first inorganic encapsulation layer 420 is formed along the underlying structure, and the upper surface of the first inorganic encapsulation layer 420 may not be flat.

The organic encapsulation layer 422 may cover the first inorganic encapsulation layer 420. The thickness of the organic encapsulation layer 422 may be greater than the thickness of the first and second inorganic encapsulation layers 420 and 421. The organic encapsulation layer 422 may have a thickness sufficient to planarize steps in the first, second, and third pixel areas PX1, PX2, and PX3 and steps in the first, second, and third laser drilling areas LD1, LD2, and LD 3.

The organic encapsulation layer 422 may include at least one of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyvinylsulfonate, polyimide, polyarylate, polyoxymethylene, and hexamethyldisiloxane.

The second inorganic encapsulation layer 421 may cover the organic encapsulation layer 422, and may include silicon oxynitride, silicon oxide, silicon nitride, or the like.

Even when cracks occur in the thin film encapsulation layer 419, the connection of the cracks between the first inorganic encapsulation layer 420 and the organic encapsulation layer 422 or between the organic encapsulation layer 422 and the second inorganic encapsulation layer 421 may be prevented or reduced.

The light generated by the emission panel 400 having the above structure may be incident on the color panel 500. The incident light Lib on the color panel 500 may be converted into light having a different color or may be emitted to the outside in the same color.

The color panel 500 comprises a second substrate 501. The second substrate 501 may be a transparent substrate. The second substrate 501 may include transparent glass or transparent resin. The second substrate 501 may be a transparent glass substrate including silicon oxide as a main component. According to some example embodiments, the second substrate 501 may include a polymer resin. The polymer resin may include polymer resins such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, cellulose acetate propionate, and polycarbonate.

The first, second, and third color regions R, G, and B may be disposed on a lower surface of the second substrate 501 facing the emission panel 400. Although the first, second, and third color regions R, G, and B are illustrated adjacent to each other in fig. 3, embodiments according to the present disclosure are not limited thereto. In addition, the cross sections of the first color region R, the second color region G, and the third color region B may not be cross sections in the same direction. The light blocking area BA may be disposed between the first, second, and third color areas R, G, and B. The light blocking area BA may be an area through which light cannot pass, and may be arranged in a grid form between the first, second, and third color areas R, G, and B.

The first, second, and third color regions R, G, and B may correspond to the first, second, and third pixel regions PX1, PX2, and PX 3. The first, second, and third color regions R, G, and B may be distinguished according to the color of emitted light. For example, the first color region R may be a region emitting light of the first color Lr, the second color region G may be a region emitting light of the second color Lg, and the third color region B may be a region emitting light of the third color Lb.

The light of the first color Lr may be red light, the light of the second color Lg may be green light, and the light of the third color Lb may be blue light. The red light may have a peak wavelength of 580nm or more and less than 750nm, the green light may have a peak wavelength of 495nm or more and less than 580nm, and the blue light may have a peak wavelength of 400nm or more and less than 495 nm.

The incident light Lib may be light of the third color Lb, and the incident light Lib may be converted or transmitted through the first, second, and third color regions R, G, and B. Accordingly, light of the first, second, and third colors Lr, Lg, and Lb may be emitted through the color panel 500.

The color panel 500 may include a light blocking layer 502, a color layer 505, and a color conversion transmission layer 510 disposed on a lower surface of a second substrate 501.

The light blocking layer 502 may include a first light blocking layer 503 and a second light blocking layer 504.

The first light-blocking layer 503 and the second light-blocking layer 504 may have black or white, or may have various colors including black or blue, for example. For example, one of the first light-blocking layer 503 and the second light-blocking layer 504 may be black, and the other may be black or blue. According to some example embodiments, the first light-blocking layer 503 and the second light-blocking layer 504 may have the same color. The first light-blocking layer 503 and the second light-blocking layer 504 may include an opaque inorganic material such as chromium oxide or molybdenum oxide, or may include an opaque organic insulating material such as black resin. The first light-blocking layer 503 and/or the second light-blocking layer 504 may include an organic insulating material such as white resin, blue resin, or the like. When the first light-blocking layer 503 includes a blue organic insulating material, the first light-blocking layer 503 may include the same material as that of the third color filter 508 and may be formed in the same operation as that of the third color filter 508.

The first light blocking layer 503 may be disposed on a lower surface of the second substrate 501. The first openings OP1 may be disposed between the first light-blocking layers 503, and the color layer 505 may be disposed in the first opening OP 1.

The color layer 505 may be a pattern of organic material including a dye or pigment. The color layer 505 may include a color filter arranged for each pixel area PX. In detail, the color layer 505 may include a first color filter 506 disposed in the first pixel area PX1, a second color filter 507 disposed in the second pixel area PX2, and a third color filter 508 disposed in the third pixel area PX 3.

The first color filter 506 may include a pigment or dye of a first color (e.g., red). The first color filter 506 may be formed by forming a first photosensitive color layer including a pigment or dye of a first color and then patterning the first photosensitive color layer. The second color filter 507 may include a pigment or dye of a second color (e.g., green). The second color filter 507 may be formed by forming a second photosensitive color layer including a pigment or dye of a second color and then patterning the second photosensitive color layer. The third color filter 508 may include a pigment or dye of a third color (e.g., blue). The third color filter 508 may be formed by forming a third photosensitive color layer including a pigment or dye of a third color (e.g., blue) and then patterning the third photosensitive color layer.

A first capping layer 509 may be disposed on lower surfaces of the first light blocking layer 503 and the color layer 505. The first capping layer 509 may cover the first color filter 506, the second color filter 507, and the third color filter 508. The first capping layer 509 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

The second light-blocking layer 504 may be disposed on the lower surface of the first cap layer 509. The second opening OP2 may be disposed between the second light-blocking layers 504, and the color conversion transmission layer 510 may be located in the second opening OP 2.

The color conversion transmissive layer 510 may be arranged in an area corresponding to the color layer 505 in the vertical direction of the display device 300. The color conversion transmission layer 510 may include a color conversion unit 511 or 512 or a transmission unit 513 arranged for each pixel area PX. In detail, the color conversion transmissive layer 510 may include a first color conversion unit 511 disposed in the first pixel region PX1, a second color conversion unit 512 disposed in the second pixel region PX2, and a transmissive unit 513 disposed in the third pixel region PX 3.

When the first color conversion unit 511 overlaps the first color filter 506 in the first pixel area PX1, the incident light Lib may be converted into light of the first color Lr. The first color conversion unit 511 may include first quantum dots that may be excited by incident light Lib and emit light of a first color Lr having a wavelength longer than that of the incident light Lib.

When the second color conversion unit 512 is overlapped with the second color filter 507 in the second pixel area PX2, the incident light Lib may be converted into light of the second color Lg. The second color conversion unit 512 may include second quantum dots that may be excited by the incident light Lib and emit light of a second color Lg having a wavelength longer than that of the incident light Lib.

The first and second quantum dots are semiconductor particles having only a diameter of 2nm to 10nm, and may be particles having unusual electrical and optical properties. When the first and second quantum dots are exposed to light, the first and second quantum dots may emit light of a specific frequency according to a particle size and a material type. For example, quantum dots may emit red, green, and blue light depending on particle size and/or material type when receiving light. The core of the first and second quantum dots may be selected from the group consisting of group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

When the transmission unit 513 is overlapped with the third color filter 508 in the third pixel area PX3, the incident light Lib may be transmitted. Accordingly, light of the third color Lb may be emitted through the transmission unit 513 and the third color filter 508. The light of the third color Lb is blue light having a peak wavelength in the same wavelength range as that of the incident light Lib.

The first color conversion unit 511, the second color conversion unit 512, and the transmission unit 513 may include a plurality of scattering particles configured to improve light efficiency. The scattering particles may be titanium oxide (TiO)₂) Or metal particles.

The first color conversion unit 511, the second color conversion unit 512, and the transmission unit 513 may be respectively formed in the second openings OP2 defined by the second light-blocking layer 504 by an inkjet method.

A second cover layer 514 may be disposed on the lower surfaces of the second light-blocking layer 504 and the color conversion transmissive layer 510. The second capping layer 514 may cover the first color conversion unit 511, the second color conversion unit 512, and the transmission unit 513. The second cap layer 514 may comprise an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

The filler 515 may be disposed between the emission panel 400 and the color panel 500. An upper surface of the filler 515 may be in contact with a lower surface of the second cover layer 514, and a lower surface of the filler 515 may be in contact with the second inorganic encapsulation layer 421 of the thin film encapsulation layer 419. The packing 515 may serve as a buffer against external pressure. The filler 515 may include an organic material such as methyl silicone, phenyl silicone, polyimide, or the like. However, the filler 515 is not limited thereto. The filler 515 may include a urethane resin, an epoxy resin, an acrylic resin, or a silicon compound as an organic sealant. According to some example embodiments, the filler 515 may be a transmissive insulating layer or an air layer.

Column spacers 516 may be disposed in the packing 515. The column spacers 516 may maintain the interval between the emission panel 400 and the color panel 500. The column spacers 516 may be at least one organic insulating material including, for example, polyimide, polyamide, acrylic, benzocyclobutene, and phenol resin. The column spacer 516 is not limited to any one material as long as it is an insulating material that can maintain the interval between the emission panel 400 and the color panel 500.

The column spacers 516 may be arranged around each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX 3. At least a portion of the column spacers 516 may overlap the first, second, and third laser drilling regions LD1, LD2, and LD3 in a vertical direction of the display apparatus 300. In the first to third laser drilling areas LD1 to LD3, the counter electrode 411 may be electrically connected to the first power line 414 via the connection electrode 418 and the conductive protection layer 417. The column spacers 516 may be positioned in a region where the counter electrode 411 and the first power line 414 are connected.

Referring to fig. 5, the first pixel area PX1 and the second pixel area PX2 may be arranged to be spaced apart from each other by a distance in the X direction, and the second pixel area PX2 and the third pixel area PX3 may be arranged to be spaced apart from each other by a distance in the Y direction. The first, second, and third pixel regions PX1, PX2, and PX3 may be surrounded by a non-pixel region NPX. The non-pixel region NPX may include a laser drilling region LD.

The first electric flux lines 414 may be electrically connected to the counter electrode (411 in fig. 3) through the through-hole 410h and the opening OPc for connecting the electrode (418 in fig. 3) in the laser drilling region LD. Column spacers 516 may be located in the laser drilling region LD.

In detail, the thin film encapsulation layer (419 in fig. 3) may have a thickness that may planarize the upper surface of the emission panel 400. When the uppermost layer of the emission panel 400 is planarized due to the thickness of the thin film encapsulation layer 419, the column spacers 516 may not need to be arranged not to overlap the laser drilling regions LD. Accordingly, the column spacers 516 may be moved from the portion B indicated by the dotted line region to be positioned in the laser drilling region LD. The column spacers 516 may completely overlap the laser drilling region LD to which the counter electrode 411 and the first power line 414 are connected.

As the display apparatus 300 increases with high resolution, a space in which the color layer 505 and the color conversion transmission layer 510 disposed on the second substrate 501 may be patterned may be insufficient. When the column spacers 516 overlap the laser drilling region LD, the degree of freedom in designing elements such as the color layer 505, the color conversion transmission layer 510, and the like can be increased. In addition, it is also possible to secure a space in which the pixel area PX on the second substrate 501 can be designed, thereby increasing the aperture ratio.

Fig. 6 illustrates a display device 600 according to some example embodiments.

The display apparatus 600 of fig. 6 is substantially the same structure as that of the display apparatus 300 of fig. 3 except for a portion in which the column spacers 616 overlap the laser drilling region LD, and thus, differences thereof will be mainly described below. The same reference numerals as those in fig. 3 denote the same members.

Referring to fig. 6, on the first substrate 401, laser drilling regions LD (such as a first laser drilling region LD1, a second laser drilling region LD2, and a third laser drilling region LD3) may be arranged around each of a first pixel region PX1, a second pixel region PX2, and a third pixel region PX 3.

The first power line 414 may be disposed in the laser drilling area LD. The first power line 414 may be a line to which the common voltage ELVSS is applied. The first electric line of force 414 may be electrically connected to the counter electrode 411 via the conductive protection layer 417 and the connection electrode 418.

A thin film encapsulation layer 419 may be disposed on the uppermost layer of the first substrate 401. According to some example embodiments, the thin film encapsulation layer 419 may be a structure in which a first inorganic encapsulation layer 420, an organic encapsulation layer 422, and a second inorganic encapsulation layer 421 are sequentially stacked.

The first, second, and third color regions R, G, and B may be disposed on a lower surface of the second substrate 501 facing the first substrate 401. The first, second, and third color regions R, G, and B may correspond to the first, second, and third pixel regions PX1, PX2, and PX 3. The first, second, and third color regions R, G, and B may be covered by the filler 615. The lower surface of the filler 615 may be in contact with the upper surface of the thin film encapsulation layer 419.

Column spacers 616 may be disposed in the packing 615. The column spacers 616 may maintain the spacing between the emission panel 400 and the color panel 500. At least a portion of the column spacers 616 may overlap the first, second, and third laser drilling regions LD1, LD2, and LD3 in a vertical direction of the display apparatus 600. The column spacers 616 may be located in a region where the counter electrode 411 and the first power lines 414 are connected.

Referring to fig. 7, the first power line 414 may extend from the non-pixel region NPX in the Y direction. The non-pixel region NPX may include a laser drilling region LD. The first electric flux line 414 may be electrically connected to the counter electrode (411 in fig. 3) through the through hole 410h and the opening OPc for connecting the electrode (418 of fig. 6) in the laser drilling region LD.

The column spacers 616 may move from the portion C indicated by the dotted line region to the laser drilling region LD. At this time, the column spacers 616 are not located in the laser-drilled region LD as in the case of fig. 3, but a portion of the column spacers 616 (e.g., a portion corresponding to a semicircular region of the column spacers 616) may overlap the laser-drilled region LD. In other words, the column spacers 616 may not completely overlap the laser-drilled region LD, and at least a portion of the column spacers 616 may overlap the laser-drilled region LD. Even when at least a portion of the column spacers 616 overlaps the laser drilling region LD, space utilization in other regions of the non-pixel region NPX is increased. As a result, the degree of freedom in designing elements such as the color layer 505, the color conversion transmissive layer 510, and the like can be increased.

Fig. 8 is a cross-sectional view of a display device 800 according to some example embodiments.

The display apparatus 800 of fig. 8 is substantially the same structure as that of the display apparatus 300 of fig. 3 except for the stacked structure of the laser drilling area LD, and thus, differences thereof will be mainly described below. The same reference numerals as those in fig. 3 denote the same members.

Referring to fig. 8, a first power line 414 may be disposed in the first laser drilling area LD 1. The first power line 414 may be a line to which the common voltage ELVSS is applied. The first power line 414 may be disposed on the first interlayer insulating layer 406. The first power line 414 may be disposed on the same layer as the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL.

The protective layer 407 may cover the edge of the first power line 414. The conductive protection layer 417 may be disposed on the exposed portion of the first power line 414.

The first insulating layer 808 may include an opening OPf for the first power line 414 exposing a portion of the stacked first power line 414 and/or a portion of the conductive protection layer 417. The first insulating layer 808 may cover an edge of the conductive protection layer 417, and a portion of the conductive protection layer 417 other than the edge may be exposed to the outside. When the conductive protection layer 417 is omitted, a portion of the first power line 414 may be exposed to the outside.

The connection electrode 818 may be disposed on an outer surface of the first insulating layer 808. The connection electrode 818 may be disposed on the same layer as that of the pixel electrode 409 and may include the same material as that of the pixel electrode 409. The connection electrode 818 may be connected to the first power line 414 via an opening OPf for the first power line 414. The connection electrode 818 may be connected to the first power line 414 via the conductive protection layer 417.

The second insulating layer 812 may be disposed on the connection electrode 818. The second insulating layer 812 may include an opening OPc for the connection electrode 818, exposing a portion of the connection electrode 818. The opening OPc for the connection electrode 818 in the second insulating layer 812 may overlap with the opening OPf for the first power line 414 in the first insulating layer 808. The second insulating layer 812 may cover an edge of the connection electrode 818, and a portion of the connection electrode 818 other than the edge may be exposed to the outside.

The intermediate layer 410 may be disposed on the second insulating layer 812. The intermediate layer 410 may integrally extend from the first pixel area PX1 to the first laser drilling area LD 1. The intermediate layer 410 may cover the second insulating layer 812 and the connection electrode 818. The intermediate layer 410 may include a via 410h overlapping the opening OPc for the connection electrode 818 and the opening OPf for the first electric field line 414. The through-hole 410h may be formed through the intermediate layer 410 by a laser drilling operation.

The counter electrode 411 may be connected to the connection electrode 818 through the opening OPf for the first power line 414 in the first insulating layer 808, the opening OPc for the connection electrode 818 in the second insulating layer 812, and the via hole 410h in the intermediate layer 410. The counter electrode 411 may be electrically connected to the first power line 414 via the connection electrode 818 and the conductive protection layer 417.

Fig. 9 is a cross-sectional view of a display device 900 according to some example embodiments.

The display apparatus 900 of fig. 9 is substantially the same structure as that of the display apparatus 300 of fig. 3 except for the stacked structure of the first power line 914, and thus, differences thereof will be mainly described below. The same reference numerals as those in fig. 3 denote the same members.

Referring to fig. 9, the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL may be disposed on the first interlayer insulating layer 406. The source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL may be disposed on the same layer.

A second interlayer insulating layer 907 may be disposed on the first interlayer insulating layer 406. The second interlayer insulating layer 907 may cover the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL. The auxiliary driving voltage line PL' may be disposed on the second interlayer insulating layer 907. The auxiliary driving voltage line PL 'may be in contact with the driving voltage line PL disposed under the auxiliary driving voltage line PL' or the source electrode S1 of the driving thin film transistor T1 through a contact hole penetrating the second interlayer insulating layer 907. The auxiliary driving voltage line PL' may be connected to the driving voltage line PL to serve as a line configured to transfer the driving voltage. Since the auxiliary driving voltage line PL' is provided, a voltage drop phenomenon of the driving voltage can be prevented or reduced. In general, the display device 900 may be provided with a uniform driving voltage.

The first power line 914 may be disposed in the first laser drilling area LD 1. The first power line 914 may be a line to which the common voltage ELVSS is applied. The first power line 914 may include a first conductive layer 915 and a second conductive layer 916 disposed on a different layer than the first conductive layer 915.

A first conductive layer 915 may be disposed on the first interlayer insulating layer 406. The first conductive layer 915 may be disposed on the same layer as the source electrode S1, the drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL.

The second interlayer insulating layer 907 may cover the first conductive layer 915. A second conductive layer 916 may be disposed on the second interlayer insulating layer 907. The second conductive layer 916 may be disposed on the same layer as the auxiliary driving voltage line PL'. The second conductive layer 916 may be in contact with the first conductive layer 915 through a contact hole penetrating the second interlayer insulating layer 907. A protective layer 908 comprising an inorganic material may cover the second conductive layer 916. A conductive protection layer 417 may be disposed on the exposed portion of the second conductive layer 916. The conductive protection layer 417 may cover the exposed portion of the second conductive layer 916.

The counter electrode 411 may be connected to the connection electrode 418 through the communicating through hole 410h and the opening OPc for the connection electrode 418. The counter electrode 411 may be electrically connected to a first power line 914 including a first conductive layer 915 and a second conductive layer 916 via the connection electrode 418 and the conductive protection layer 417.

Fig. 10 is a plan view illustrating the laser drilling regions LD and the column spacers 516 stacked on each other according to some example embodiments.

Referring to fig. 10, a plurality of first power lines 414 may be arranged spaced apart from each other in the display area DA. The opening OP corresponding to the opening OPc for the connection electrode 418 formed in the second insulating layer 412 of fig. 3 may overlap the first electric line of force 414. The through-hole h corresponding to the through-hole 410h formed in the intermediate layer 410 of fig. 3 may overlap the opening OP.

The virtual units VU may be repeatedly arranged in the display area DA. Positions where the counter electrode (411 of fig. 3) and the first power lines 414 are electrically connected (e.g., overlapping portions of the opening OP and the through-hole h) may be located at four corners of the virtual unit VU having M × N. Among the plurality of openings OP in the M × N virtual cells VU, the opening OP in which the via h is not formed may have a dummy connection structure.

The column spacers 516 may be located in the laser drilling region LD which is a region where the counter electrode 411 and the first power lines 414 are connected. At least a portion of the column spacers 516 may overlap the laser drilling region LD in which the opening OP overlaps the via hole h.

Fig. 11 and 12 are diagrams of electronic apparatuses including display devices 1100 and 1200 according to some example embodiments.

Referring to fig. 11 and 12, the display apparatuses 1100 and 1200 may be provided in an electronic device such as a television or a monitor, or in an electronic device such as a laptop computer. Alternatively, the display apparatuses 1100 and 1200 may be used in various electronic devices such as a smart photo frame or a large billboard.

The display apparatuses 1100 and 1200 are not only used in electronic devices having a horizontally long rectangular screen. For example, the display apparatuses 1100 and 1200 may be used in an electronic device having a vertically long rectangular screen.

The display apparatus according to some example embodiments of the present disclosure may implement a display apparatus in which the spatial utilization of a substrate is relatively improved because a laser drilling region overlaps a column spacer.

In addition to the above description, the characteristics of the embodiments according to the present disclosure can be understood by the contents described with reference to the drawings.

It should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each embodiment should generally be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the following claims and their equivalents.