阅读说明：本技术 可选择开机bios之控制电路 (Control circuit capable of selecting boot BIOS ) 是由 王祥铭 于 2020-05-15 设计创作，主要内容包括：一种可选择开机BIOS之控制电路,适用于处理单元模块以及载板之电子装置。处理单元模块包括处理单元以及储存第一BIOS的第一存储器单元,载板包括储存第二BIOS的第二存储器单元。控制电路包括第一、第二跨接器、非门以及或门,非门接收第一跨接器的第一设定电压位准,或门接收第二跨接器的第二设定电压位准以及非门之输出。或门的输出端耦接至第一、第二模拟开关的控制端,而第一、第二模拟控制开关根据或门之输出端的讯号将处理单元的第一、第二芯片选择端选择性地电性连接至第一、第二存储器单元的从属选择端。(A control circuit capable of selecting a power-on BIOS is suitable for processing a unit module and an electronic device of a carrier board. The processing unit module comprises a processing unit and a first memory unit for storing a first BIOS, and the carrier plate comprises a second memory unit for storing a second BIOS. The control circuit comprises a first jumper, a second jumper, a NOT gate and an OR gate, wherein the NOT gate receives a first set voltage level of the first jumper, and the OR gate receives a second set voltage level of the second jumper and an output of the NOT gate. The output end of the OR gate is coupled to the control ends of the first and second analog switches, and the first and second analog control switches selectively and electrically connect the first and second chip selection ends of the processing unit to the slave selection ends of the first and second memory units according to the signal at the output end of the OR gate.)

1. A control circuit capable of selecting a boot BIOS is applicable to an electronic device having a processing unit module and a carrier, wherein the processing unit module includes a processing unit and a first memory unit, the processing unit has a first chip selection terminal and a second chip selection terminal, the first memory unit is used for storing a first BIOS and has a first slave selection terminal, the control circuit comprises:

a first cross-connect device for providing a first set voltage level;

a second jumper for providing a second set voltage level;

a NOT gate, the input terminal of the NOT gate receiving the first setting voltage level;

an OR gate, the first input terminal of the OR gate receiving the second set voltage level, the second input terminal of the OR gate being coupled to the output terminal of the NOT gate;

a first analog switch, wherein the control terminal of the first analog control switch is coupled to the output terminal of the OR gate, and the input terminal of the first analog control switch is coupled to the first chip selection terminal; and

a second analog switch, wherein the control terminal of the second analog control switch is coupled to the output terminal of the OR gate, and the input terminal of the second analog control switch is coupled to the second chip selection terminal;

wherein the second output terminal of the first analog control switch and the first output terminal of the second analog control switch are coupled to the first slave selection terminal of the first memory cell,

wherein when the control terminals of the first analog switch and the second analog switch are at high voltage level, the first chip selection terminal is electrically connected to the first slave selection terminal through the first analog switch,

when the control terminals of the first analog switch and the second analog switch are at low voltage levels, the second chip selection terminal is electrically connected to the first slave selection terminal through the second analog switch.

2. The control circuit of claim 1 wherein the carrier further comprises a second memory unit for storing a second BIOS and having a second slave select terminal,

wherein the first output terminal of the first analog control switch and the second output terminal of the second analog control switch are coupled to the second slave selection terminal of the second memory unit,

wherein when the control terminals of the first analog switch and the second analog switch are at high voltage level, the second chip selection terminal is electrically connected to the second slave selection terminal through the second analog switch,

wherein, when the control terminals of the first analog switch and the second analog switch are at a low voltage level, the first chip selection terminal is electrically connected to the second slave selection terminal through the first analog switch.

3. The control circuit of claim 2 wherein said processing unit is further communicatively coupled to said first memory unit and said second memory unit via an SPI bus.

4. The control circuit of claim 3, wherein after the electronic device is powered on, when the first set voltage level is a high voltage level and the second set voltage level is a high voltage level, the processing unit outputs the high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

5. The control circuit of claim 3, wherein after the electronic device is powered on, when the first set voltage level is a low voltage level and the second set voltage level is a high voltage level, the processing unit outputs a high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

6. The control circuit of claim 3, wherein after the electronic device is powered on, when the first set voltage level is a high voltage level and the second set voltage level is a low voltage level, the processing unit outputs the high voltage level through the first chip select terminal to access the second BIOS of the second memory unit through the SPI bus and execute the second BIOS to perform a power-on procedure.

7. The control circuit of claim 3, wherein after the electronic device is powered on, when the first set voltage level is a low voltage level and the second set voltage level is a low voltage level, the processing unit outputs a high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

8. The control circuit of claim 1, wherein the first jumper and the second jumper are disposed on the carrier board, and the NOT gate, the OR gate, the first analog switch and the second analog switch are disposed on the processing unit module.

9. The BIOS boot control circuit of claim 1, wherein the first chip select terminal is pin # CS0 of the processing unit and the second chip select terminal is pin # CS1 of the processing unit.

Technical Field

The invention relates to a control circuit capable of selecting a boot BIOS, in particular to a control circuit capable of selecting a boot BIOS in an electronic device conforming to COM Express definition.

Background

In the field of Industrial Computer technology, the COM Express specification is defined by the PCI Industrial Computer Manufacturers Group (PICMG) to provide a standardized interface for different application modules to connect and maintain compatibility between each module, so that the design, application and integration of the Industrial Computer modules are more flexible. Currently, in order to make products of industrial computers more convenient to improve performance and meet different requirements of customers in use, more and more products of industrial computers adopt a modular design according to COM Express specification, generally, a common industrial computer includes a processing unit module (CPU module) and a Carrier Board (Carrier Board), and a user can replace different processing unit modules to improve the performance of the industrial computer or increase applications, thereby prolonging the service life of the product.

In addition, the COM Express specification also specifies the setting mode of executing the basic input/output system after the processing unit module is started, and a user can select the started basic input/output system through the setting of the jumper. Conventionally, an embedded controller or a CPLD is disposed on a processing unit module for switching to a correct access path, but the controller is disposed at a relatively high cost and a relatively high space of a circuit board, and the design is complicated, and is prone to error, so that problems are not easily found.

Disclosure of Invention

The present invention provides a control circuit for an electronic device conforming to COM Express definition and capable of selecting boot BIOS.

To solve the above technical problem, the present invention provides a control circuit capable of selecting a boot BIOS, which is suitable for an electronic device having a processing unit module (CPU module) and a Carrier Board (Carrier Board), wherein the processing unit module includes a processing unit and a first memory unit, the processing unit has a first chip select terminal and a second chip select terminal, the first memory unit is used for storing a first BIOS and has a first slave select terminal, the control circuit includes: a first cross-connect device for providing a first set voltage level; a second jumper for providing a second set voltage level; a NOT gate (Inverter), the input terminal of the NOT gate receiving the first set voltage level; an OR gate (OR gate) having a first input terminal receiving the second set voltage level and a second input terminal coupled to the output terminal of the NOT gate; a first analog switch, wherein the control terminal of the first analog control switch is coupled to the output terminal of the OR gate, and the input terminal of the first analog control switch is coupled to the first chip selection terminal; and a second analog switch, wherein the control terminal of the second analog control switch is coupled to the output terminal of the OR gate, and the input terminal of the second analog control switch is coupled to the second chip selection terminal; wherein the second output terminal of the first analog control switch and the first output terminal of the second analog control switch are coupled to the first slave selection terminal of the first memory unit, wherein when the control terminals of the first analog switch and the second analog switch are at a high voltage level, the first chip selection terminal is electrically connected to the first slave selection terminal through the first analog switch, and when the control terminals of the first analog switch and the second analog switch are at a low voltage level, the second chip selection terminal is electrically connected to the first slave selection terminal through the second analog switch.

Preferably, the carrier further includes a second memory unit, and the second memory unit is used for storing a second BIOS and has a second slave select terminal. In addition, the first output terminal of the first analog control switch and the second output terminal of the second analog control switch are coupled to the second slave selection terminal of the second memory unit. When the control terminals of the first analog switch and the second analog switch are at high voltage level, the second chip selection terminal is electrically connected to the second slave selection terminal through the second analog switch. When the control terminals of the first analog switch and the second analog switch are at a low voltage level, the first chip selection terminal is electrically connected to the second slave selection terminal through the first analog switch.

Preferably, the processing unit is further communicatively connected to the first memory unit and the second memory unit via an SPI bus.

Preferably, after the electronic device is powered on, when the first set voltage level is a high voltage level and the second set voltage level is a high voltage level, the processing unit outputs the high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

Preferably, after the electronic device is powered on, when the first setting voltage level is a low voltage level and the second setting voltage level is a high voltage level, the processing unit outputs a high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

Preferably, after the electronic device is powered on, when the first set voltage level is a high voltage level and the second set voltage level is a low voltage level, the processing unit outputs the high voltage level through the first chip select terminal to access the second BIOS of the second memory unit through the SPI bus and execute the second BIOS to perform a power-on procedure.

Preferably, after the electronic device is powered on, when the first setting voltage level is a low voltage level and the second setting voltage level is a low voltage level, the processing unit outputs a high voltage level through the first chip select terminal to access the first BIOS of the first memory unit through the SPI bus and execute the first BIOS to perform a power-on procedure.

Preferably, the first jumper and the second jumper are disposed on the carrier board, and the not gate, the or gate, the first analog switch, and the second analog switch are disposed on the processing unit module.

Preferably, the first chip selection terminal is a # CS0 pin of the processing unit, and the second chip selection terminal is a # CS1 pin of the processing unit.

Compared with the prior art, the invention can ensure that the startup operation of the processing unit module and the carrier plate can meet the COM Express specification definition without arranging an additional controller through the arrangement of the NOT gate, the OR gate and the analog switches SW0 and SW1, and a user can select a path of the processing unit for accessing the basic input and output system through the jumpers J0 and J1, thereby simplifying the design of a circuit and reducing the production and manufacturing cost.

[ description of the drawings ]

Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:

fig. 1 is a diagram illustrating an electronic device 100 according to an embodiment of the invention.

[ detailed description ] embodiments

The embodiments or examples shown in the figures are expressed in a particular manner as set forth below. It is to be understood that the embodiment or examples are not to be construed as limiting. Any alterations and modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.

Fig. 1 is a diagram illustrating an electronic device 100 according to an embodiment of the invention. The electronic device 100 may be a modular computer conforming to the COM Express specification, and the electronic device 100 includes a processor unit module (processor mezzanine module)102 and a Carrier Board (Carrier Board) 104. In some embodiments of the present invention, the processing unit module 102 includes a processing unit 112, a memory unit ROM0, analog switches SW0, SW1, OR gate OR, and NOT gate NOT (Inverter). The carrier board 104 includes a memory cell ROM1 and jumpers (jumpers) J0, J1. Further, the memory unit ROM0 stores a BIOS0, and the memory unit ROM1 stores a BIOS 1. In some embodiments of the present invention, the memory units ROM0 and ROM1 are memories with Serial Peripheral Interface (SPI) and are communicatively connected to the processing unit 112 via SPI bus Db. It should be understood that only some of the components are shown for simplicity, and in some embodiments of the invention, other electronic components, such as network cards, platform management controllers, PCI cards, random access memories, etc., may be included in the processing unit module 102 and the carrier board 104, depending on the design of the user.

As shown in FIG. 1, the chip select terminal CS0 of the processing unit 112 is coupled to the analog switch SW0, and the chip select terminal CS1 of the processing unit 112 is coupled to the analog switch SW 1. In some embodiments, the chip select terminal CS0 is the # CS0 pin of the processing unit 112, and the chip select terminal CS1 is the # CS1 pin of the processing unit 112. The analog switch SW0 is used to selectively electrically connect the chip select terminal CS0 to the slave select terminal SS0 of the memory unit ROM0 or the slave select terminal SS1 of the memory unit ROM1, and similarly, the analog switch SW1 is used to selectively electrically connect the chip select terminal CS1 to the slave select terminal SS0 of the memory unit ROM0 or the slave select terminal SS1 of the memory unit ROM 1.

The input terminal of the NOT gate NOT is coupled to the jumper J0 of the carrier 104 for receiving the set voltage level DIS0, the first input terminal of the OR gate OR is coupled to the jumper J1 of the carrier 104 for receiving the set voltage level DIS1, and the second input terminal of the OR gate OR is coupled to the output terminal of the NOT gate NOT. The output terminal of the OR gate is coupled to the control terminals of the analog switches SW0 and SW1 for switching the connection between the chip select terminals CS0 and CS1 and the slave select terminals SS0 and SS 1.

In order to meet the COM Express specification, when the set voltage level DIS0 of the jumper J0 is the high voltage level "H" and the set voltage level DIS1 of the jumper J1 is the high voltage level "H", the set voltage levels DIS0 and DIS1 of the high voltage level are input to the NOT gate NOT OR the OR gate OR, and the output terminal of the OR gate OR outputs the high voltage level to the control terminals of the analog switches SW0 and SW1, so that the analog switch SW0 electrically connects the chip selection terminal CS0 of the processing unit 112 to the slave selection terminal SS0 of the memory unit ROM0, and the analog switch SW1 electrically connects the chip selection terminal CS1 of the processing unit 112 to the slave selection terminal SS1 of the memory unit ROM 1.

In some embodiments of the present invention, after the electronic device 100 is powered on, the chip select terminal CS1 of the processing unit 112 outputs a low voltage level, and the chip select terminal CS0 of the processing unit 112 outputs a high voltage level, so as to sequentially select and access the bios in the corresponding memory unit for execution. In detail, in a state that the set voltage level DIS0 of the jumper J0 is the high voltage level "H" and the set voltage level DIS1 of the jumper J1 is the high voltage level "H", the chip select terminal CS0 outputs the high voltage level to the slave select terminal SS0 via the analog switch SW 0. When the slave select terminal SS0 receives the high voltage level to enable the memory cell ROM0, the processing unit 112 can then access the BIOS0 of the memory cell ROM0 through the SPI bus Db and execute the BIOS0 for a boot process. In other words, the BIOS0 of the ROM0 is set to be the BIOS that is turned on primarily. In some embodiments, when the processing unit 112 executes the BIOS0, the chip select terminal CS0 of the processing unit 112 outputs a low voltage level and the chip select terminal CS1 of the processing unit 112 outputs a high voltage level to the slave select terminal SS1 via the analog switch SW 1. When the slave select terminal SS1 receives the high voltage level to enable the memory cell ROM1, the processing unit 112 can then access the BIOS1 of the memory cell ROM1 through the SPI bus Db and execute the BIOS1 to perform the boot process. It should be understood that the condition for the processing unit 112 to access the memory unit ROM1 can be determined according to user design, and the invention is not limited to this embodiment.

On the other hand, when the set voltage level DIS0 of the jumper J0 is the low voltage level "L" and the set voltage level DIS1 of the jumper J1 is the high voltage level "H", the set voltage level DIS0 of the low voltage level and the set voltage level DIS1 of the high voltage level are respectively input to the NOT gate NOT and the OR gate OR, and then the output terminal of the OR gate OR outputs the high voltage level to the control terminals of the analog switches SW0 and SW1, so that the analog switch SW0 electrically connects the chip selection terminal CS0 of the processing unit 112 to the slave selection terminal SS0 of the memory unit ROM0, and the analog switch SW1 electrically connects the chip selection terminal CS1 of the processing unit 112 to the slave selection terminal SS1 of the memory unit ROM 1.

In some embodiments of the present invention, after the electronic device 100 is powered on, the chip select terminal CS1 of the processing unit 112 outputs a low voltage level, and the chip select terminal CS0 of the processing unit 112 outputs a high voltage level, so as to sequentially select and access the bios in the corresponding memory unit for execution. Specifically, in a situation where the set voltage level DIS0 of the jumper J0 is the low voltage level "L" and the set voltage level DIS1 of the jumper J1 is the high voltage level "H", the chip select terminal CS0 outputs the high voltage level to the slave select terminal SS0 via the analog switch SW 0. When the slave select terminal SS0 receives the high voltage level to enable the memory cell ROM0, the processing unit 112 can then access the BIOS0 of the memory cell ROM0 through the SPI bus Db and execute the BIOS0 for a boot process. In other words, the BIOS0 of the ROM0 is set to be the BIOS that is turned on primarily. In some embodiments, when the processing unit 112 executes the BIOS0, the chip select terminal CS0 of the processing unit 112 outputs a low voltage level and the chip select terminal CS1 of the processing unit 112 outputs a high voltage level to the slave select terminal SS1 via the analog switch SW 1. When the slave select terminal SS1 receives the high voltage level to enable the memory cell ROM1, the processing unit 112 can then access the BIOS1 of the memory cell ROM1 through the SPI bus Db and execute the BIOS1 to perform the boot process. It should be understood that the condition for the processing unit 112 to access the memory unit ROM1 can be determined according to user design, and the invention is not limited to this embodiment.

When the set voltage level DIS0 of the jumper J0 is the high voltage level "H" and the set voltage level DIS1 of the jumper J1 is the low voltage level "L", the set voltage level DIS0 of the high voltage level and the set voltage level DIS1 of the low voltage level are respectively input to the NOT gate NOT and the OR gate OR, and the output terminal of the OR gate OR outputs the low voltage level to the control terminals of the analog switches SW0 and SW1, so that the analog switch SW0 electrically connects the chip selection terminal CS0 of the processing unit 112 to the slave selection terminal SS1 of the memory unit ROM1, and the analog switch SW1 electrically connects the chip selection terminal CS1 of the processing unit 112 to the slave selection terminal SS0 of the memory unit ROM 0.

In some embodiments of the present invention, after the electronic device 100 is powered on, the chip select terminal CS1 of the processing unit 112 outputs a low voltage level, and the chip select terminal CS0 of the processing unit 112 outputs a high voltage level, so as to sequentially select and access the bios in the corresponding memory unit for execution. In detail, in a state where the set voltage level DIS0 of the jumper J0 is the high voltage level "H" and the set voltage level DIS1 of the jumper J1 is the low voltage level "L", the chip select terminal CS0 outputs the high voltage level to the slave select terminal SS1 via the analog switch SW 0. When the slave select terminal SS1 receives the high voltage level to enable the memory cell ROM1, the processing unit 112 can then access the BIOS1 of the memory cell ROM1 through the SPI bus Db and execute the BIOS1 for a boot process. In other words, the BIOS1 of the ROM1 is set to be the BIOS that is turned on primarily. In some embodiments, when the processing unit 112 executes the BIOS1, the chip select terminal CS0 of the processing unit 112 outputs a low voltage level and the chip select terminal CS1 of the processing unit 112 outputs a high voltage level to the slave select terminal SS0 via the analog switch SW 1. When the slave select terminal SS0 receives the high voltage level to enable the memory cell ROM0, the processing unit 112 can then access the BIOS0 of the memory cell ROM0 through the SPI bus Db and execute the BIOS0 to perform the boot process. It should be understood that the condition for the processing unit 112 to access the memory unit ROM0 can be determined according to user design, and the invention is not limited to this embodiment.

On the other hand, when the set voltage level DIS0 of the jumper J0 is the low voltage level "L" and the set voltage level DIS1 of the jumper J1 is the low voltage level "L", the set voltage levels DIS0 and DIS1 of the low voltage level are respectively inputted to the NOT gate NOT and the OR gate OR, and the output terminal of the OR gate OR outputs the high voltage level to the control terminals of the analog switches SW0 and SW1, so that the analog switch SW0 electrically connects the chip selection terminal CS0 of the processing unit 112 to the slave selection terminal SS0 of the memory unit ROM0, and the analog switch SW1 electrically connects the chip selection terminal CS1 of the processing unit 112 to the slave selection terminal SS1 of the memory unit ROM 1.

In some embodiments of the present invention, after the electronic device 100 is powered on, the chip select terminal CS1 of the processing unit 112 outputs a low voltage level, and the chip select terminal CS0 of the processing unit 112 outputs a high voltage level, so as to sequentially select and access the bios in the corresponding memory unit for execution. In detail, in a state where the set voltage level DIS0 of the jumper J0 is the low voltage level "L" and the set voltage level DIS1 of the jumper J1 is the high voltage level "L", the chip select terminal CS0 outputs the high voltage level to the slave select terminal SS0 via the analog switch SW 0. When the slave select terminal SS0 receives the high voltage level to enable the memory cell ROM0, the processing unit 112 can then access the BIOS0 of the memory cell ROM0 through the SPI bus Db and execute the BIOS0 for a boot process. In other words, the BIOS0 of the ROM0 is set to be the BIOS that is turned on primarily. In some embodiments, when the processing unit 112 executes the BIOS0, the chip select terminal CS0 of the processing unit 112 outputs a low voltage level and the chip select terminal CS1 of the processing unit 112 outputs a high voltage level to the slave select terminal SS1 via the analog switch SW 1. When the slave select terminal SS1 receives the high voltage level to enable the memory cell ROM1, the processing unit 112 can then access the BIOS1 of the memory cell ROM1 through the SPI bus Db and execute the BIOS1 to perform the boot process. It should be understood that the condition for the processing unit 112 to access the memory unit ROM1 can be determined according to user design, and the invention is not limited to this embodiment.

In summary, the present invention does NOT need to provide an additional controller through the configuration of the NOT gate NOT, the OR gate OR and the analog switches SW0 and SW1, so that the power-on operation of the processing unit module 102 and the carrier 104 can meet the COM Express specification definition, and the user can select the path of the processing unit 112 accessing the bios through the jumpers J0 and J1, thereby simplifying the circuit design and reducing the manufacturing cost. It should be understood that, depending on the specification and the user design, the memory unit ROM0 and the memory unit ROM1 can be disposed on the processing unit module 102 or the carrier board 104, or the memory unit ROM0 and the memory unit ROM1 can be integrated into one memory unit.

The methods of the present invention, or certain aspects or portions thereof, may take the form of program code. The program code may be embodied in tangible media, such as floppy diskettes, cd-roms, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine thereby becomes an apparatus for practicing the invention. The program code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique apparatus that operates analogously to specific logic circuits.

While the present invention has been described with reference to preferred embodiments, it is to be understood that the above disclosure is not intended to limit the embodiments of the invention. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Furthermore, the appended claims are to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.