阅读说明：本技术 一种基于可布线性预测的全局布线优化方法 (Global wiring optimization method based on routability prediction ) 是由 张旋 宿淼迪 丁鸿志 翁绍鸿 邹长忠 陈建利 于 2021-08-15 设计创作，主要内容包括：本发明涉及一种基于可布线性预测的全局布线优化方法,首先在详细布局之后根据布局结果定义关键特征,然后利用提取的特征数据和详细布线后衡量可布线性的实际数据训练得到可布线性预测模型,最后将模型嵌入布局布线算法中,指导布线过程,达到优化布线拥塞的效果。本发明可以有效地减少全局布线结果中的溢出和线长。(The invention relates to a global wiring optimization method based on routability prediction, which comprises the steps of firstly defining key characteristics according to a layout result after detailed layout, then training by utilizing extracted characteristic data and actual data for measuring routability after detailed wiring to obtain a routability prediction model, and finally embedding the model into a layout-wiring algorithm to guide a wiring process so as to achieve the effect of optimizing wiring congestion. The invention can effectively reduce overflow and wire length in the global wiring result.)

1. A global routing optimization method based on routability prediction is characterized in that: the method comprises the following steps:

step S1: regarding each layer of the chip layout design as a plane, dividing the plane into grids with the same size and representing the grids as a grid graph, representing each grid as a matrix element, counting pins, net capacity and NCPR information contained in each grid from netlist information of a layout result, and estimating net density to obtain higher-level features; analyzing and comparing the statistical Pearson correlation coefficients of the features, and selecting the features with low correlation, namely removing the similar repeated features with high correlation; counting the use amount of the central line and the through holes of each grid from the netlist information of the global wiring result so as to obtain a label; storing the finally reserved features and labels as a multi-dimensional matrix for the following neural network model training;

step S2: selecting a U-Net network model as a congestion estimator, taking the extracted features as input and taking the labels as output, training the model to an optimal state so as to enable the network to effectively apply input information and fit a real wiring congestion condition;

step S3: embedding the trained model into a wiring flow, extracting relevant information of detailed layout results, namely the characteristic input model mentioned in the step S2 before global wiring, and obtaining a fitted wiring congestion condition through model calculation; on the basis, a routing constraint strategy based on the congestion situation is used for guiding in the global routing process so as to optimize the final routing result from the global perspective and reduce the routing overflow and the line length under the condition that the time consumption is approximately the same.

2. The global routing optimization method based on routability prediction according to claim 1, wherein: the specific content of step S1 is:

dividing each layer of the chip layout design into a group of grids called tiles as a plane, wherein each tile represents a vertex and is connected with adjacent vertices to construct a grid line; the grid line between two vertices is called a line edge, i.e. the line edge is a channel between two tiles; the direction of the channels on the same layer is uniform, i.e. horizontal or vertical; each vertex, namely each grid tile, is provided with the number of adjacent pins, the pin density, the wire mesh capacity, the wire mesh density and NCPR information, the correlation is calculated by adopting a Pearson correlation coefficient, and the information with the highest correlation is removed, so that the information with low correlation is extracted as the characteristic of the tile; the using amount of the central line and the through hole of each tile after wiring is the label of the tile;

a new calculation mode of the wire mesh density, namely three-dimensional RUDY, is adopted to extract higher-level features; the specific calculation method of the two-dimensional RUDY is shown as a formula (1), and the three-dimensional RUDY assumes that a wire net is arranged in a corresponding b-box, expands the RUDY into a three-dimensional space so as to construct three-dimensional characteristics, and obtains a converted formula (4);

RUDY for net n is denoted R (n), where HPWL denotes the length of the half-cycle and the width of the wire is denoted p (n), where w_nAnd h_nThe width and height of the two-dimensional b-box of the wire mesh n, respectively;

suppose a net must traverse the layer in which its pins reside, i.e., the pin layer and all layers between pins; therefore, the lowest pin layer is set as the lowest layer of the b-box, the highest pin layer is set as the highest layer, and the range of the b-box depends on the relative positions of the pins; the relative position of the pins determines the path direction of a wire mesh; if the pin is positioned on a horizontal or vertical line, the wiring direction is horizontal or vertical; if the two pins are positioned on the diagonal, the wiring direction simultaneously comprises a horizontal direction and a vertical direction; that is, the direction of the conductive lines on different layers alternates between the horizontal direction and the vertical direction; when the b-box lacks the layer where the pins are located, the b-box is expanded up and down so as to enable the b-box to comprise layers in different directions passing through when the two pins are wired; after the RUDY estimation, the product of the wire and the wire width should be evenly assigned to each tile in the three-dimensional b-box; with a width w according to b-box_nAnd height h_nThe method for determining the proportion of each layer is given by the formula (2) and the formula (3) to accurately estimate the wiring density:

wherein r is_h(n) and r_v(n) is each waterRatio of wire meshes n in the flat and vertical layers, y_h(n) and y_v(n) respectively representing the number of horizontal and vertical layers in the b-box of the wire mesh n; the above formula represents the width and height of the wire mesh and the b-box bottom half perimeter w_n+h_nThe ratio of (a) directly determines the distribution of the wire mesh in the horizontal layer and the vertical layer; further, the calculation formula for obtaining the three-dimensional RUDY is as follows:

wherein i represents h or v; the meaning of formula (4) is as follows: because the number of the metal layers is small, the proportion of the wire mesh in each layer needs to be according to w_nAnd h_nIt is estimated that the product of the half-cycle length and the wire width is allocated to each layer of the b-box in this ratio;

in addition, the wire mesh density is obtained by calculation according to the formula (4), and the calculation mode of the wire mesh density, namely the three-dimensional RUDY combined pin density, the wire mesh capacity, the number of adjacent pins and the NCPR finally obtains 5 characteristics; then, analyzing by using a Pearson correlation coefficient, evaluating the correlation of the characteristics, only keeping one of the characteristics with the correlation coefficient larger than 0.4, and removing redundant information; the three characteristics of the pin density, the wire mesh capacity and the wire mesh density are finally reserved and calculated by the three-dimensional RUDY; correspondingly, the usage amount of the lines and the through holes directly obtained from the netlist information after wiring is used as a label; the method is characterized in that each layer of the chip layout design is regarded as a plane, the plane is divided and expressed into a grid graph according to grids with the same size, each grid tile is expressed as a matrix element, the value of each element is the value of a feature or a label extracted from the grid, so that the feature or the label information of each layer of the chip layout design can be converted into matrix representation according to the process, and the chip has multiple layers, so that the multidimensional matrix representation of circuit example information can be established.

3. The global routing optimization method based on routability prediction according to claim 1, wherein: the specific content of step S2 is:

regarding the multidimensional matrix of the layout result information obtained in the step S1 as a group of pixel matrices, i.e., images, where the feature information matrix is represented as a feature map and the label information matrix is represented as a congestion map; for these images cut at a fixed size of 64 x 64 and a step size of 10 and then stacked to segment the features of one circuit instance into a set of images, the dimensions of the inputs and outputs of the neural network can be determined from the dimensions of the features and label images obtained in step S1; the characteristics include pin density, wire mesh capacity, and wire mesh density; the label comprises the usage amount of the thread and the usage amount of the through hole;

adopt seven layers of neural network structures, including cubic downsampling, cubic upsampling and an output layer, whole model calculation process divide into two parts: down-sampling and up-sampling; the down-sampling operation is carried out three times in total, and each time can be decomposed into four processes of convolution, activation, normalization and maximum pooling; each downsampling reduces the input feature map size by a factor of two, which is considered to be an encoder; similarly, three times of upsampling operation form a decoder, and the semantic feature map calculated by the encoder is restored to the resolution of the congestion map through three times of upsampling; each up-sampling module consists of bilinear interpolation, convolution operation, an activation layer and a normalization layer; finally, connecting and stacking the output feature matrix of each module and the data at the same stage of down-sampling by adopting a jump connection method to obtain a fusion feature map; after the model is designed, the segmented original characteristic diagram obtained in the step S1 is used as a training set batch input model of the model, the output is obtained through forward propagation calculation of the neural network, the output is compared with a real label diagram, a loss function is calculated, and parameters of the neural network model, namely convolution and normalization weight parameters, are continuously optimized by using a gradient descent and back propagation algorithm; by adopting an Adam optimizer and multiple rounds of iteration, the parameters of the model are converged to the optimal state, so that the network can effectively apply input information and fit the real wiring congestion condition.

4. The global routing optimization method based on routability prediction according to claim 1, wherein: the specific content of step S3 is:

predicting global wiring congestion by using a congestion estimator, and then adjusting a wiring mode according to the predicted congestion condition so as to avoid a highly congested area of wiring; adding a global congestion prediction constraint in a global wiring stage in the physical design of a chip to adjust an initial wiring solution and obtain a better final solution; in order to introduce a congestion estimator for guiding global routing, designing a constraint based on congestion prediction to modify a congestion cost function of initial routing; the expression is as follows:

g(u，v)＝wl(u，v)×t(u，v)×c_o， (5)

where (u, v) denotes the edge connecting vertices u and v, g (u, v) andoriginal and new congestion cost functions of the line edge (u, v), respectively, wl (u, v) denotes the length of the line edge (u, v), c_oIs the cost of spillage per unit length; pw (u, v) and pv (u, v) represent the usage of the line and via, respectively, predicted by the congestion estimator, pu (u, v) is the predicted usage; e is a parameter that the user can specify; in equation (7), when the edge is predicted to have overflow or nearly overflow, the congestion cost g (u, v) of the edge (u, v) is set to infinity to avoid passing through the edge when routing; if the edge does not reach the overflow level, adjusting according to the use condition of the edge; specifically, a lower bound of 0.5 is set for pu (u, v) to prevent over-tuning of the model; in addition, the above-described basis is used for the first 70% of nets in the wiringThe congestion prediction guiding method utilizes the predicted usage amount of the lines and the vias to modify the congestion cost function of the original router to guide routing, and the last 30% of the nets still use the congestion cost function and the routing method of the original router to enable the first 70% of the nets to avoid the highly congested areas in the prediction result during routing, and the last 30% of the nets to route in the areas, so that the congestion situation is effectively reduced.

Technical Field

The invention relates to the technical field of VLSI physical design automation, in particular to a global wiring optimization method based on routability prediction.

Background

Chip physical design generally has optimization goals of routability, time delay, power consumption, area, manufacturability, etc., and as integrated circuit manufacturing processes evolve and feature sizes decrease, routability is becoming one of the most important goals. The actual routing congestion and routability can be obtained only after the detailed routing is finished, and the routability prediction means that the congestion condition and routability of the routing are estimated in the design stage before the detailed routing, so that the routing congestion can be optimized in the early stage of physical design, and the method has important significance for the design quality and the cycle shortening of the chip.

The current routability prediction is mainly based on the utilization rate of the wiring resources of each region and the quantity of design rule violations, and is essentially a rough measure of factors influencing the consumption of the wiring resources, and has the limitations of dependence on manpower, long time consumption, difficulty in adapting to increasingly complex design rules and the like. To overcome the above limitations, the present invention proposes to use a method of deep learning for predicting routability. Deep learning is to mine the rules and essence hidden behind the object by training data and using an algorithm to obtain a model. The routability prediction model based on deep learning takes the utilization rate of routing resources in the detailed routing result as the measurement of routability, extracts relevant characteristics of the circuit after detailed layout, and uses the data for training the model. The routability model obtained by training is applied in the global routing stage, so that the routing congestion condition can be quickly estimated, the routability is optimized, the running time is shortened, and the quality of routing solutions (such as wire length, the number of through holes, the number of design rule violations and the like) is improved.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a global routing optimization method based on routability prediction, which is based on a machine learning modeling method, combines with a neural network model, selects a suitable model, defines key features after detailed routing, trains to obtain a routability model by using extracted feature data and actual data for measuring routability after detailed routing, embeds the model in a routing algorithm, guides a global routing process, achieves an effect of optimizing routing congestion, and finally forms a routability-driven global routing model and algorithm.

The invention is realized by adopting the following scheme: a global routing optimization method based on routability prediction comprises the following steps:

step S1: regarding each layer of the chip layout design as a plane, dividing the plane into grids with the same size and representing the grids as a grid graph, representing each grid as a matrix element, counting pins, net capacity and NCPR information contained in each grid from netlist information of a layout result, and estimating net density to obtain higher-level features; performing Pearson correlation coefficient analysis and comparison on the features, and selecting the features with low correlation degree, namely removing the similar repeated features with high correlation; counting the use amount of the central line and the through holes of each grid from the netlist information of the global wiring result so as to obtain a label; storing the finally reserved features and labels as a multi-dimensional matrix for the following neural network model training;

step S2: selecting a U-Net network model as a congestion estimator, taking the extracted features as input and taking the labels as output, training the model to an optimal state so as to enable the network to effectively apply input information and fit a real wiring congestion condition;

step S3: embedding the trained model into a wiring flow, extracting relevant information of detailed layout results, namely the characteristic input model mentioned in the step S2 before global wiring, and obtaining a fitted wiring congestion condition through model calculation; on the basis, a routing constraint strategy based on the congestion situation is used for guiding in the global routing process so as to optimize the final routing result from the global perspective and reduce the routing overflow and the line length under the condition that the time consumption is approximately the same.

Further, the specific content of step S1 is:

dividing each layer of the chip layout design into a group of grids called tiles as a plane, wherein each tile represents a vertex and is connected with adjacent vertices to construct a grid line; the grid line between two vertices is called a line edge, i.e. the line edge is a channel between two tiles; the direction of the channels on the same layer is uniform, i.e. horizontal or vertical; each vertex, namely each grid tile, is provided with the information of the number of adjacent pins, the pin density, the wire mesh capacity, the wire mesh density and NCPR (net-cut-per-region), the correlation is calculated by adopting a Pearson correlation coefficient, and the information with the highest correlation is removed, so that the information with low correlation is extracted as the characteristic of the tile; the using amount of the central line and the through hole of each tile after wiring is the label of the tile;

a new wire mesh density calculation mode, namely three-dimensional RUDY (rectangular uniformity wire Density), is adopted to extract higher-level features; a formula (1) is a specific calculation method of the traditional two-dimensional RUDY, and the three-dimensional RUDY assumes that a wire net is arranged in a corresponding b-box (bounding box), expands the RUDY into a three-dimensional space so as to construct a three-dimensional feature, and obtains a converted formula (4);

RUDY for net n is denoted R (n), where HPWL denotes the length of the half-cycle and the width of the wire is denoted p (n), where w_nAnd h_nThe width and height of the two-dimensional b-box of the wire mesh n, respectively;

suppose a net must traverse the layer in which its pins reside, i.e., the pin layer and all layers between pins; therefore, the lowest pin layer is set as the lowest layer of the b-box, the highest pin layer is set as the highest layer, and the range of the b-box depends on the relative positions of the pins; the relative position of the pins determines the path direction of a wire mesh; if the pin is positioned on a horizontal or vertical line, the wiring direction is horizontal or vertical; if the two pins are positioned on the diagonal, the wiring direction simultaneously comprises a horizontal direction and a vertical direction; i.e. the direction of the conductors on different layers alternates between horizontal and verticalMelting; when the b-box lacks the layer where the pins are located, the b-box is expanded up and down so as to enable the b-box to comprise layers in different directions passing through when the two pins are wired; after the RUDY estimation, the product of the wire and the wire width should be evenly assigned to each tile in the three-dimensional b-box; with a width w according to b-box_nAnd height h_nThe method for determining the proportion of each layer is given by the formula (2) and the formula (3) to accurately estimate the wiring density:

wherein r is_h(n) and r_v(n) is the ratio of the wire network n in each horizontal and vertical layer, y_h(n) and y_v(n) respectively representing the number of horizontal and vertical layers in the b-box of the wire mesh n; the above formula represents the width and height of the wire mesh and the b-box bottom half perimeter w_n+h_nThe ratio of (a) directly determines the distribution of the wire mesh in the horizontal layer and the vertical layer; further, the calculation formula for obtaining the three-dimensional RUDY is as follows:

wherein i represents h or v; the meaning of formula (4) is as follows: because the number of the metal layers is small, the proportion of the wire mesh in each layer needs to be according to w_nAnd h_nIt is estimated that the product of the half-cycle length and the wire width is allocated to each layer of the b-box in this ratio;

in addition, the wire mesh density is obtained by calculation according to the formula (4), and the calculation mode of the wire mesh density, namely the three-dimensional RUDY combined pin density, the wire mesh capacity, the number of adjacent pins and the NCPR finally obtains 5 characteristics; then, analyzing by using a Pearson correlation coefficient, evaluating the correlation of the characteristics, only keeping one of the characteristics with the correlation coefficient larger than 0.4, and removing redundant information; the three characteristics of the pin density, the wire mesh capacity and the wire mesh density are finally reserved and calculated by the three-dimensional RUDY; correspondingly, the usage amount of the lines and the through holes directly obtained from the netlist information after wiring is used as a label; the method is characterized in that each layer of the chip layout design is regarded as a plane, the plane is divided and expressed into a grid graph according to grids with the same size, each grid tile is expressed as a matrix element, the value of each element is the value of a feature or a label extracted from the grid, so that the feature or the label information of each layer of the chip layout design can be converted into matrix representation according to the process, and the chip has multiple layers, so that the multidimensional matrix representation of circuit example information can be established.

Further, the specific content of step S2 is:

regarding the multidimensional matrix of the layout result information obtained in the step S1 as a group of pixel matrices, i.e., images, where the feature information matrix is represented as a feature map and the label information matrix is represented as a congestion map; for these images cut at a fixed size of 64 x 64 and a step size of 10 and then stacked to segment the features of one circuit instance into a set of images, the dimensions of the inputs and outputs of the neural network can be determined from the dimensions of the features and label images obtained in step S1; the characteristics include pin density, wire mesh capacity, and wire mesh density; the label comprises the usage amount of the thread and the usage amount of the through hole;

adopt seven layers of neural network structures, including cubic downsampling, cubic upsampling and an output layer, whole model calculation process divide into two parts: down-sampling and up-sampling; the down-sampling operation is carried out three times in total, and each time can be decomposed into four processes of convolution, activation, normalization and maximum pooling; each downsampling reduces the input feature map size by a factor of two, which is considered to be an encoder; similarly, three times of upsampling operation form a decoder, and the semantic feature map calculated by the encoder is restored to the resolution of the congestion map through three times of upsampling; each up-sampling module consists of bilinear interpolation, convolution operation, an activation layer and a normalization layer; finally, connecting and stacking the output feature matrix of each module and the data at the same stage of down-sampling by adopting a jump connection method to obtain a fusion feature map; after the model is designed, the segmented original characteristic diagram obtained in the step S1 is used as a training set batch input model of the model, the output is obtained through forward propagation calculation of the neural network, the output is compared with a real label diagram, a loss function is calculated, and parameters of the neural network model, namely convolution and normalization weight parameters, are continuously optimized by using a gradient descent and back propagation algorithm; by adopting an Adam optimizer and multiple rounds of iteration, the parameters of the model are converged to the optimal state, so that the network can effectively apply input information and fit the real wiring congestion condition.

Further, the specific content of step S3 is:

predicting global wiring congestion by using a congestion estimator, and then adjusting a wiring mode according to the predicted congestion condition so as to avoid a highly congested area of wiring; adding a global congestion prediction constraint in a global wiring stage in the physical design of a chip to adjust an initial wiring solution and obtain a better final solution; in order to introduce a congestion estimator for guiding global routing, designing a constraint based on congestion prediction to modify a congestion cost function of initial routing; the expression is as follows:

g(u，v)＝wl(u，v)×t(u，v)×c_o， (5)

where (u, v) denotes the edge connecting vertices u and v, g (u, v) andoriginal and new congestion cost functions of the line edge (u, v), respectively, wl (u, v) denotes the length of the line edge (u, v), c_oIs overflow per unit lengthCost is produced; pw (u, v) and pv (u, v) represent the usage of the line and via, respectively, predicted by the congestion estimator, pu (u, v) is the predicted usage; e is a parameter that the user can specify; in equation (7), when the edge is predicted to have overflow or nearly overflow, the congestion cost g (u, v) of the edge (u, v) is set to infinity to avoid passing through the edge when routing; if the edge does not reach the overflow level, adjusting according to the use condition of the edge; specifically, a lower bound of 0.5 is set for pu (u, v) to prevent over-tuning of the model; in addition, the method based on the congestion prediction guidance is adopted for the first 70% of nets in the routing, the method modifies the congestion cost function of the original router by using the predicted usage amount of the lines and the vias to guide the routing, and the congestion cost function and the routing method of the original router are still used for the last 30% of nets so that the first 70% of nets avoid the highly congested areas in the prediction result during the routing, and the last 30% of nets route in the areas, thereby effectively reducing the congestion condition.

Compared with the prior art, the invention has the following beneficial effects:

(1) the invention has high speed. At present, most of estimation on wiring congestion is to perform fast overall wiring, and the congestion situation after detailed wiring is estimated by using the result after the overall wiring. According to the invention, under the condition of not carrying out overall wiring, the congestion is estimated directly according to indexes such as pin density and the like after layout based on a deep learning method.

(2) The invention has high prediction accuracy. In practical application, the similarity of the result of congestion prediction in the invention and the actual congestion situation is very high, and the average value reaches 84.8%.

(3) The invention has good wiring effect. In the test of actual mass data, the model prediction result provided by the invention guides the wiring method to reduce the overflow, the wire length and the through hole count of the wiring result by 6.05 percent, 0.02 percent and 1.18 percent respectively.

Drawings

FIG. 1 is a flow chart of a method according to an embodiment of the present invention.

Fig. 2 is a schematic diagram showing a circuit plane as a grid diagram according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of three-dimensional RUDY calculation according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an embodiment of the present invention that employs a correlation analysis to evaluate the correlation coefficient of a feature, thereby removing redundant information.

FIG. 5 is a diagram illustrating the creation of a multi-dimensional matrix of circuit instance information and the conversion into image processing according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a model training set produced by cutting a feature map and a congestion map in steps according to an embodiment of the present invention.

Fig. 7 is a schematic design diagram of a congestion estimator based on a deep learning neural network model according to an embodiment of the present invention.

Detailed Description

The invention is further explained below with reference to the drawings and the embodiments.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The embodiment provides a global routing optimization method based on routability prediction, which comprises the following steps:

step S1: regarding each layer of the chip layout design as a plane, dividing the plane into grids with the same size and representing the grids as a grid graph, wherein each grid is represented as a matrix element, counting pins, net capacity and NCPR information contained in each grid from netlist information of a layout result, and estimating net density based on the information by combining a formula (4) mentioned below so as to obtain higher-level features; analyzing and comparing the statistical Pearson correlation coefficients of the features, and selecting the features with low correlation, namely removing the similar repeated features with high correlation; counting the use amount of the central line and the through holes of each grid from the netlist information of the global wiring result so as to obtain a label; storing the finally reserved features and labels as a multi-dimensional matrix for the following neural network model training;

step S2: selecting an effective deep learning neural network model (in the embodiment, a U-Net network model is adopted) as a congestion estimator, taking the extracted features as input and taking a label as output, and training the model to an optimal state so as to enable the network to effectively apply input information and fit a real wiring congestion condition;

step S3: the traditional layout and wiring process is divided into global layout, legalization, detailed layout, global wiring and detailed wiring, in the embodiment, a trained model is embedded into the traditional wiring process, relevant information of a detailed layout result, namely the characteristic input model mentioned in the step S2, is extracted before global wiring is carried out, and a fitted wiring congestion condition can be obtained through model calculation; on the basis, guidance is carried out in the global routing process by using a routing constraint strategy based on the congestion situation, which is detailed below, so as to optimize the final routing result from the global perspective and reduce the overflow of the routing and the line length under the condition that the time consumption is approximately the same.

In this embodiment, the specific content of step S1 is:

as shown in the attached figure 2 of the specification, each layer of the chip layout design is divided into a group of grids called tiles as a plane, and each tile represents a vertex and is connected with an adjacent vertex to form a grid line; the grid line between two vertices is called a line edge, i.e. the line edge is a channel between two tiles; the direction of the channels on the same layer is uniform, i.e. horizontal or vertical; each vertex, namely each grid tile, is provided with the number of adjacent pins, the pin density, the wire mesh capacity, the wire mesh density and NCPR information, the correlation is calculated by adopting a Pearson correlation coefficient, and the information with the highest correlation is removed, so that the information with the most representative (low correlation degree) is extracted as the characteristic of the tile; the usage amount of the wire and the through hole of each tile after routing (which can be directly obtained from the netlist information after routing) is the label of the tile;

for feature extraction, a plurality of features related to evaluation are first analyzed. In particular, the present invention designs a new way to calculate net density for the three-dimensional router appearing in recent years, namely, three-dimensional RUDY (triangular uniformity wire Density). The RUDY itself is an estimation method of the wire network distribution in the two-dimensional wiring. The RUDY for net n can be represented as R (n), as shown in equation (1), where HPWL represents the half-cycle length and the width of the wire is represented as p (n), where w_nAnd h_nThe width and height, respectively, of the two-dimensional b-box (bounding box) of wire mesh n.

The specific calculation method of the traditional two-dimensional RUDY is shown as a formula (1), while the three-dimensional RUDY assumes that a wire net is arranged in a corresponding b-box, and the RUDY is expanded into a three-dimensional space so as to construct a three-dimensional feature, so that a converted formula (4) is obtained;

the embodiment expands the RUDY to a three-dimensional space, and solves the problem of wire mesh density calculation in the three-dimensional router. In order to extract higher-level features, on the basis of obtaining the information of the number of adjacent pins, the pin density, the wire network capacity and the wire network density, a new wire network density calculation mode, namely a three-dimensional RUDY is adopted, and the specific calculation method of the three-dimensional RUDY is as follows: the RUDY assumes that the wire mesh is in the corresponding b-box, and the RUDY is expanded to a three-dimensional space so as to construct three-dimensional characteristics, and finally a formula (4) is obtained;

first, assume that the net must pass through the layer where its pins are located, i.e., the pin layer and all layers between the pins; so the lowest pin level is set as the lowest level of the b-box, the highest pin level is set as the highest level, and the range of the b-box depends on the leadThe relative position of the feet; the relative position of the pins determines the path direction of a wire mesh; if the pin is positioned on a horizontal or vertical line, the wiring direction is horizontal or vertical; if the two pins are positioned on the diagonal, the wiring direction simultaneously comprises a horizontal direction and a vertical direction; that is, the direction of the conductive lines on different layers alternates between the horizontal direction and the vertical direction; therefore, in order to make the b-box include layers passing through different directions when the wiring is performed with the wire net, when the b-box lacks the layer where the pins are located, the b-box is expanded up and down so as to make the b-box include layers passing through different directions when the two pins are wired; after the RUDY estimation, the product of the wire and the wire width should be evenly assigned to each tile in the three-dimensional b-box; since there may be millions of nets in a chip design, the two-dimensional b-box of a net is small compared to the size of the chip, and the wiring requirements and circuitry requirements of the net are also small. Thus, a single net need not accurately predict routing requirements within its two-dimensional b-box. In contrast, a chip can only have up to tens of metal layers, so the error is mainly due to whether a net is evenly distributed to each layer of its b-box. Therefore, in order to accurately estimate the wiring density, the present invention proposes a width w according to the b-box_nAnd height h_nThe method for determining the proportion of each layer is given by formula (2) and formula (3):

with a width w according to b-box_nAnd height h_nThe method for determining the proportion of each layer is given by the formula (2) and the formula (3) to accurately estimate the wiring density:

wherein r is_h(n) and r_v(n) is the ratio of the wire network n in each horizontal and vertical layer, y_h(n) and y_v(n) respectively representing the number of horizontal and vertical layers in the b-box of the wire mesh n;the above formula represents the width and height of the wire mesh and the b-box bottom half perimeter (w)_n+h_n) The ratio of (a) directly determines the distribution of the wire mesh in the horizontal layer and the vertical layer; further, the calculation formula for obtaining the three-dimensional RUDY is as follows:

wherein i represents h or v; the meaning of formula (4) is as follows: because the number of metal layers is relatively small, the proportion of the wire mesh in each layer needs to be according to w_nAnd h_nIt is estimated that the product of the half-cycle length and the wire width is allocated to each layer of the b-box in this ratio; in contrast, the size of the two-dimensional b-box is much smaller than the chip, so the values on each layer can be evenly distributed to each tile on that layer.

In addition, 5 features in fig. 4 of pin density, net capacity, net density (calculated by three-dimensional RUDY), number of adjacent pins, and NCPR (net-cuts-per-region) are finally obtained by combining other features (pin density, net capacity, number of adjacent pins, NCPR) which can be directly extracted; then, evaluating the correlation coefficient of the characteristics by adopting correlation analysis, only keeping one characteristic in the characteristics with the correlation coefficient more than 0.4, and removing redundant information; the three characteristics of the pin density, the wire mesh capacity and the wire mesh density are finally reserved and calculated by the three-dimensional RUDY; the three characteristics are correspondingly used as labels according to the usage amount of the lines and the through holes directly obtained from the netlist information after wiring; in step S1, each layer of the chip layout design is regarded as a plane, the plane is divided into grids of the same size and represented as a grid graph, each grid (tile) is represented as a matrix element, and the value of each element is the value of the feature or label extracted from the grid, so that the feature or label information of each layer of the chip layout design can be transformed into such a matrix representation (as shown in fig. 2) according to the above process, and since the chip has multiple layers, a multi-dimensional matrix representation of circuit instance information can be established as shown in fig. 5.

In this embodiment, the specific content of step S2 is:

regarding the multidimensional matrix of the layout result information obtained in the step S1 as a group of pixel matrices, i.e., images, where the feature information matrix is represented as a feature map and the label information matrix is represented as a congestion map; these images are cut at a fixed size (64 x 64) and step size (size 10) and then stacked to segment the features of one circuit instance into a set of images that can be accepted by a deep learning neural network. Determining the input and output dimensions of the neural network according to the dimensions of the feature (pin density, wire mesh capacity, wire mesh density) and label (wire usage and via usage) images obtained in step S1;

next, an effective neural network model is designed, and since the routability prediction task is converted into an image translation task through the steps, namely the conversion of the feature image into the congestion image, the congestion estimator based on the neural network model is designed based on the U-Net network, and the model achieves a very good effect in the image translation task. The estimator adopts the operations of down-sampling, up-sampling and jump connection;

in addition, the embodiment improves the method by using bilinear interpolation upsampling to replace the common deconvolution upsampling operation, and avoids the possible chessboard artifact (image noise). This embodiment proposes a seven-layer neural network architecture including three downsampling, three upsampling, and an output layer to predict routability from the extracted features. The whole model calculation process is divided into two parts: downsampling and upsampling. The downsampling operation is carried out three times in total, and each operation can be decomposed into four processes of convolution operation, activation layer, normalization and maximum pooling. The model employs a total of three downsamplings, reducing the size of the input feature map by a factor of 8. This process can be viewed as an encoder. Similarly, a cubic upsampling operation (upsampling by bilinear interpolation) forms a decoder, and the semantic feature map obtained by the encoder (cubic downsampling) is subjected to cubic upsampling to restore the resolution of the congestion map. Each upsampling module consists of a bilinear interpolation, a convolution operation, an activation layer, and a normalization layer. In addition, the model stacks each module output feature matrix and the data connection of the same stage of downsampling, namely, a jump connection operation is adopted. The operation can enable the finally recovered feature map to be fused with more semantic features and the features of different scales to be fused, so that multi-scale prediction and deep supervised learning can be performed.

After the model is designed, the segmented original characteristic diagram obtained in the step S1 is used as a training set batch input model of the model, the output is obtained through forward propagation calculation of the neural network, the output is compared with a real label diagram, a loss function is calculated, and parameters (convolution and normalization weight parameters) of the neural network model are continuously optimized by using a gradient descent and back propagation algorithm; by adopting an Adam optimizer and multiple rounds of iteration, the parameters of the model are converged to the optimal state, so that the network can effectively apply input information and fit the real wiring congestion condition.

In this embodiment, the specific content of step S3 is:

predicting global wiring congestion by using the neural network model, namely a congestion estimator, and then adjusting a wiring mode according to the predicted congestion condition so as to avoid a highly congested area of wiring; therefore, a constraint of global congestion prediction is added in the global wiring stage in the physical design of the chip to adjust the initial wiring solution and obtain a better final solution; in order to introduce a congestion estimator for guiding global routing, designing a constraint based on congestion prediction to modify a congestion cost function of initial routing; the expression is as follows:

g(u，v)＝wl(u，v)×t(u，v)×c_o， (5)

wherein g (u, v) andwl (u, v) represents the length of the line edge (u, v), c, the original and new congestion cost functions, respectively_oIs the overflow cost per unit length (a given constant), pw (u, v) and pv (u, v) represent the predicted usage of lines and vias by the congestion estimator, respectively, and pu (u, v) is the predicted usage; e is a parameter (set to 0.15) that the user can specify; in equation (7), when the edge is predicted to have overflow or nearly overflow, the congestion cost g (u, v) of the edge (u, v) is set to infinity to avoid passing through the edge when routing; if the edge does not reach the overflow level, adjusting according to the use condition of the edge; specifically, a lower bound of 0.5 is set for pu (u, v) to prevent over-tuning of the model; in addition, the method based on the congestion prediction guidance is adopted for the first 70% of nets in the routing, the method modifies the congestion cost function of the original router by using the predicted usage amount of the lines and the vias to guide the routing, and the last 30% of nets still use the congestion cost function and the routing method of the original router, so that the first 70% of nets avoid the highly congested areas obtained in the prediction result during the routing, and the last 30% of nets route in the areas, thereby effectively reducing the congestion situation.

Preferably, in this embodiment, FIG. 1 is a flowchart of a method for optimizing global routing based on routability prediction according to the present invention;

firstly, defining key features according to a layout result after detailed layout, then training by using extracted feature data and actual data for measuring routability after detailed wiring to obtain a routability prediction model, and finally embedding the model into a layout and wiring algorithm to guide a wiring process so as to achieve the effect of optimizing wiring congestion. The technical scheme is as follows: (1) before global wiring, a brand-new three-dimensional router-based net density calculation mode is defined according to a layout result, pin density, net capacity and net density information in a net after detailed layout are extracted and used as input characteristics of routability prediction, and meanwhile, the use amount of lines and through holes obtained after detailed wiring is used as label information output by the routability prediction; (2) a reasonable neural network structure is designed and adopted (the improved U-Net model is used in the invention), and a real data training model is obtained by utilizing the 2 nd point, so that the network can effectively apply input information and fit the real wiring congestion condition. (3) And embedding the trained model into a wiring frame, extracting a characteristic input model before global wiring, and predicting the wiring congestion condition, namely the routability information obtained by using the model. And guiding the wiring by using a certain strategy according to the congestion prediction condition so as to optimize the final wiring result. The embodiment can effectively reduce overflow and line length in the global routing result.

The method comprises the following steps:

(1) each layer plane of the circuit is represented as a grid graph, each grid is represented as a matrix element, and appropriate features and labels are extracted or designed from the netlist information of the layout result. And analyzing and comparing the characteristics, selecting proper and effective characteristics, and removing the characteristics with higher correlation. Because the circuit is multi-layered in three-dimensional space, the present invention extracts three-dimensional features. Storing the finally reserved features and labels as a multi-dimensional matrix for the following neural network model training;

(2) an effective deep learning neural network model (the invention uses the improved U-Net network model) is selected as a congestion estimator, and the model is trained to the best state using the extracted features as input and the labels as output. The network can effectively apply the input information and fit the real wiring congestion condition;

(3) and (3) embedding the trained model into a wiring flow, extracting relevant information of a layout result, namely the characteristic input model mentioned in the step (2), before global wiring, and obtaining a fitted wiring congestion condition through model calculation. On the basis, a certain strategy is used for guidance in the global wiring process according to the congestion prediction situation, so that the final wiring result can be optimized from the global perspective. The effect of reducing the overflow of the wiring and the length of the wire under the condition of approximately same time consumption is achieved;

fig. 2 shows a circuit plane divided into a set of meshes called tiles according to a first embodiment of the present invention, wherein each tile represents a vertex and connects adjacent vertices to form a grid line. The grid lines between two vertices are called line edges, i.e. a line edge is a channel between two tiles. The direction of the channels on the same layer is uniform, i.e. horizontal or vertical. Each vertex, i.e. each mesh tile, has certain information, and the most representative information needs to be extracted as the feature of the tile. And the amount of wire and via usage for each tile after routing is the tile's label.

FIG. 3 is a schematic diagram of a three-dimensional RUDY calculation proposed by the present invention. The invention designs a new calculation mode of net density, namely three-dimensional RUDY (rectangular uniformity wire Density), aiming at the three-dimensional router appearing in recent years. The RUDY itself is an estimation method of the wire network distribution in the two-dimensional wiring. The four boundaries of the dark rectangle form a two-dimensional b-box of the pins of one net. The invention expands the RUDY into a three-dimensional space, and solves the problem of wire mesh density calculation in the three-dimensional wiring device. An example is illustrated where both pins of the net are on the second level (the bottom most level is level 0). Since the two pins are diagonally opposite, the routing direction of the net should include both horizontal and vertical directions. I.e. a three-dimensional b-box should contain both horizontal and vertical layers. However, only the second level of the pin layer of the net is horizontal, so the b-box needs to extend above and below the second level. The dark cube marked in the figure is the three-dimensional b-box of the last net. The main purpose of the above steps is to have the layers in the b-box contain layers in the same direction as the net routing direction so that the three dimensional b-box can model the basic routing extent of the net.

Fig. 4 is a schematic diagram of removing redundant information by evaluating the correlation coefficient of a feature through correlation analysis according to an embodiment of the present invention, as shown in the figure, the characteristics of pin density, net capacity, net density (calculated by three-dimensional RUDY), adjacent pin count, NCPR (net-cut-per-region), and the like. And then, evaluating the correlation coefficient of the characteristics by adopting correlation analysis, and only keeping one of the characteristics with higher correlation to remove redundant information. And finally, three characteristics of pin density, net capacity and net density are reserved.

FIG. 5 is a diagram illustrating the creation of a multi-dimensional matrix of circuit instance information and its conversion to image processing, according to an embodiment of the present invention. After the layout result information is converted into a multi-dimensional matrix, the multi-dimensional matrix is regarded as a group of pixel matrixes, namely images, so that the characteristic information matrix can be expressed as a characteristic diagram, and the label information matrix can be expressed as a congestion diagram.

Fig. 6 is a schematic diagram of a training set of a cut-to-make model according to step size for a pair of feature maps and a congestion map according to an embodiment of the present invention. The images are cut at fixed size and step size and then stacked, so that the features of one circuit instance are segmented into a set of images that can be accepted by a deep learning neural network.

Fig. 7 is a schematic design diagram of a deep learning neural network model-based congestion estimator in the present invention. The invention designs a congestion estimator based on a neural network model based on a U-Net network, and the model has good effect in an image translation task at present. The estimator employs downsampling, upsampling and hopping connection operations. In addition, the invention improves the method and uses bilinear interpolation upsampling to replace the common deconvolution upsampling operation, thereby avoiding the chessboard artifact which can occur. The present invention proposes a seven-layer neural network architecture to predict routability from extracted features. The whole model calculation process is divided into two parts: downsampling and upsampling. The downsampling progress has three modules, and each module can be decomposed into four processes of convolution operation, activation layer, normalization and maximum pooling. The model employs a total of three downsamplings, reducing the size of the input feature map by a factor of 8. This process can be viewed as an encoder. Similarly, the three modules of upsampling form a decoder that restores the high level semantic feature map obtained by the encoder to the resolution of the congestion map. Each upsampling module consists of a bilinear interpolation, a convolution operation, an activation layer, and a normalization layer. In addition, the model stacks each module output feature matrix and the data connection of the same stage of downsampling, namely, a jump connection operation is adopted. The operation can enable the finally recovered feature map to be fused with more semantic features and the features of different scales to be fused, so that multi-scale prediction and deep supervised learning can be performed. After the model is designed, the segmented characteristic diagram is used as a training set of the model and input into the model in batches, output is obtained through calculation, the output is compared with a real label diagram, a loss function is calculated, and parameters of the model are continuously optimized by using a gradient descent and back propagation algorithm. And adopting an Adam optimizer, and converging the parameters of the model to the optimal state through multiple rounds of iteration. Therefore, the network can effectively apply the input information and fit the real wiring congestion condition. And finally, predicting global wiring congestion by using a congestion estimator, and adjusting a wiring mode according to the predicted congestion condition so as to avoid a highly congested area of wiring.

Embodiments illustrate routers that are the latest three-dimensional routers, and the present invention is equally applicable to routability prediction and route optimization in conventional two-dimensional routers.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.