阅读说明：本技术 一种用户态下dma数据缓存一致性方法、装置及系统 (DMA data cache consistency method, device and system in user mode ) 是由 高强 于 2021-08-13 设计创作，主要内容包括：本发明公开了一种用户态下DMA数据缓存一致性方法、装置、系统及计算机可读存储介质,该方法包括：在用户态下根据DMA发送的数据存储完成通知确定出目标内存；判断各个缓存中是否存在与目标内存对应的目标缓存,若存在,则获取目标缓存中的数据信息,并对数据信息进行校验；若不存在,则直接获取目标内存中存储的数据信息,并结束操作；当验证成功时,目标缓存中的数据信息与目标内存中存储的数据信息一致,结束操作；当校验失败时,延迟预设时长后返回执行判断各个缓存中是否存在与目标内存对应的目标缓存的步骤,直至不存在与目标内存对应的目标缓存或校验成功；能够提高缓存与内存中数据的一致性,有利于提升系统性能及提高用户使用体验。(The invention discloses a method, a device and a system for DMA data cache consistency in a user mode and a computer readable storage medium, wherein the method comprises the following steps: determining a target memory according to a data storage completion notification sent by the DMA in a user mode; judging whether a target cache corresponding to the target memory exists in each cache, if so, acquiring data information in the target cache, and verifying the data information; if the data information does not exist, directly acquiring the data information stored in the target memory, and finishing the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished; when the verification fails, delaying for a preset time, returning to execute the step of judging whether a target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful; the consistency of the data in the cache and the memory can be improved, and the system performance and the user experience can be improved.)

1. A DMA data cache consistency method in a user mode is characterized by comprising the following steps:

determining a target memory according to a data storage completion notification sent by the DMA in a user mode;

judging whether a target cache corresponding to the target memory exists in each cache, if so, acquiring data information in the target cache, and verifying the data information; if the data information does not exist, directly acquiring the data information stored in the target memory, and finishing the operation;

when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished;

and when the verification fails, delaying for a preset time, and returning to the step of judging whether the target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful.

2. The method of claim 1, further comprising, after a check fails:

and when no link layer error report or physical layer error report exists at present, executing the step of delaying for the preset time length and then returning to execute the step of judging whether a target cache corresponding to the target memory exists in each cache.

3. The method according to claim 1 or 2, wherein before the step of returning and determining whether a target cache corresponding to the target memory exists in each cache after the delaying for the preset duration, the method further comprises:

and judging whether the current continuous verification failure times reach preset times, if so, failing in data transmission, and controlling the system to restart, otherwise, executing the step of delaying the preset time length and then returning to the step of judging whether the target cache corresponding to the target memory exists in each cache.

4. The method according to claim 1, wherein before determining the target memory according to the data storage completion notification sent by the DMA in the user mode, the method further comprises:

receiving original data information sent by a sending end through a DMA (direct memory access) in a user state; the sending end obtains effective data with a target preset length from the initial end of the effective data of the original data information to calculate a standard CRC value, and adds the CRC value to the tail of the effective data to form the original data information; wherein, the target preset lengths respectively corresponding to the original data information sent by two adjacent times are different

Sending the original data information to a memory for storage through the DMA, and generating a data storage completion notification;

then, the data information includes valid data and a standard CRC check value; the process of verifying the data information comprises the following steps:

obtaining effective data with the target preset length from the effective data starting end of the data information, and calculating a current CRC value according to the effective data with the target preset length;

and comparing the current CRC check value with a standard CRC check value in the data information, if the current CRC check value is consistent with the standard CRC check value, the check is successful, and if the current CRC check value is inconsistent with the standard CRC check value, the check is failed.

5. The method according to claim 4, wherein the process of the sending end obtaining valid data with a target preset length from the original data information to calculate a standard CRC value is as follows:

the sending end selects a preset length different from the preset length of the historical target from a first preset length and a second preset length as a preset target length corresponding to the currently sent original data information according to the preset historical target length corresponding to the original data information sent last time; selecting a preset length different from the last time from the first preset length and the second preset length alternately as a target preset length when data information is sent each time;

and acquiring the effective data with the target preset length from the effective data start end of the original data information, and calculating a standard CRC value according to the effective data with the target preset length.

6. A DMA data cache coherency apparatus in a user mode, comprising:

the determining module is used for determining a target memory according to the data storage completion notice sent by the DMA in the user mode;

the judging module is used for judging whether a target cache corresponding to the target memory exists in each cache or not, and if yes, the verifying module is triggered; if not, triggering an acquisition module;

the verification module is used for acquiring the data information in the target cache and verifying the data information;

the acquisition module is used for directly acquiring the data information stored in the target memory and finishing the operation;

the ending module is used for finishing the operation when the verification is successful and the data information in the target cache is consistent with the data information stored in the target memory;

and the return module is used for triggering the judgment module after delaying the preset time when the verification fails.

7. The device according to claim 6, wherein the return module is specifically configured to delay the triggering of the determining module for a preset time period when there is no error report in a link layer or no error report in a physical layer at present.

8. The apparatus for DMA data cache coherency in a user mode according to claim 6, further comprising:

the receiving module is used for receiving original data information sent by the sending end through the DMA in a user mode; the sending end obtains effective data with a target preset length from the initial end of the effective data of the original data information to calculate a standard CRC value, and adds the CRC value to the tail of the effective data to form the original data information; the target preset lengths respectively corresponding to the original data information sent in two adjacent times are different;

the sending module is used for sending the original data information to an internal memory for storage through the DMA and generating a data storage completion notice;

then, the data information includes valid data and a standard CRC check value; the authentication module includes:

the acquisition unit is used for acquiring the effective data with the target preset length from the effective data starting end of the data information and calculating the current CRC value according to the effective data with the target preset length;

and the comparison unit is used for comparing the current CRC value with a standard CRC value in the data information, if the current CRC value is consistent with the standard CRC value, the ending module is triggered, and if the current CRC value is inconsistent with the standard CRC value, the returning module is triggered.

9. A DMA data cache coherency system in user mode, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the DMA data cache coherency method in the user mode according to any one of claims 1 to 5 when executing the computer program.

10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, performs the steps of the DMA data cache coherency method in the user mode according to any one of claims 1 to 5.

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a system, and a computer-readable storage medium for DMA data cache consistency in a user mode.

Background

DMA (Direct Memory Access) can take over the bus to complete data transmission, thereby freeing up a CPU (Central Processing Unit/Processor) and enabling the CPU to complete other work. However, if the DMA cache is provided with a cache (cache memory) and the CPU is provided with a prefetch function, after the receiving end receives the data, the data in the cache may be inconsistent with the data in the memory, thereby causing data errors. Experiments prove that the problem has higher probability when the CPU Cache is larger and the Cache automatic failure time is longer.

When the CPU changes data in a certain cache line, the data in the cache line is newer than the data in the corresponding memory, and at this time, the cache line needs to be marked as modified (updated) so that the content flush in the cache line is synchronized to the memory when necessary (for example, when the cache is full, the cache line needs to be released, and bits are vacated to the new cache line). cache operations for maintaining consistency can be divided into flush and invalid, when the DMA is used, data transmitted from an external device (such as a network card) can be directly transmitted to a memory without passing through a CPU, at this time, data in the memory is newer than data in the corresponding cache, and a cache line (marked as dirty) related to invalid (invalid) needs to be made, so that when the CPU reads data in the cache line next time, the data can be known to be not up to date, and can be updated from the memory. In fact, after a certain cache line is invalid, the cache line has no utilization value, namely, the cache line does not exist, namely, the cache line is emptied, so that the cache line can be counted as flush.

However, there is no separate invalid instruction in the user mode, because the invalid instruction belongs to a privileged instruction, and the user mode only has invalid and Flush operations, but this causes that, when data in the invalid-related cache is needed, a Flush operation must be attached, that is, the data in the cache is flushed to a corresponding storage, so as to pollute new data transferred from the DMA to the memory. Therefore, after data transmitted from an external device (such as a network card) is directly transmitted to the memory, the data in the memory is newer than the data in the corresponding cache, and since the cache cannot be marked in an invalid state in a user state, the data read by the CPU from the cache corresponding to the memory is not the new data stored in the memory, which causes data verification failure.

In view of the above, how to provide a method, an apparatus, a system and a computer-readable storage medium for DMA data cache consistency in a user mode is a problem to be solved by those skilled in the art.

Disclosure of Invention

Embodiments of the present invention provide a method, an apparatus, a system, and a computer-readable storage medium for DMA data cache consistency in a user mode, which can improve consistency between a cache and data in a memory during use, and are beneficial to improving system performance and improving user experience.

To solve the foregoing technical problem, an embodiment of the present invention provides a method for DMA data cache consistency in a user mode, including:

determining a target memory according to a data storage completion notification sent by the DMA in a user mode;

judging whether a target cache corresponding to the target memory exists in each cache, if so, acquiring data information in the target cache, and verifying the data information; if the data information does not exist, directly acquiring the data information stored in the target memory, and finishing the operation;

when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished;

and when the verification fails, delaying for a preset time, and returning to the step of judging whether the target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful.

Optionally, after the verification fails, the method further includes:

and when no link layer error report or physical layer error report exists at present, executing the step of delaying for the preset time length and then returning to execute the step of judging whether a target cache corresponding to the target memory exists in each cache.

Optionally, before the step of returning to execute the step of determining whether the target cache corresponding to the target memory exists in each cache after the delaying for the preset time period, the method further includes:

and judging whether the current continuous verification failure times reach preset times, if so, failing in data transmission, and controlling the system to restart, otherwise, executing the step of delaying the preset time length and then returning to the step of judging whether the target cache corresponding to the target memory exists in each cache.

Optionally, before determining the target memory according to the data storage completion notification sent by the DMA in the user mode, the method further includes:

receiving original data information sent by a sending end through a DMA (direct memory access) in a user state; the sending end obtains effective data with a target preset length from the initial end of the effective data of the original data information to calculate a standard CRC value, and adds the CRC value to the tail of the effective data to form the original data information; the target preset lengths respectively corresponding to the original data information sent in two adjacent times are different;

sending the original data information to a memory for storage through the DMA, and generating a data storage completion notification;

then, the data information includes valid data and a standard CRC check value; the process of verifying the data information comprises the following steps:

obtaining effective data with the target preset length from the effective data starting end of the data information, and calculating a current CRC value according to the effective data with the target preset length;

and comparing the current CRC check value with a standard CRC check value in the data information, if the current CRC check value is consistent with the standard CRC check value, the check is successful, and if the current CRC check value is inconsistent with the standard CRC check value, the check is failed.

Optionally, the process of obtaining, by the sending end, valid data with a preset target length from the original data information and calculating a standard CRC check value includes:

the sending end selects a preset length different from the preset length of the historical target from a first preset length and a second preset length as a preset target length corresponding to the currently sent original data information according to the preset historical target length corresponding to the original data information sent last time; selecting a preset length different from the last time from the first preset length and the second preset length alternately as a target preset length when data information is sent each time;

and acquiring the effective data with the target preset length from the effective data start end of the original data information, and calculating a standard CRC value according to the effective data with the target preset length.

The embodiment of the invention also provides a device for DMA data cache consistency in a user mode, which comprises the following components:

the determining module is used for determining a target memory according to the data storage completion notice sent by the DMA in the user mode;

the judging module is used for judging whether a target cache corresponding to the target memory exists in each cache or not, and if yes, the verifying module is triggered; if not, triggering an acquisition module;

the verification module is used for acquiring the data information in the target cache and verifying the data information;

the acquisition module is used for directly acquiring the data information stored in the target memory and finishing the operation;

the ending module is used for finishing the operation when the verification is successful and the data information in the target cache is consistent with the data information stored in the target memory;

and the return module is used for triggering the judgment module after delaying the preset time when the verification fails.

Optionally, the returning module is specifically configured to delay a preset time and then trigger the determining module when there is no error report of the link layer or no error report of the physical layer.

Optionally, the method further includes:

the receiving module is used for receiving original data information sent by the sending end through the DMA in a user mode; the sending end obtains effective data with a target preset length from the initial end of the effective data of the original data information to calculate a standard CRC value, and adds the CRC value to the tail of the effective data to form the original data information; the target preset lengths respectively corresponding to the original data information sent in two adjacent times are different;

the sending module is used for sending the original data information to an internal memory for storage through the DMA and generating a data storage completion notice;

then, the data information includes valid data and a standard CRC check value; the authentication module includes:

the acquisition unit is used for acquiring the effective data with the target preset length from the effective data starting end of the data information and calculating the current CRC value according to the effective data with the target preset length;

and the comparison unit is used for comparing the current CRC value with a standard CRC value in the data information, if the current CRC value is consistent with the standard CRC value, the ending module is triggered, and if the current CRC value is inconsistent with the standard CRC value, the returning module is triggered.

The embodiment of the invention also provides a system for DMA data cache consistency in a user mode, which comprises the following steps:

a memory for storing a computer program;

and the processor is used for realizing the steps of the DMA data cache consistency method in the user mode when executing the computer program.

The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the DMA data cache consistency method in the user mode are implemented as described above.

The embodiment of the invention provides a method, a device and a system for DMA data cache consistency in a user mode and a computer readable storage medium, wherein the method comprises the following steps: determining a target memory according to a data storage completion notification sent by the DMA in a user mode; judging whether a target cache corresponding to the target memory exists in each cache, if so, acquiring data information in the target cache, and verifying the data information; if the data information does not exist, directly acquiring the data information stored in the target memory, and finishing the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished; and when the verification fails, delaying for a preset time, returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful.

It can be seen that, in the embodiment of the present invention, a target memory is determined according to a data storage completion notification sent by a DMA in a user mode, then it is determined whether a cache corresponding to the target memory exists in each cache, if the corresponding target cache does not exist, it indicates that the CPU has not yet printed the data information stored in the target memory into the cache, the stored data information is directly obtained from the target memory, if the corresponding target cache exists, the data information in the target cache is obtained from the corresponding target cache, and the data information is verified, if the verification is successful, it indicates that the data information cached in the target cache is consistent with the data information stored in the target memory, the data obtaining is successful and the operation is finished, if the verification is unsuccessful, a preset duration is delayed, and then it is continuously determined whether a target cache consistent with the target memory exists in each cache, if the target cache corresponding to the target memory does not exist or the verification is successful, ending the operation; the delay of the preset time is beneficial to the CPU to brush the data information in the target memory into the cache by using the time so as to keep the consistency of the cache and the data in the memory; the invention can improve the consistency of the data in the cache and the memory, and is beneficial to improving the system performance and improving the user experience.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic flowchart of a DMA data cache consistency method in a user mode according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a DMA data cache coherency device in a user mode according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention provide a method, an apparatus, a system, and a computer-readable storage medium for DMA data cache consistency in a user mode, which can improve consistency between a cache and data in a memory during use, and are beneficial to improving system performance and improving user experience.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a DMA data cache consistency method in a user mode according to an embodiment of the present invention. The method comprises the following steps:

s110: determining a target memory according to a data storage completion notification sent by the DMA in a user mode;

it should be noted that, when the embodiment of the present invention is applied in a user mode, when implementing DMA data transfer between devices through a network card, the DMA directly stores the transferred data into the memory, and generates a data storage completion notification after the DMA sends data information to the memory to complete storage, and after receiving the data storage completion notification sent by the DMA, determines a target memory according to the data storage completion notification, and specifically may determine a corresponding target memory according to a memory identification code carried in the data storage completion notification.

S120: judging whether a target cache corresponding to the target memory exists in each cache, and if so, entering S130; if not, entering S160;

s130: acquiring data information in a target cache, and verifying the data information;

specifically, when a target cache corresponding to the target memory exists in the cache, the data information is acquired from the target cache, and the data information is verified, so as to determine whether the verification of the data information is successful.

S140: when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished;

specifically, when the verification is successful, it is indicated that the data information stored in the target cache is consistent with the data information stored in the target memory, and the data information obtained at this time is correct data information, and the operation is ended.

S150: when the verification fails, delaying for a preset time, returning to execute the step of judging whether a target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful;

specifically, if the data information acquired from the target cache fails to be checked, it indicates that the data information is inconsistent with the data information stored in the target memory, at this time, the step of determining whether a target cache corresponding to the target memory exists in each cache may be executed after delaying for a preset time, and the data information of the target cache is read again when the target cache corresponding to the target memory exists, and the data information is checked until the target cache consistent with the target memory does not exist in each cache or the data check fails. Specifically, when there is no error report of the link layer or physical layer, the step of delaying for a preset time period and then returning to execute the step of determining whether a target cache corresponding to the target memory exists in each cache may be executed. That is, if there is no error report at the link layer or physical layer and the verification fails, it indicates that the data information obtained from the target cache is not the newly stored data information in the target memory, and the problem of cache data inconsistency occurs.

It should be noted that, because the mechanism of the CPU itself is to continuously refresh the data information in the memory into the cache corresponding to the memory, when new data is stored in the memory and the CPU has not refreshed the new data from the memory into the corresponding cache, the data information obtained from the cache is old data information, since the data information in the memory is not consistent with the data information in the cache, the verification fails if passing through the verification, but since the CPU continuously refreshes the data in the memory into the corresponding cache, the present invention sets a delayed reading mechanism, that is, after the verification fails, the step of delaying for a preset time length to trigger again to determine whether a target cache corresponding to the target memory exists in each cache, and reading the data information in the target cache if exists, if the target cache corresponding to the target memory is stored all the time, after the cpu refreshes the data information in the target memory into the target cache, the data information read from the target cache in a certain round is successfully verified, that is, correct data information is obtained. In addition, according to the mechanism of the CPU itself, since the overall size of the cache is much smaller than the overall size of the memory, after data is stored in a certain memory, the CPU finds out the cache corresponding to the memory from the cache and then refreshes the data into the cache, but when the cache corresponding to the memory does not exist in the cache, the CPU can directly obtain corresponding data information from the memory, and also finds out an idle cache from each cache or when there is no idle cache, it is necessary to establish a mapping relationship between the cache that is used first and the memory from the first cache, and refresh the data in the memory into the cache to cover the old data originally stored in the cache.

S160: and directly acquiring the data information stored in the target memory, and finishing the operation.

It should be noted that, in the embodiment of the present invention, when it is determined that a target cache corresponding to a target memory does not exist in each cache, the stored data information may be directly acquired from the target memory.

Further, when the IOPS requirement for the data is high, before the step of returning to the step of determining whether the target cache corresponding to the target memory exists in each cache after the preset time delay is performed, the method may further include:

and judging whether the current continuous verification failure times reach preset times, if so, failing in data transmission, and carrying out restarting operation by the control system, otherwise, delaying for a preset time and returning to the step of judging whether a target cache corresponding to the target memory exists in each cache. Further, before determining the target memory according to the data storage completion notification sent by the DMA in the user mode, the method may further include:

receiving original data information sent by a sending end through a DMA (direct memory access) in a user state; the method comprises the steps that a sending end obtains effective data with a target preset length from the starting end of the effective data of original data information to calculate a standard CRC value, and the CRC value is added to the tail of the effective data to form original data information, wherein the target preset lengths corresponding to the original data information sent twice in adjacent times are different;

sending the original data information to an internal memory for storage through DMA, and generating a data storage completion notice;

it should be noted that, in the user mode, the sending end sends the sent original data information to the memory for storage through the DMA, where the original data information includes valid data and a standard CRC check value, where the sending end obtains valid data of a target preset length from a start end of the valid data to calculate the standard CRC check value, and then adds the standard CRC check value to an end of the valid data to form the original data information. The target preset length corresponding to the original data information sent last time by the sending end is different from the target preset length corresponding to the original data information sent currently, and the target preset length corresponding to the original data information sent currently is also different from the target preset length corresponding to the original data information sent next time.

Correspondingly, the data information comprises valid data and a standard CRC value; the process of verifying the data information may specifically be:

acquiring effective data with a target preset length from an effective data starting end of the data information, and calculating a current CRC value according to the effective data with the target preset length;

and comparing the current CRC check value with the standard CRC check value in the data information, if the current CRC check value is consistent with the standard CRC check value, the check is successful, and if the current CRC check value is inconsistent with the standard CRC check value, the check is failed.

Specifically, data information is acquired from a target cache, valid data with the target preset length is acquired from the start end of the valid data in the data information, a current CRC check value is calculated according to the valid data with the target preset length, then the current CRC check value is compared with a standard CRC check value in the acquired data information, if the current CRC check value is consistent with the standard CRC check value, it is indicated that the data information in the target cache is consistent with the data information stored in a target memory, and if the current CRC check value is inconsistent with the standard CRC check value, it is indicated that the data information in the target cache is inconsistent with the data information stored in the target memory.

It should be noted that, when the sending end sends the original data information, the target preset lengths corresponding to the original data information sent twice in the adjacent time are different, so after the currently sent original data information is sent to the target memory for storage through the DMA, if the CPU has not yet reached to refresh the data information stored in the target memory this time into the target cache, the data information still stored in the target cache is the data information sent to the target memory last time, then since the target preset length adopted last time is different from the target preset length adopted this time, for example, the target preset length adopted last time is 30, the target preset length adopted this time is 60, that is, the standard CRC check value in the data information cached in the target cache is calculated by using valid data with the target preset length of 30, after the data information is obtained from the target cache, after the valid data is acquired by adopting the current target preset length, the calculated current CRC value is inconsistent with the standard CRC value in the data information, so that the data information in the target cache is proved to be inconsistent with the data information in the target memory, after the preset time is delayed, if the CPU refreshes the data information in the target memory to the target cache in the period of time, the current CRC value calculated by adopting the valid data of the current target preset length (such as 60) after the data information in the target cache is read again is consistent with the standard CRC value in the data information, so that the data information acquired from the target cache is determined to be consistent with the data information stored in the target memory.

Further, the process of the sending end obtaining the valid data with the target preset length from the original data information to calculate the standard CRC value may specifically be:

the sending end selects a preset length different from the preset length of the historical target from the first preset length and the second preset length as a preset target length corresponding to the currently sent original data information according to the preset historical target length corresponding to the original data information sent last time; selecting a preset length different from the last time from the first preset length and the second preset length alternately as a target preset length when data information is sent each time;

and obtaining effective data with a target preset length from the effective data starting end of the original data information, and calculating a standard CRC value according to the effective data with the target preset length.

It should be noted that, in the embodiment of the present invention, the first preset length and the second preset length may be preset, and the first preset length and the second preset length are alternately used as the target preset length when the sending end sends the data information each time, so that it is ensured that the target preset lengths corresponding to the data information sent twice are different. Correspondingly, after the data information is obtained from the target cache, the first preset length and the second preset length are alternately used as the target preset length, wherein the target preset length adopted in the process is the same as the target preset length of the data information sent by the sending end, and the currently corresponding target preset length (for example, the last time is the first preset length, and the current time is the second preset length) can be automatically determined according to the rule that the first preset length and the second preset length are alternately performed when the data storage completion notification is received every time, and the target preset length is switched to another preset length (for example, the next time is the first preset length) until the data storage completion notification is received next time.

It can be seen that, in the embodiment of the present invention, a target memory is determined according to a data storage completion notification sent by a DMA in a user mode, then it is determined whether a cache corresponding to the target memory exists in each cache, if the corresponding target cache does not exist, it indicates that the CPU has not yet printed the data information stored in the target memory into the cache, the stored data information is directly obtained from the target memory, if the corresponding target cache exists, the data information in the target cache is obtained from the corresponding target cache, and the data information is verified, if the verification is successful, it indicates that the data information cached in the target cache is consistent with the data information stored in the target memory, the data obtaining is successful and the operation is finished, if the verification is unsuccessful, a preset duration is delayed, and then it is continuously determined whether a target cache consistent with the target memory exists in each cache, if the target cache corresponding to the target memory does not exist or the verification is successful, ending the operation; the delay of the preset time is beneficial to the CPU to brush the data information in the target memory into the cache by using the time so as to keep the consistency of the cache and the data in the memory; the invention can improve the consistency of the data in the cache and the memory, and is beneficial to improving the system performance and improving the user experience.

On the basis of the foregoing embodiments, an embodiment of the present invention further provides a device for DMA data cache coherency in a user mode, which is specifically shown in fig. 2. The device includes:

the determining module 21 is configured to determine, in the user mode, a target memory according to the data storage completion notification sent by the DMA;

the judging module 22 is configured to judge whether a target cache corresponding to the target memory exists in each cache, and if yes, trigger the verifying module 23; if not, triggering the obtaining module 24;

the verification module 23 is configured to obtain data information in the target cache, and verify the data information;

the obtaining module 24 is configured to directly obtain data information stored in the target memory, and end the operation;

an ending module 25, configured to, when the verification is successful, end the operation if the data information in the target cache is consistent with the data information stored in the target memory;

and a returning module 26, configured to trigger the determining module 22 after delaying for a preset time period when the verification fails.

Optionally, the returning module 26 is specifically configured to trigger the determining module after delaying a preset time when there is no error report of the link layer or no error report of the physical layer.

Optionally, the apparatus further comprises:

the receiving module is used for receiving original data information sent by the sending end through the DMA in a user mode; the sending end obtains effective data with a target preset length from the initial end of the effective data of the original data information to calculate a standard CRC value, and adds the CRC value to the tail of the effective data to form the original data information; the target preset lengths respectively corresponding to the original data information sent in two adjacent times are different;

the sending module is used for sending the original data information to the memory for storage through the DMA and generating a data storage completion notice;

then, the data information includes valid data and a standard CRC check value; the authentication module 23 includes:

the acquiring unit is used for acquiring effective data with a target preset length from the effective data starting end of the data information and calculating a current CRC value according to the effective data with the target preset length;

and the comparison unit is used for comparing the current CRC value with the standard CRC value in the data information, if the current CRC value is consistent with the standard CRC value, the ending module is triggered, and if the current CRC value is inconsistent with the standard CRC value, the returning module is triggered.

It should be noted that the DMA data cache consistency device in the user mode provided in the embodiment of the present invention has the same beneficial effects as the DMA data cache consistency method in the user mode provided in the foregoing embodiment, and for specific description of the DMA data cache consistency method in the user mode related in the embodiment of the present invention, reference is made to the foregoing embodiment, and details of the present invention are not repeated herein.

On the basis of the above embodiments, an embodiment of the present invention further provides a DMA data cache coherency system in a user mode, where the system includes:

a memory for storing a computer program;

and the processor is used for realizing the steps of the DMA data cache consistency method in the user mode when executing the computer program.

For example, the processor in the embodiment of the present invention may be specifically configured to determine the target memory according to the data storage completion notification sent by the DMA in the user mode; judging whether a target cache corresponding to the target memory exists in each cache, if so, acquiring data information in the target cache, and verifying the data information; if the data information does not exist, directly acquiring the data information stored in the target memory, and finishing the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is finished; and when the verification fails, delaying for a preset time, returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the verification is successful.

On the basis of the foregoing embodiments, an embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the DMA data cache consistency method in the user mode are implemented.

The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.