阅读说明：本技术 半导体结构及其制造方法 (Semiconductor structure and manufacturing method thereof ) 是由 张哲诚 林志翰 曾鸿辉 于 2016-11-22 设计创作，主要内容包括：一种半导体结构,包括：衬底、至少一个第一栅极结构、至少一个第一间隔件、至少一个源漏结构、至少一个导体以及至少一个保护层。第一栅极结构位于衬底上。第一间隔件位于第一栅极结构的至少一个侧壁上。源漏结构邻近于第一间隔件。导体电连接至源漏结构。保护层位于导体和第一间隔件之间并且保护层位于第一栅极结构的顶面上。本发明还提供了制造半导体结构的方法。(A semiconductor structure, comprising: the semiconductor device comprises a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor and at least one protective layer. The first gate structure is located on the substrate. The first spacer is located on at least one sidewall of the first gate structure. The source and drain structures are adjacent to the first spacer. The conductor is electrically connected to the source drain structure. A protective layer is between the conductor and the first spacer and on a top surface of the first gate structure. The invention also provides a method of fabricating a semiconductor structure.)

1. A semiconductor structure, comprising:

a substrate;

at least one first gate structure located on the substrate;

at least one first spacer on at least one sidewall of the first gate structure;

at least one source drain structure adjacent to the first spacer;

at least one conductor electrically connected to the source drain structure;

at least one protective layer between the conductor and the first spacer and on a top surface of the first gate structure; and

a first dielectric layer between the conductor and the first spacer and between the protective layer and the source drain structure, wherein the protective layer is separated from the source drain structure by the first dielectric layer, wherein, in a cross-sectional view, the protective layer has vertical portions extending laterally beyond the first spacer, the vertical portions are both in contact with the conductor and the width of the vertical portions increases linearly from top to bottom,

wherein sidewalls of the conductor extend continuously from a top surface of the protective layer through the protective layer to a bottom surface of the protective layer at corners of respective ones of the at least one first gate structure,

wherein the at least one first gate structure comprises a diffusion barrier layer, wherein a lower portion of the diffusion barrier layer and an upper portion located above the lower portion comprise different materials.

2. The semiconductor structure of claim 1, wherein the protective layer is made of silicon nitride, silicon oxynitride, or a combination thereof.

3. The semiconductor structure of claim 1, further comprising:

at least one second gate structure on the substrate; and

and the source-drain structure is positioned between the first spacer and the second spacer.

4. The semiconductor structure of claim 3, wherein the protective layer is further located between the conductor and the second spacer, and the protective layer is located on a top surface of the second gate structure.

5. The semiconductor structure of claim 1, further comprising:

a second dielectric layer at least on the protective layer, the second dielectric layer having an opening therein, wherein at least a portion of the conductor is located in the opening.

6. The semiconductor structure of claim 5, wherein the first and second dielectric layers are made of substantially the same material.

7. The semiconductor structure of claim 1, wherein the protective layer and the first dielectric layer are made of different materials.

8. The semiconductor structure of claim 1, wherein the conductor completely fills a space laterally enclosed by the entire protective layer

9. A semiconductor structure, comprising:

a substrate;

at least one gate structure located on the substrate;

at least one spacer on at least one sidewall of the gate structure;

at least one source-drain structure located on the substrate;

at least one first dielectric layer at least on the gate structure and having an opening therein, wherein the source drain structure is exposed through the opening;

at least one conductor electrically connected to the source-drain structure at least through the opening;

at least one protective layer between the conductor and the spacer and between the first dielectric layer and the gate structure; and

a second dielectric layer between the conductor and the spacer, wherein the protective layer is over the second dielectric layer and separated from the source drain structures by the second dielectric layer, wherein, in a cross-sectional view, the protective layer has vertical portions extending laterally beyond the spacer, the vertical portions each contacting the conductor and the width of the vertical portions increasing linearly from top to bottom,

wherein sidewalls of the conductor extend continuously from a top surface of the protective layer through the protective layer to a bottom surface of the protective layer at corners of respective ones of the at least one gate structure,

wherein the at least one gate structure comprises a diffusion barrier layer, wherein a lower portion of the diffusion barrier layer and an upper portion located above the lower portion comprise different materials.

10. A method of fabricating a semiconductor structure, the method comprising:

forming a first dielectric layer on the at least one source drain structure and between the at least one first gate structure and the at least one second gate structure;

removing the upper part of the first dielectric layer to enable the first dielectric layer, the first gate structure and the second gate structure to form a groove;

forming a protective layer on at least one side wall of the groove, wherein the protective layer is separated from the source drain structure through the first dielectric layer;

forming a second dielectric layer on the first gate structure, the second gate structure, the protective layer, and the first dielectric layer;

forming holes in the first dielectric layer and the second dielectric layer to expose the source drain structures; and

forming a conductor in the hole, wherein the conductor is electrically connected to the source drain structure,

wherein, in a cross-sectional view, the protective layer has vertical portions extending laterally beyond the first gate structure, the vertical portions each being in contact with the conductor and the width of the vertical portions increasing linearly from top to bottom,

wherein sidewalls of the conductor extend continuously from a top surface of the protective layer through the protective layer to a bottom surface of the protective layer at corners of respective ones of the first and second gate structures,

the source-drain structure comprises at least one source-drain stress source.

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to semiconductor structures and methods of fabricating the same.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, or other electronic devices. The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area.

The term "interconnect" in an integrated circuit refers to a conductive line connecting various electronic components. The interconnecting conductive line is separated from the substrate by an insulating layer except on the contact region. As feature densities increase, the widths of the conductive lines and the size of the spaces between the conductive lines in the interconnect structure also become smaller.

Disclosure of Invention

According to an embodiment of the present invention, a semiconductor structure includes: a substrate; at least one first gate structure on the substrate; at least one first spacer on at least one sidewall of the first gate structure; at least one source drain structure adjacent to the first spacer; at least one conductor electrically connected to the source drain structure; and at least one protective layer between the conductor and the first spacer and on a top surface of the first gate structure.

According to an embodiment of the present invention, a semiconductor structure includes: a substrate; at least one gate structure on the substrate; at least one spacer on at least one sidewall of the gate structure; at least one source-drain structure located on the substrate; at least one first dielectric layer at least on the gate structure and having an opening in the at least one first dielectric layer, wherein the source drain structure is exposed through the opening; at least one conductor electrically connected to the source-drain structure at least through the opening; and at least one protective layer between the conductor and the spacer and between the first dielectric layer and the gate structure.

According to an embodiment of the present invention, a method of fabricating a semiconductor structure, the method comprising: forming a first dielectric layer on the at least one source drain structure and between the at least one first gate structure and the at least one second gate structure; removing the upper part of the first dielectric layer to enable the first dielectric layer, the first grid structure and the second grid structure to form a groove; forming a protective layer on at least one sidewall of the groove; forming a second dielectric layer on the first gate structure, the second gate structure, the protective layer and the first dielectric layer; forming holes in the first dielectric layer and the second dielectric layer to expose the source drain structures; and forming a conductor in the hole, wherein the conductor is electrically connected to the source drain structure.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-9 are cross-sectional views of methods for fabricating semiconductor structures at various stages according to some embodiments of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features provided by the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and/or configurations discussed.

Furthermore, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," or "including" and/or "including" or "having" and/or "having," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the listed related substances.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1-9 are cross-sectional views of methods for fabricating semiconductor structures at various stages according to some embodiments of the invention.

Refer to fig. 1. A semiconductor structure is formed. The semiconductor structure includes: substrate 110, gate structures 121 and 123, and at least one source drain structure 130. Gate structures 121 and 123 are located on substrate 110. Source drain structures 130 are located on substrate 110 and source drain structures 130 are adjacent to gate structures 121 and 123. In other words, source drain structure 130 is located between gate structures 121 and 123. It is noted that the number of gate structures 121 and 123 and the number of source drain structures 130 are illustrative and should not limit the various embodiments of the present invention. The number of gate structures 121 and 123 and the number of source drain structures 130 may be determined according to practical situations.

In some embodiments, for example, the substrate 110 may be made of a semiconductor material and a Graded layer (Graded layer) or a buried oxide may be included in the substrate 110. In some embodiments, substrate 110 comprises bulk silicon, which may be undoped or doped (e.g., P-type, N-type, or combinations thereof). Other suitable materials for semiconductor device formation may be used. For example, germanium, quartz, sapphire, and glass may be optionally used for the substrate 110. Alternatively, the substrate 110 may be an active layer substrate of a semiconductor-on-insulator (SOI) or a multilayer structure, such as a silicon germanium layer formed on a bulk silicon layer.

In some embodiments, at least one stack of a gate dielectric layer, a diffusion barrier layer, a metal layer, a bulk layer, a wetting layer, and a fill metal forms at least one gate structure 121 and 123. In other words, the at least one gate structure 121 and 123 may include a stack of a gate dielectric layer, a diffusion barrier layer, a metal layer, a bulk layer, a wetting layer, and a filling metal.

In some embodiments, the gate dielectric layer includes an interfacial layer (IL, a lower portion of the gate dielectric layer) that is a dielectric layer. In some embodiments, the IL comprises an oxide layer (such as a silicon oxide layer), and the IL may be formed by a thermal oxidation, chemical oxidation, or deposition step of the substrate 110. The gate dielectric layer may also include a high-k dielectric layer (upper portion of the gate dielectric layer) that includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, or combinations thereof. The dielectric constant (k value) of high-k dielectric materials is higher than about 3.9, and the dielectric constant of high-k dielectric materials can be higher than about 7, and sometimes the dielectric constant of high-k dielectric materials is as high as about 21 or higher. The high-k dielectric layer covers the IL and the high-k dielectric layer may contact the IL.

In some embodiments, the diffusion barrier layer comprises TiN, TaN, or a combination thereof. For example, the diffusion barrier layer may include a TiN layer (lower portion of the diffusion barrier layer) and a TaN layer (upper portion of the diffusion barrier layer) over the TiN layer.

When one of the gate structures 121 and 123 forms an n-type Metal Oxide Semiconductor (MOS) device, the metal layer is in contact with the diffusion barrier layer. For example, in embodiments where the diffusion barrier layer includes a TiN layer and a TaN layer, the metal layer may be in physical contact with the TaN layer. In other embodiments where one of the gate structures 121 and 123 forms a p-type MOS device, an additional TiN layer is formed between the TaN layer (in the diffusion barrier layer) and the overlying metal layer, and the additional TiN layer is in contact with the TaN layer and the overlying metal layer. The additional TiN layer provides a work function suitable for pMOS devices that is higher than the mid-gap (mid-gap) work function (about 4.5eV), which is the median of the valence and conduction bands of silicon. A work function higher than the mid-gap work function is referred to as a p-work function, and the corresponding metal with a p-work function is referred to as a p-metal.

The metal layer provides a work function suitable for the nMOS device, which is lower than the mid-gap work function. A work function lower than the mid-gap work function is referred to as an n-work function, and the corresponding metal with an n-work function may be referred to as an n-metal. In some embodiments, the metal layer is an n-metal having a work function of less than about 4.3 eV. The workfunction of the metal layer may also range from about 3.8eV to about 4.6 eV. According to some embodiments, the metal layer may comprise titanium aluminum (TiAl) (which may comprise other elements, or be free of other elements or substantially free of other elements). Forming the metal layer may be achieved by Physical Vapor Deposition (PVD). According to some embodiments of the invention, the metal layer is formed at room temperature (e.g., from about 20 ℃ to about 25 ℃). In other embodiments, the metal layer is formed at an elevated temperature above room temperature, e.g., above about 200 ℃.

In some embodiments, the bulk layer may comprise TiN. The bulk layer may be formed using Atomic Layer Deposition (ALD).

During reflow of the filler metal, the wetting layer has the ability to adhere to (and wet) the subsequently formed filler metal. In some embodiments, the wetting layer is a cobalt layer, which may be formed using Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD).

The filler metal may include aluminum, an aluminum alloy (e.g., titanium aluminum), tungsten, or copper, and the filler metal may also be formed using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like. The filler metal may be reflowed. The formation of the wetting layer improves the wettability of the underlying layer by the filler metal.

Source drain structures 130 may be formed by depositing impurities into at least one active semiconductor fin, for example, source drain structures 130 are formed by patterning and etching substrate 110 using photolithographic techniques. In some embodiments, the resulting MOS device is an nMOS device, and an n-type impurity such as phosphorous or arsenic may be doped in the source drain structure 130. In some other embodiments, the resulting MOS device is a pMOS device, and source drain structures 130 may be doped with a dopant such as boron or BF₂P-type impurity of (1).

Alternatively, the source drain structure 130 may be formed by epitaxial growth, for example. In some embodiments, source drain structures 130 may be used as source drain stressors to enhance carrier mobility and device performance of the semiconductor device. The source drain structures 130 may be formed using a Cyclic Deposition and Etch (CDE) process. The CDE process includes an epitaxial deposition/partial etch process and the epitaxial deposition/partial etch process is repeated at least once.

In some embodiments, the resulting MOS device is an nMOS device and source drain structure 130 may be an n-type epitaxial structure. In some embodiments, the resulting MOS device is a pMOS device and source drain structure 130 may be a p-type epitaxial structure. The n-type epitaxial structure may be made of a semiconductor material including SiP, SiC, SiPC, Si, III-V compound, or a combination thereof, and the p-type epitaxial structure may be made of SiGe, SiGeC, Ge, Si, III-V compound, or a combination thereof. During the formation of the n-type epitaxial structure, n-type impurities such as phosphorus or arsenic may be doped as the epitaxy proceeds. For example, when the n-type epitaxial structure includes SiP or SiC, n-type impurities are doped. In addition, during the formation of the p-type epitaxial structure, doping such as boron or BF may be performed as the epitaxy proceeds₂P-type impurity of (1). For example, when the p-type epitaxial structure includes SiGe, a p-type impurity is doped. Epitaxial processes include CVD deposition techniques (e.g., Vapor Phase Epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. Source drain structures 130 may be in-situ doped. If source drain structures 130 are not in-situ doped, a second implantation process (e.g., a junction implantation process) may be performed to dope the source drain structures 130. One or more anneal processes may be performed to activate the source drain structure 130. The annealing process includes a Rapid Thermal Annealing (RTA) and/or a laser annealing process.

In addition, spacers 141 are located on sidewalls of gate structure 121, and spacers 143 are located on sidewalls of gate structure 123. In some embodiments, at least one of spacers 140 and 143 comprises one or more layers comprising silicon nitride, silicon oxynitride, silicon oxide, or other dielectric material. Useful formation methods include Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), and other deposition methods.

Refer to fig. 2. Dielectric layer 150 is formed on gate structures 121 and 123 and source drain structure 130, and at least partiallyIs located between gate structures 121 and 123 and on source drain structure 130. Dielectric layer 150 is an interlayer dielectric (ILD) layer. The dielectric layer 150 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the dielectric layer 150 is made of a low-k dielectric material to improve the resistance-capacitance (RC) delay. The low-k dielectric material has a dielectric constant lower than that of silicon dioxide (SiO)₂) The dielectric constant of (2). One method of reducing the dielectric constant of a dielectric material is to introduce carbon (C) atoms or fluorine (F) atoms. For example, in SiO₂(k ═ 3.9), introduction of C atoms to form hydrogenated carbon-doped silicon oxide (SiCOH) (k between 2.7 and 3.3) and F atoms to form fluorosilicate glass (FSG) (k between 3.5 and 3.9) reduced its dielectric constant. In some embodiments, for example, the low-k dielectric material is nanoporous Carbon Doped Oxide (CDO), Black Diamond (BD), benzocyclobutene (BCB) based polymers, aromatic (hydrocarbon) thermoset polymers (ATP), Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), Polyarylether (PAE), nitrogen doped diamond-like carbon (DLC), or combinations thereof. For example, the dielectric layer 150 may be formed by Chemical Vapor Deposition (CVD), spin coating, or a combination thereof.

As shown in fig. 2 and 3, the dielectric layer 150 located over the gate structures 121 and 123 is removed by a removal process. In some embodiments, portions of the dielectric material 150 are removed by a Chemical Mechanical Polishing (CMP) process. After the CMP process, remaining dielectric layer 150 is located on source drain structure 130 and remaining dielectric layer 150 is located between gate structures 121 and 123.

Refer to fig. 4. The remaining upper portion of dielectric layer 150 is removed such that dielectric layer 150, gate structures 121 and 123, and spacers 141 and 143 form a recess 151. At least portions of the spacers 141 and 143 are exposed through the grooves 151. The top of the dielectric layer 150 is removed by an etching process. The etching of the dielectric layer 150 may be dry etching such as Reactive Ion Etching (RIE), Plasma Enhanced (PE) etching, or Inductively Coupled Plasma (ICP) etching. In some embodiments, when dielectric layer 150 is made of silicon oxide, a fluorine-based RIE may be used to form recess 151.For example, the gaseous etchant used to dry etch dielectric layer 150 is CF₄/O₂。

More specifically, the depth of the groove 151 is aboutToWithin the range of (1). Embodiments of the invention are not limited in this regard.

Refer to fig. 5. Protective layer 160 is formed on the top surfaces of gate structures 121 and 123, at least one sidewall of recess 151 (i.e., at least a portion of exposed spacers 141 and 143), and the bottom surface of recess 151 (i.e., the top surface of dielectric layer 150 over source drain structures 130). For example, the protection layer 160 may include silicon nitride, silicon oxynitride, or the like. The protective layer 160 may be formed using Atomic Layer Deposition (ALD), other suitable methods, or a combination thereof.

In fig. 6, a dielectric layer 170 is formed over gate structures 121 and 123, protective layer 160, and dielectric layer 150. The dielectric layer 170 is an interlayer dielectric (ILD) layer. The dielectric layer 170 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the dielectric layer 170 is made of a low-k dielectric material to improve the resistance-capacitance (RC) delay. The low-k dielectric material has a dielectric constant lower than that of silicon dioxide (SiO)₂) The dielectric constant of (2). In some embodiments, for example, the low-k dielectric material is hydrogenated carbon doped silicon oxide (SiCOH), fluorosilicate glass (FSG), nanoporous Carbon Doped Oxide (CDO), Black Diamond (BD), benzocyclobutene (BCB) based polymers, aromatic (hydrocarbon) thermosetting polymers (ATP), Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), Polyarylether (PAE), nitrogen doped diamond-like carbon (DLC), or combinations thereof. For example, the dielectric layer 170 may be formed by Chemical Vapor Deposition (CVD), spin coating, or a combination thereof.

Refer to fig. 6 and 7. A hole 171 is formed in the dielectric layers 150 and 170 to expose the source-drain structures 130, and a portion of the protective layer 160 located on the bottom surface of the groove 151 is removed when the hole 171 is formed. At least a portion of protective layer 160 is exposed through aperture 171. The hole 171 is formed by a photolithography and etching process. The photolithography and etching processes include applying photoresist, exposing, developing, etching, and removing the photoresist. A photoresist is applied to the dielectric layer 170, for example, by spin coating. The photoresist is then pre-baked to drive off excess photoresist solvent. After the pre-bake, the photoresist is exposed to a pattern of intense light.

For example, the intense light is G line having a wavelength of about 436nm, I line having a wavelength of about 365nm, KrF excimer laser having a wavelength of about 248nm, ArF excimer laser having a wavelength of about 193nm, fluoride (F) having a wavelength of about 157nm₂) An excimer laser, or a combination thereof. The gap between the final lens of the exposure tool and the photoresist surface may be filled with a liquid medium having a refractive index greater than that of the liquid medium during exposure to enhance lithographic resolution. Exposure to light causes a chemical change that allows some of the photoresist to dissolve in the developer.

A post-exposure bake (PEB) may then be performed prior to development to help reduce standing wave phenomena caused by destructive and constructive interference patterns of the incident light. A developer is then applied to the photoresist to remove some of the photoresist dissolved in the developer. The remaining photoresist is then hard baked to solidify the remaining photoresist.

At least a portion of the dielectric layer 170 not protected by the remaining photoresist is etched to form a hole 171. The etching of the dielectric layer 170 may be dry etching such as Reactive Ion Etching (RIE), Plasma Enhanced (PE) etching, or Inductively Coupled Plasma (ICP) etching. In some embodiments, when the dielectric layer 170 is made of silicon oxide, fluorine-based RIE may be used to form the holes 171. For example, the gaseous etchant used to dry etch dielectric layer 170 is CF₄/O₂。

For example, after the hole 171 is formed, the photoresist is removed from the dielectric layer 170 by plasma ashing, stripping, or a combination thereof. Plasma ashing uses a plasma source to generate monatomic reactive species, such as oxygen or fluorine. The reactive species combine with the photoresist to form an ash that is removed with a vacuum pump. A photoresist stripper such as acetone or a phenolic solvent is used in the stripping to remove the photoresist from the dielectric layer 170.

In addition, after forming the hole 171, at least a portion of the remaining dielectric layer 150 is located on the sidewalls of the hole 171. More specifically, portions of remaining dielectric layer 150 on the sidewalls of hole 171 are located on spacers 141 and 143 on the sidewalls of gate structures 121 and 123.

Referring to fig. 8, a conductive layer 180 overfills the holes 171. The conductive layer 180 is made of a metal such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), tantalum (Ta), or a combination thereof. For example, conductive layer 180 is formed by electrochemical deposition, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or combinations thereof.

Then, as shown in fig. 8 and 9, the excess conductive layer 180 located outside the hole 171 is removed. The excess conductive layer 180 located outside the hole 171 is removed by a removal process. In some embodiments, the overburden conductive layer 180 is removed by a Chemical Mechanical Polishing (CMP) process. In some embodiments, for example, when conductive layer 180 is made of copper (Cu), the CMP slurry is made of a mixture of suspended abrasive particles, an oxidizing agent, and a corrosion inhibitor, and the CMP slurry is acidic. After the CMP process, a conductor 181 (conductive layer 180) is formed in the hole 171. Conductor 181 is electrically connected to source drain structure 130 and protective layer 160 is positioned between conductor 181 and spacer 141 while protective layer 160 is positioned between conductor 181 and spacer 143.

In accordance with another aspect of the present invention, a semiconductor structure 100 is provided. Semiconductor structure 100 includes a substrate 100, gate structures 121 and 123, spacers 141 and 143, at least one source drain structure 130, at least one conductor 181, and at least one protective layer 160. Gate structures 121 and 123 are located on substrate 110. Spacers 141 are located on at least one sidewall of gate structure 121 and spacers 143 are located on at least one sidewall of gate structure 123. Source drain structure 130 is located on substrate 110 and source drain structure 130 is adjacent to spacers 141 and 143, while source drain structure 130 is located between spacers 141 and 143. Conductor 181 is electrically connected to source drain structure 130. Protective layer 160 is located between conductor 181 and spacer 141 and protective layer 160 is located between conductor 181 and spacer 143, with protective layer 160 being located on the top surfaces of gate structures 121 and 123.

More specifically, the protection layer 160 is made of a dielectric material such as silicon nitride, silicon oxynitride, or a combination thereof. Embodiments of the invention are not limited in this regard.

More specifically, the distance between the top and bottom surfaces of the portion of the protective layer 160 located between the spacer 141 and the conductor 181 is aboutToWithin the range of (1). The distance between the top and bottom surfaces of the portion of the protective layer 160 located between the spacer 143 and the conductor 181 is aboutToWithin the range of (1). Embodiments of the invention are not limited in this regard.

The semiconductor structure 100 further includes a dielectric layer 170. The dielectric layer 170 is at least on the protection layer 160 and has an opening O at least in the dielectric layer 170. Source drain structures 130 are exposed through opening O and at least a portion of conductor 181 is located in opening O. Conductor 181 is electrically connected to source drain structure 130 through at least opening O. Furthermore, the protection layer 160 is not located in the opening O of the dielectric layer 170, and the protection layer 160 is located between the dielectric layer 170 and the gate structure 121, while the protection layer 160 is located between the dielectric layer 170 and the gate structure 123.

The semiconductor structure 100 further includes a dielectric layer 150. Dielectric layer 150 is located between conductor 181 and spacer 141 and dielectric layer 150 is located between conductor 181 and spacer 143. The passivation layer 160 is disposed over the dielectric layer 150. That is, dielectric layer 150 is located between protective layer 160 and source drain structure 130.

Source drain structure 130 may include at least one source drain stressor. Embodiments of the invention are not limited in this regard.

The protective layer 160 may protect the spacers 141 and 143 from being over-etched during formation of the holes 171. Thus, after conductor 181 is formed, conductor 181 can be electrically isolated from gate structures 121 and 123 without causing short-circuit faults and/or leakage problems. With the protective layer 160, the device size can be further reduced without imposing heavy loads on the photolithography and etching processes, and thus the device performance can be improved. Furthermore, the need for overlay and patterning loads may be reduced. In addition, the protective layer 60 may enlarge a process window for the formation of contact holes while improving on-line control in a semiconductor device manufacturing process. Accordingly, reliability and/or yield in manufacturing the semiconductor device may be improved.

According to some embodiments of the invention, a semiconductor structure comprises: the semiconductor device comprises a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor and at least one protective layer. The first gate structure is located on the substrate. The first spacer is located on at least one sidewall of the first gate structure. The source and drain structures are adjacent to the first spacer. The conductor is electrically connected to the source drain structure. A protective layer is between the conductor and the first spacer and on a top surface of the first gate structure.

According to some embodiments of the invention, a semiconductor structure comprises: the semiconductor device comprises a substrate, at least one gate structure, at least one spacer, at least one source drain structure, at least one first dielectric layer and at least one protective layer. The gate structure is located on the substrate. The spacer is located on at least one sidewall of the gate structure. The source and drain structure is located on the substrate. The first dielectric layer is at least located on the gate structure and has an opening in the first dielectric layer, and the source and drain structures are exposed through the opening. The conductor is electrically connected to the source drain structure at least through the opening. A protective layer is between the conductor and the spacer and a protective layer is between the first dielectric layer and the gate structure.

According to some embodiments of the present invention, a method for fabricating a semiconductor structure includes the following steps. A first dielectric layer is formed over the at least one source drain structure and between the at least one first gate structure and the at least one second gate structure. Removing the upper part of the first dielectric layer to enable the first dielectric layer, the first grid structure and the second grid structure to form a groove; a protective layer is formed on at least one sidewall of the recess. And forming a second dielectric layer on the first gate structure, the second gate structure, the protective layer and the first dielectric layer. A hole is formed in the first dielectric layer and the second dielectric layer. A conductor is formed in the hole, wherein the conductor is electrically connected to the source drain structure.

According to an embodiment of the present invention, a semiconductor structure includes: a substrate; at least one first gate structure on the substrate; at least one first spacer on at least one sidewall of the first gate structure; at least one source drain structure adjacent to the first spacer; at least one conductor electrically connected to the source drain structure; and at least one protective layer between the conductor and the first spacer and on a top surface of the first gate structure.

According to an embodiment of the present invention, the protective layer is made of silicon nitride, silicon oxynitride, or a combination thereof.

According to an embodiment of the present invention, further comprising: at least one second gate structure on the substrate; and at least one second spacer located on at least one sidewall of the second gate structure, wherein the source-drain structure is located between the first spacer and the second spacer.

According to an embodiment of the present invention, a protective layer is also located between the conductor and the second spacer, and the protective layer is located on a top surface of the second gate structure.

According to an embodiment of the present invention, further comprising: and a first dielectric layer located between the conductor and the first spacer and between the protective layer and the source-drain structure.

According to an embodiment of the present invention, further comprising: and a second dielectric layer at least on the protective layer, the second dielectric layer having an opening therein, wherein at least a portion of the conductor is located in the opening.

According to an embodiment of the invention, the first dielectric layer and the second dielectric layer are made of substantially the same material.

According to an embodiment of the invention, the protective layer and the first dielectric layer are made of different materials.

According to an embodiment of the present invention, a semiconductor structure includes: a substrate; at least one gate structure on the substrate; at least one spacer on at least one sidewall of the gate structure; at least one source-drain structure located on the substrate; at least one first dielectric layer at least on the gate structure and having an opening in the at least one first dielectric layer, wherein the source drain structure is exposed through the opening; at least one conductor electrically connected to the source-drain structure at least through the opening; and at least one protective layer between the conductor and the spacer and between the first dielectric layer and the gate structure.

According to an embodiment of the present invention, the protective layer is not located in the opening of the first dielectric layer.

According to an embodiment of the present invention, further comprising: a second dielectric layer between the conductor and the spacer, wherein the protective layer is over the second dielectric layer.

According to an embodiment of the invention, the protective layer and the second dielectric layer are made of different materials.

According to an embodiment of the present invention, the protective layer is made of silicon nitride, silicon oxynitride, or a combination thereof.

According to an embodiment of the present invention, a method of fabricating a semiconductor structure, the method comprising: forming a first dielectric layer on the at least one source drain structure and between the at least one first gate structure and the at least one second gate structure; removing the upper part of the first dielectric layer to enable the first dielectric layer, the first grid structure and the second grid structure to form a groove; forming a protective layer on at least one sidewall of the groove; forming a second dielectric layer on the first gate structure, the second gate structure, the protective layer and the first dielectric layer; forming holes in the first dielectric layer and the second dielectric layer to expose the source drain structures; and forming a conductor in the hole, wherein the conductor is electrically connected to the source drain structure.

According to an embodiment of the invention, a hole is formed in the first dielectric layer in a remaining portion on a sidewall of the hole.

According to an embodiment of the invention, a portion of the first dielectric layer on the sidewalls of the hole remains on the at least one spacer of at least one of the first gate structure and the second gate structure.

According to an embodiment of the present invention, forming the protective layer forms the protective layer on at least the spacer of one of the first gate structure and the second gate structure.

According to an embodiment of the present invention, forming the protective layer further forms a part of the protective layer on the bottom surface of the groove; and wherein forming the hole removes a portion of the protective layer on the bottom surface of the recess.

According to an embodiment of the present invention, forming the protective layer further forms a portion of the protective layer on at least one of the first gate structure and the second gate structure.

According to an embodiment of the present invention, the protective layer is made of silicon nitride, silicon oxynitride, or a combination thereof.

The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.