阅读说明：本技术 半导体器件中孔、半导体器件的制备方法及半导体器件 (Semiconductor device, method for manufacturing semiconductor device, and semiconductor device ) 是由 夏军 刘涛 宛强 姜正秀 占康澍 李森 于 2020-05-22 设计创作，主要内容包括：本发明实施例公开了一种半导体器件中孔、半导体器件的制备方法及半导体器件,包括：提供一待刻蚀基底,并在待刻蚀基底上形成掩膜层；在掩膜层上形成具有阵列排布的第一图案层；以第一图案层为掩膜刻蚀掩膜层,以形成第一孔和第二图案层；在第二图案层远离待刻蚀基底的一侧沉积保护层,保护层同时覆盖第一孔的侧壁和底部；刻蚀覆盖第一孔的底部的保护层；以第二图案层和覆盖第一孔的侧壁的保护层为掩膜刻蚀支撑层,以形成第二孔；其中,第二孔的关键尺寸小于第一孔的关键尺寸。以解决现有技术中如果孔的尺寸较小,会出现无法刻蚀透的现象,而如果加大孔的尺寸,又不能满足半导体器件小尺寸的需求的问题。(The embodiment of the invention discloses a method for preparing a hole in a semiconductor device, a semiconductor device and a semiconductor device, wherein the method comprises the following steps: providing a substrate to be etched, and forming a mask layer on the substrate to be etched; forming a first pattern layer with array arrangement on the mask layer; etching the mask layer by taking the first pattern layer as a mask to form a first hole and a second pattern layer; depositing a protective layer on one side of the second pattern layer, which is far away from the substrate to be etched, wherein the protective layer covers the side wall and the bottom of the first hole at the same time; etching the protective layer covering the bottom of the first hole; etching the supporting layer by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole; wherein the critical dimension of the second hole is smaller than the critical dimension of the first hole. The problem that in the prior art, if the size of the hole is small, the phenomenon that etching cannot be conducted can be caused, and if the size of the hole is increased, the requirement of a small size of a semiconductor device cannot be met is solved.)

1. A method of fabricating a hole in a semiconductor device, comprising:

providing a substrate to be etched, and forming a mask layer on the substrate to be etched;

forming a first pattern layer with array arrangement on the mask layer;

etching the mask layer by taking the first pattern layer as a mask to form a first hole and a second pattern layer;

depositing a protective layer on one side of the second pattern layer, which is far away from the substrate to be etched, wherein the protective layer covers the side wall and the bottom of the first hole at the same time;

etching the protective layer covering the bottom of the first hole;

etching the substrate to be etched by taking the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole;

wherein the critical dimension of the second hole is smaller than the critical dimension of the first hole.

2. The method for preparing a hole in a semiconductor device according to claim 1, wherein the second hole comprises any one of a capacitor hole, a wiring hole, or a through hole.

3. The method for producing a hole in a semiconductor device according to claim 1, wherein the second hole comprises a capacitive hole; the substrate to be etched comprises a capacitor hole substrate; the capacitance hole base comprises a semiconductor substrate and a supporting layer formed on the semiconductor substrate;

providing a substrate to be etched, and forming a mask layer on the substrate to be etched, wherein the method comprises the following steps:

providing a semiconductor substrate, and sequentially forming a supporting layer and a mask layer on the semiconductor substrate;

etching the substrate to be etched by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole, including:

and etching the supporting layer to the semiconductor substrate by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form the capacitor hole.

4. A method for forming a hole in a semiconductor device as claimed in claim 1, wherein a material of the protective layer includes polysilicon.

5. A method for preparing a hole in a semiconductor device according to any of claims 1 to 4, wherein depositing a protective layer on a side of the second pattern layer remote from the substrate to be etched comprises:

and depositing a protective layer on one side of the second pattern layer far away from the substrate to be etched by utilizing an atomic layer deposition process.

6. The method for preparing a hole in a semiconductor device according to claim 3, further comprising, before the sequentially forming the support layer and the mask layer on the semiconductor substrate:

and forming a plurality of electrode contact blocks on the semiconductor substrate, wherein adjacent electrode contact blocks are isolated by a block-shaped insulating structure.

7. A method of fabricating a hole in a semiconductor device as claimed in claim 6, characterized in that a perpendicular projection of the second hole in a plane of the semiconductor substrate is located within a perpendicular projection of the electrode contact block in a plane of the semiconductor substrate.

8. The method for producing a hole in a semiconductor device according to claim 1, wherein the protective layer is a single-layer protective layer.

9. A method for producing a semiconductor device, comprising the method for producing a hole in a semiconductor device according to any one of claims 1 to 8.

10. A semiconductor device produced by the method for producing a semiconductor device according to claim 9.

Technical Field

The embodiment of the invention relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method of a hole in the semiconductor device and the semiconductor device.

Background

With the development of the semiconductor industry and the demand for increased portability, computing power, storage capacity, and energy efficiency in modern electronic devices, the size of semiconductor devices is continuously decreasing.

While a reduction in the size of the semiconductor device may be achieved by a reduction in the size of the formation structures in the semiconductor device, e.g., the size of the capacitive holes in the capacitive structure of the memory. However, if the size of the hole is small, i.e. the aspect ratio of the hole is large, the phenomenon of etching through failure may occur due to the limitation of the process conditions, and the subsequent process steps are affected. If the size of the hole is increased, the requirement for small size of the semiconductor device cannot be satisfied.

Disclosure of Invention

The embodiment of the invention provides a semiconductor device and a preparation method of a hole in the semiconductor device, and the semiconductor device, which are used for solving the problems that in the prior art, if the size of a capacitor hole is smaller, the phenomenon that etching cannot be conducted through occurs, and if the size of the hole is increased, the requirement of the small size of the semiconductor device cannot be met.

In a first aspect, embodiments of the present invention provide a method for preparing a hole in a semiconductor device, the method including:

providing a substrate to be etched, and forming a mask layer on the substrate to be etched;

forming a first pattern layer with array arrangement on the mask layer;

etching the mask layer by taking the first pattern layer as a mask to form a first hole and a second pattern layer;

depositing a protective layer on one side of the second pattern layer, which is far away from the substrate to be etched, wherein the protective layer covers the side wall and the bottom of the first hole at the same time;

etching the protective layer covering the bottom of the first hole;

etching the substrate to be etched by taking the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole;

wherein the critical dimension of the second hole is smaller than the critical dimension of the first hole.

Optionally, the second hole includes any one of a capacitor hole, a wire connection hole, or a through hole.

Optionally, the second aperture comprises a capacitive aperture; the substrate to be etched comprises a capacitor hole substrate; the capacitance hole base comprises a semiconductor substrate and a supporting layer formed on the semiconductor substrate;

providing a substrate to be etched, and forming a mask layer on the substrate to be etched, wherein the method comprises the following steps:

providing a semiconductor substrate, and sequentially forming a supporting layer and a mask layer on the semiconductor substrate;

etching the substrate to be etched by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole, including:

and etching the supporting layer to the semiconductor substrate by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form the capacitor hole.

Optionally, the material of the protective layer comprises polysilicon.

Optionally, depositing a protective layer on a side of the second pattern layer away from the substrate to be etched includes:

and depositing a protective layer on one side of the second pattern layer far away from the substrate to be etched by utilizing an atomic layer deposition process.

Optionally, before the sequentially forming the support layer and the mask layer on the semiconductor substrate, the method further includes:

and forming a plurality of electrode contact blocks on the semiconductor substrate, wherein adjacent electrode contact blocks are isolated by a block-shaped insulating structure.

Optionally, a perpendicular projection of the second hole on the plane of the semiconductor substrate is located within a perpendicular projection of the electrode contact block on the plane of the semiconductor substrate.

Optionally, the protective layer is a single protective layer.

In a second aspect, embodiments of the present invention further provide a method for manufacturing a semiconductor device, where the method includes a method for manufacturing a hole in a semiconductor device as described in the first aspect.

In a third aspect, the embodiment of the present invention further provides a method for manufacturing a semiconductor device, which is obtained by the method for manufacturing a semiconductor device according to the second aspect.

According to the method for preparing the hole in the semiconductor device and the semiconductor device, the protective layer is deposited on one side, far away from the substrate to be etched, of the second pattern layer, and the protective layer covers the side wall of the first hole at the same time, so that the key size of the first hole between the adjacent second pattern layers is reduced, when the substrate to be etched is etched by taking the second pattern layer and the protective layer covering the side wall of the first hole as masks, the size of the obtained second hole is smaller, therefore, the problem that etching cannot be conducted through due to the fact that the depth of the first hole is larger is solved, meanwhile, a smaller hole can be obtained, the requirement for the small size of the semiconductor device is met, the integration level of the semiconductor device is improved, and the process is simple.

Drawings

Fig. 1 is a flowchart of a method for fabricating a hole in a semiconductor device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram illustrating a first pattern layer formed according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a structure after forming a first hole according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram after forming a protective layer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a structure after forming a second hole according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method for fabricating a hole in a semiconductor device according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a structure after a first pattern layer is formed according to another embodiment of the present invention;

FIG. 8 is a schematic view of another structure after forming a first hole according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a protective layer formed according to another embodiment of the present invention;

fig. 10 is a schematic structural diagram of another structure after forming the second hole according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In view of the problems in the background art, embodiments of the present invention provide a method for fabricating a hole in a semiconductor device. Fig. 1 is a flowchart of a method for manufacturing a hole in a semiconductor device according to an embodiment of the present invention, and as shown in fig. 1, the method for manufacturing a hole in a semiconductor device according to an embodiment of the present invention includes the following steps:

s110, providing a substrate to be etched, and forming a mask layer on the substrate to be etched.

Referring to fig. 2, the substrate 10 to be etched may include, for example, a substrate in a semiconductor device, such as a capacitor hole substrate, a wire hole substrate, or a through hole substrate, the type of the substrate is not limited in this embodiment, and for example, the substrate 10 to be etched includes a capacitor hole substrate. The mask layer 30 serves as a mask for subsequent etching of the substrate 10 to be etched. The mask layer 30 has a larger thickness, so that the mask layer 30 is used as a mask to etch the substrate 10 to be etched in the following step, so as to form a second subsequent hole. Optionally, the mask layer 30 may have a single-layer structure or a multi-layer stacked structure, and this implementation is not particularly limited; the material of the mask layer is not limited in this embodiment.

S120, forming a first pattern layer with array arrangement on the mask layer; and etching the mask layer by taking the first pattern layer as a mask to form a first hole and a second pattern layer.

Referring to fig. 2 and 3, specifically, a photoresist layer may be formed as the material of the first pattern layer 40, and it is understood that the first pattern layer 40 of other materials, for example, a silicon nitride layer, may be formed in other embodiments. The layer material is then patterned using a photolithography process to obtain a first patterned layer 40. First patterning layer 40 defines the location and shape of the subsequently formed first aperture. Then, the mask layer 30 is etched using the first pattern layer 40 as a mask, and a first hole 31 and a second pattern layer 32 are formed in the mask layer 30, wherein the cross section of the first hole 31 may be, for example, circular, and the critical dimension of the first hole 31 is M1.

S130, depositing a protective layer on one side, far away from the substrate to be etched, of the second pattern layer, wherein the protective layer covers the side wall and the bottom of the first hole at the same time.

Referring to fig. 4, the material of the protection layer 50 may be, for example, polysilicon or silicon nitride, and the embodiment is not particularly limited as long as a high etching selectivity ratio between the protection layer 50 and the mask layer 30 is ensured. Wherein, a protective layer 50 can be deposited on the second pattern layer 32 by using atomic layer deposition or chemical vapor deposition. When the material of the protection layer 50 is polysilicon and is deposited by an atomic deposition method, the deposition uniformity of the protection layer 50 is better, and the shape of the obtained second hole is more accurate in the subsequent process. Optionally, the protection layer 50 is a single-layer protection layer or a multi-layer protection layer, and when the protection layer 50 is a single layer, the requirement of reducing the critical dimension of the first hole 31 can be met, and meanwhile, the number of process steps is not increased. Alternatively, the thickness of the protection layer 50 may be set according to the expected critical dimension of the second hole, and the embodiment is not limited.

Specifically, it is considered that when the aspect ratio of the first hole 31 is large, that is, the critical dimension of the first hole 31 is small, the problem of etching-through may occur, and thus, the subsequent process is affected. Therefore, in this embodiment, after the first holes 31 are fully etched, at this time, the distance between the second pattern layers 32, that is, the critical dimension of the first holes 31 is large, a protective layer 50 is deposited on the side of the second pattern layer 32 away from the substrate 10 to be etched, and the sidewall and the bottom of the first holes 31 are covered by the protective layer 50, so as to obtain new first holes 31 ', where the critical dimension of the new first holes 31' is small. The critical dimension of the newly formed first hole 31 'is the expected critical dimension, that is, when the protective layer and the second pattern layer on the two sides of the newly formed first hole 31' are used as masks, the expected second hole can be obtained, and then a corresponding structure can be prepared in the second hole, so that a corresponding semiconductor device can be obtained, and the obtained semiconductor device meets the requirement of the small size of the semiconductor device.

S140, etching the protective layer covering the bottom of the first hole; etching the substrate to be etched by taking the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a second hole; wherein the critical dimension of the second hole is smaller than the critical dimension of the first hole.

Referring to fig. 4 and 5, specifically, the supporting layer 20 is etched by using the second pattern layer 32 and the protective layer 50 covering the sidewalls of the first hole 31 as masks to form the second hole 60, so that the critical dimension of the second hole 60 is reduced compared to when the second pattern layer 32 is used as a mask, thereby not only ensuring sufficient etching of the first hole 31, but also obtaining a smaller second hole 60, meeting the requirement of a small size of a semiconductor device, and improving the integration level of the semiconductor device.

In summary, in the method for manufacturing a hole in a semiconductor device provided in the embodiments of the present invention, the protective layer is deposited on the side of the second pattern layer away from the substrate to be etched, and the protective layer covers the sidewall of the first hole, so that the critical dimension of the first hole between the adjacent second pattern layers is reduced.

On the basis of the above scheme, optionally, with continued reference to fig. 3, the aspect ratio of the first hole 31 is a, and a is greater than or equal to 8 and less than or equal to 20.

In this embodiment, the aspect ratio a of the first hole 31 is H1/M1, and when the aspect ratio of the first hole 31 is greater than or equal to 8 and less than or equal to 20, the first hole 31 is fully etched, so that the problem that the subsequent process is affected due to the etching impermeability of the first hole 31 is avoided.

Optionally, with reference to fig. 3, it is ensured that the aspect ratio of the first hole 31 is greater than or equal to 8 and less than or equal to 20 by reserving a portion of the first pattern layer 40, so as to prevent over-etching during etching the substrate 10 to be etched, thereby affecting the subsequent process.

Optionally, with continued reference to FIG. 5, the second pores 60 have a pore size B, B < 100 nm.

In this embodiment, when the aperture of the second hole 60 is smaller than 100nm, that is, the critical dimension of the second hole 60 is smaller, so that the integration level of the semiconductor device is improved.

Alternatively, fig. 6 is a flowchart of a method for manufacturing a hole in a semiconductor device according to another embodiment of the present invention, which illustrates a specific process of "when the hole in the semiconductor device is a capacitor hole". As shown in fig. 6, the method for preparing a hole in a semiconductor device may include:

s210, providing a semiconductor substrate, forming a plurality of electrode contact blocks on the semiconductor substrate, isolating adjacent electrode contact blocks through a block-shaped insulating structure, and sequentially forming a supporting layer and a mask layer on the semiconductor substrate.

Referring to fig. 7, the material of the semiconductor substrate 10 may be silicon, germanium, silicon cadmium, silicon carbide; or silicon-on-insulator, germanium-on-insulator; or a III-V compound such as gallium arsenide, and the like, and the present embodiment is not particularly limited. Optionally, a semiconductor device (not shown in the figure) is disposed on the semiconductor substrate 10, the semiconductor device may include, for example, a transistor and/or a capacitor, and a metal interconnection line (not shown in the figure) is further disposed on the semiconductor substrate 10. The electrode contact block 70 is used to connect a lower electrode layer of a capacitor to be formed later, and data stored in the capacitor can be read or written into the capacitor through the electrode contact block 70. The electrode contact block 70 is arranged in the same manner as the second hole, i.e., the capacitor hole, which is formed later. Illustratively, the electrode contact blocks 70 may be arranged in a hexagonal array. The material of the electrode contact block 70 may be, for example, metal, and the material of the electrode contact block 70 is, for example, tungsten, copper, aluminum, or the like. The support layer 20 is used to define the main structure of the semiconductor device to be formed later, for example, capacitor holes are formed in the support layer 20, the upper and lower electrode layers of the capacitor and the capacitor dielectric layer are formed in the capacitor holes, that is, the support layer 20 defines the depth of the capacitor hole and the height of the upper and lower electrode layers of the capacitor. The support layer 20 may include, for example, a stacked structure of the sacrificial elements 22 and the support elements 21 stacked alternately, so that the second holes 60 with a larger aspect ratio can be obtained, thereby greatly improving the capacitance per unit area and improving the integration and performance of the memory device. The material of the sacrificial unit 22 may include, for example, silicon oxide, silicon nitride, or polysilicon, and the sacrificial unit 22 may also be doped with boron or phosphorus, which can ensure uniformity of critical dimensions and improve the removal rate of the sacrificial unit; the material of the support unit 21 may be any one of silicon nitride and silicon oxynitride, or a combination of any two or more of them. The sacrificial unit 22 is removed in the subsequent process, and the supporting unit 21 is used as a supporting frame after the sacrificial unit 22 is removed in the subsequent process, so that the mechanical strength of the structure in the subsequent manufacturing of the capacitor can be greatly improved, and the damage to the capacitor caused by the subsequent process can be avoided. Alternatively, the number of the supporting units 21 and the sacrificial units 22 may be set according to the required height of the subsequent capacitor, for example, referring to fig. 7, the number of the supporting units 21 is 3, and the number of the sacrificial units 22 is 2.

S220, forming a first pattern layer with array arrangement on the mask layer; and etching the mask layer by taking the first pattern layer as a mask to form a first hole and a second pattern layer.

Referring to fig. 7 and 8, specifically, the mask layer 30 is etched using the first pattern layer 40 as a mask, and a first hole 31 and a second pattern layer 32 are formed in the mask layer 30.

And S230, depositing a protective layer on the side, away from the semiconductor substrate, of the second pattern layer, wherein the protective layer covers the side wall and the bottom of the first hole at the same time.

Referring to fig. 9, in particular, considering that when the aspect ratio of the first hole 31 is large, that is, the critical dimension of the first hole 31 is small, and thus a small-sized capacitor is obtained, the problem of etching-through may occur, and thus, the subsequent process is affected. Therefore, in this embodiment, after the first holes 31 are fully etched, at this time, the distance between the second pattern layers 32, that is, the critical dimension of the first holes 31 is larger, a protection layer 50 is deposited on the side of the second pattern layers 32 away from the semiconductor substrate 10, and the side walls and the bottom of the first holes 31 are covered by the protection layer 50, so as to obtain new first holes 31 ', where the critical dimension of the new first holes 31' is smaller. The key size of the newly formed first hole 31 'is an expected key size, that is, when the protective layer and the second pattern layer on the two sides of the newly formed first hole 31' are used as masks, an expected second hole 60, that is, a capacitor hole, may be obtained, and a corresponding structure may be prepared in the capacitor hole, for example, a lower electrode layer, a capacitor dielectric layer, etc. may be formed in the capacitor hole, so as to obtain a capacitor, which has a smaller size, thereby improving the integration level of the memory device.

S240, etching the protective layer covering the bottom of the first hole; etching the supporting layer to the semiconductor substrate by using the second pattern layer and the protective layer covering the side wall of the first hole as masks to form a capacitor hole and expose the electrode contact block; wherein the critical dimension of the second hole is smaller than the critical dimension of the first hole.

On the basis of the above-described solution, optionally, with continued reference to fig. 10, the perpendicular projection of the second aperture 60 onto the plane of the semiconductor substrate 10 is located within the perpendicular projection of the electrode contact block 70 onto the plane of the semiconductor substrate 10.

In this embodiment, when the vertical projection of the second hole 60 on the plane of the semiconductor substrate 10 is located in the vertical projection of the electrode contact block 70 on the plane of the semiconductor substrate 10, the subsequently formed lower electrode is ensured to be in sufficient contact with the electrode contact block 70, thereby increasing the speed of reading data stored in the capacitor or writing data into the capacitor through the electrode contact block 70.

In this embodiment, through the one side deposit protective layer that keeps away from the semiconductor substrate on the second pattern layer, the protective layer covers the lateral wall of first hole, thereby make the critical dimension of first hole between the adjacent second pattern layer reduce, when using the protective layer of second pattern layer and the lateral wall that covers first hole as the mask etching supporting layer, the size in electric capacity hole that obtains this moment is less, so, can not appear can't the problem that the sculpture can't pass through because the height and depth of first hole is bigger promptly, can also obtain less electric capacity hole simultaneously, improve the integrated level of semiconductor memory, and simple process.

Based on the same inventive concept, the embodiment of the invention also provides a preparation method of a semiconductor device, which comprises the preparation method of the hole in the semiconductor device in the embodiment. Since the method for manufacturing a semiconductor memory in the present embodiment is the same inventive concept as the method for manufacturing a hole in a semiconductor device in each of the above embodiments, reference may be made to the above embodiments of the method for manufacturing a hole in a semiconductor device, in which details are not described in detail in the embodiments of the method for manufacturing a semiconductor device.

Based on the same inventive concept, embodiments of the present invention further provide a semiconductor device, which belongs to the same inventive concept as the method for manufacturing the holes in the semiconductor devices of the above embodiments, so that the semiconductor device provided in embodiments of the present invention also has the beneficial effects described in the above embodiments, and details which are not described in detail in the embodiments of the semiconductor device may be referred to in the embodiments of the method for manufacturing the holes in the semiconductor device, and are not described again here. Illustratively, the semiconductor device may be a semiconductor memory or the like.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.