阅读说明：本技术 Nor型存储器件及其制造方法及包括存储器件的电子设备 (NOR type memory device, method of manufacturing the same, and electronic apparatus including the same ) 是由 朱慧珑 于 2021-08-02 设计创作，主要内容包括：公开了一种NOR型存储器件及其制造方法及包括该NOR型存储器件的电子设备。根据实施例,该NOR型存储器件可以包括：存储器件层,包括第一源/漏区和第二源/漏区以及第一源/漏区与第二源/漏区之间的第一沟道区；竖直延伸以穿过存储器件层的第一栅堆叠,包括第一栅导体层和设置在第一栅导体层与存储器件层之间的存储功能层,在第一栅堆叠与存储器件层相交之处限定存储单元；存储器件层上的选择器件层,包括第三源/漏区和第四源/漏区以及第三源/漏区与第四源/漏区之间的第二沟道区；设置在第一栅堆叠上方的第二栅堆叠,竖直延伸以穿过选择器件层；以及连接部,将第三源/漏区电连接到第一栅导体层。(A NOR-type memory device, a method of manufacturing the same, and an electronic apparatus including the NOR-type memory device are disclosed. According to an embodiment, the NOR type memory device may include: a memory device layer including first and second source/drain regions and a first channel region between the first and second source/drain regions; a first gate stack extending vertically to pass through the memory device layer, including a first gate conductor layer and a memory function layer disposed between the first gate conductor layer and the memory device layer, defining a memory cell where the first gate stack intersects the memory device layer; a select device layer on the memory device layer including third and fourth source/drain regions and a second channel region between the third and fourth source/drain regions; a second gate stack disposed over the first gate stack, extending vertically to pass through the select device layer; and a connection portion electrically connecting the third source/drain region to the first gate conductor layer.)

1. A NOR-type memory device comprising:

a memory device layer on a substrate, wherein the memory device layer includes a first source/drain region and a second source/drain region at opposite ends in a vertical direction and a first channel region between the first source/drain region and the second source/drain region in the vertical direction;

a first gate stack extending vertically relative to the substrate to pass through the memory device layer, the first gate stack including a first gate conductor layer and a memory functional layer disposed between the first gate conductor layer and the memory device layer, a memory cell being defined where the first gate stack intersects the memory device layer;

a select device layer on the memory device layer, including third and fourth source/drain regions at opposite ends in the vertical direction and a second channel region between the third and fourth source/drain regions in the vertical direction;

a second gate stack disposed over the first gate stack, extending vertically relative to the substrate to pass through the select device layer; and

a connection part electrically connecting the third source/drain region to the first gate conductor layer.

2. The NOR-type memory device of claim 1 comprising a plurality of the memory device layers stacked on the substrate,

wherein the first gate stack extends through each of the memory device layers, an

Wherein the select device layer is disposed above an uppermost memory device layer.

3. The NOR-type memory device of claim 1, wherein the connector is interposed between the first and second gate stacks in the vertical direction, and the first, connector, and second gate stacks are self-aligned in the vertical direction.

4. The NOR-type memory device of claim 1 wherein,

the second gate stack includes a second gate conductor layer and a gate dielectric layer disposed between the second gate conductor layer and the select device layer,

the second gate stack is arranged on the connecting portion, and the gate dielectric layer further extends between the second gate conductor layer and the connecting portion.

5. NOR-type memory device according to claim 3 or 4, wherein the connection portion comprises a conductive layer contacting the first gate conductor layer at a bottom surface and contacting the third source/drain region at a side surface.

6. The NOR-type memory device of claim 2, further comprising:

an isolation layer between adjacent layers of the plurality of memory device layers and the select device layer.

7. The NOR-type memory device of claim 1 or 2, wherein one of the first and second source/drain regions in each of the memory device layers is electrically connected to a corresponding bit line, and the other is electrically connected to a corresponding source line.

8. NOR-type memory device according to claim 1 or 2, comprising:

a plurality of the first gate stacks, wherein the plurality of the first gate stacks are arranged in an array in a first direction and a second direction intersecting each other in a plan view;

a plurality of the second gate stacks disposed over respective ones of the plurality of first gate stacks, respectively, wherein the select device layer includes separate portions around the plurality of second gate stacks, respectively, to define a plurality of select transistors arranged in an array including rows in the first direction and columns in the second direction;

a plurality of word lines extending in the first direction and arranged in the second direction, the word lines being electrically connected to the fourth/source drain regions of the selection transistors in the corresponding row, respectively; and

and a plurality of selection lines extending along the second direction and arranged in the first direction are respectively and electrically connected to the second gate stacks of the selection transistors of the corresponding columns.

9. The NOR-type memory device of claim 8, wherein the word line includes a conductive layer around the outer periphery of the select transistors of the corresponding row, the conductive layer contacting the fourth source/drain regions of the select transistors of the corresponding row.

10. A NOR-type memory device according to claim 1 or 2, wherein the memory function layer comprises at least one of a charge trapping material or a ferroelectric material.

11. The NOR-type memory device of claim 1 or 2, wherein the memory device layer and the select device layer each comprise a single crystalline semiconductor material.

12. A method of fabricating a NOR-type memory device, comprising:

stacking at least one memory device layer on a substrate, each memory device layer including first and second source/drain regions at opposite ends in a vertical direction and a first channel region between the first and second source/drain regions in the vertical direction;

forming a selection device layer on an uppermost memory device layer, the selection device layer including third and fourth source/drain regions at opposite ends in the vertical direction and a second channel region between the third and fourth source/drain regions in the vertical direction;

forming a plurality of process channels extending vertically with respect to the substrate to pass through the selection device layer and each of the memory device layers, wherein the plurality of process channels are arranged in an array including rows in a first direction and columns in a second direction crossing the first direction in a plan view;

forming a first gate stack in the process channel, the first gate stack including a first gate conductor layer and a memory function layer disposed between the first gate conductor layer and the memory device layer, a memory cell being defined where the first gate stack intersects the memory device layer;

separating the select device layer into portions that respectively surround the peripheries of the respective process channels in which the first gate stacks are formed;

forming a plurality of word lines extending in the first direction and arranged in the second direction, each word line surrounding a portion of the select device layer at the periphery of the process channel of a corresponding row and contacting a fourth source/drain region of the portion;

recessing the first gate stack to free an upper space of the process channel in which a third source/drain region of the select device layer is at least partially exposed;

forming a connection in the process channel on the first gate stack to electrically connect a third source/drain region of the select device layer to the first gate conductor layer;

forming a second gate stack on the connection in the process channel; and

and forming a plurality of selection lines extending along the second direction and arranged in the first direction, wherein the selection lines are respectively and electrically connected to the second gate stacks formed in the processing channels of the corresponding columns.

13. The method of claim 12, wherein the connecting portion is formed as a conductive layer in the process channel, the conductive layer contacting the first gate conductor layer at a bottom surface and contacting the third source/drain region at a side surface.

14. The method of claim 12, wherein separating the select device layer comprises:

recessing the first gate stack;

forming a cap layer on the first gate stack in the process channel;

forming a side wall on the side wall of the cap layer; and

and etching the selective device layer by taking the side wall as an etching mask.

15. The method of claim 12, further comprising:

forming a sacrificial layer between adjacent layers of the at least one memory device layer and the select device layer;

replacing the plurality of sacrificial layers with solid phase dopant source layers via the process channel;

dopants are driven from the solid phase dopant source layer into opposite ends of the memory device layer by annealing to form the first and second source/drain regions.

16. The method of claim 15, wherein the memory device layer, the select device layer, and the sacrificial layer are provided by epitaxial growth.

17. The method of claim 15, wherein replacing the sacrificial layer with a solid phase dopant source layer comprises:

forming a support layer in a portion of the process channels, while the sacrificial layer is exposed in the remaining process channels;

replacing the sacrificial layer with the solid phase dopant source layer via the process channel; and

and removing the supporting layer.

18. An electronic device comprising a NOR-type memory device as claimed in any of claims 1 to 11.

19. The electronic device of claim 18, wherein the electronic device comprises a smartphone, a personal computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to NOR-type memory devices, methods of manufacturing the same, and electronic devices including such memory devices.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the horizontal type device is not easily further downsized. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are more easily scaled down relative to horizontal devices.

For vertical devices, integration density can be increased by stacking one on top of the other. However, this may result in poor performance. Since polysilicon is generally used as the channel material for the convenience of stacking a plurality of devices, the resistance becomes large compared to that of a channel material of single crystal silicon. In addition, it is also desirable to be able to control the word lines using the selection switch device to save interconnect lines.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a NOR-type memory device having improved performance, a method of manufacturing the same, and an electronic apparatus including the same.

According to an aspect of the present disclosure, there is provided a NOR-type memory device including: a memory device layer on the substrate, wherein the memory device layer includes a first source/drain region and a second source/drain region at opposite ends in a vertical direction and a first channel region between the first source/drain region and the second source/drain region in the vertical direction; a first gate stack extending vertically with respect to the substrate to pass through the memory device layer, the first gate stack including a first gate conductor layer and a memory function layer disposed between the first gate conductor layer and the memory device layer, a memory cell being defined where the first gate stack intersects the memory device layer; a selection device layer on the memory device layer, including a third source/drain region and a fourth source/drain region at opposite ends in a vertical direction and a second channel region between the third source/drain region and the fourth source/drain region in the vertical direction; a second gate stack disposed over the first gate stack, extending vertically with respect to the substrate to pass through the select device layer; and a connection portion electrically connecting the third source/drain region to the first gate conductor layer.

According to another aspect of the present disclosure, there is provided a method of manufacturing a NOR-type memory device, including: stacking at least one memory device layer on a substrate, each memory device layer including first and second source/drain regions at opposite ends in a vertical direction and a first channel region between the first and second source/drain regions in the vertical direction; forming a selection device layer on the uppermost memory device layer, the selection device layer including third and fourth source/drain regions at opposite ends in a vertical direction and a second channel region between the third and fourth source/drain regions in the vertical direction; forming a plurality of process channels extending vertically with respect to the substrate to pass through the selection device layer and the respective memory device layers, wherein, in a plan view, the plurality of process channels are arranged in an array including rows in a first direction and columns in a second direction crossing the first direction; forming a first gate stack in the process channel, the first gate stack including a first gate conductor layer and a memory function layer disposed between the first gate conductor layer and the memory device layer, a memory cell being defined where the first gate stack intersects the memory device layer; separating the select device layer into portions respectively surrounding the peripheries of the respective process channels in which the first gate stacks are formed; forming a plurality of word lines extending in the first direction and arranged in the second direction, each word line surrounding a portion of the selection device layer at the periphery of the process channels of the corresponding row and contacting a portion of the fourth source/drain region; recessing the first gate stack to release an upper space of the process channel in which a third source/drain region of the select device layer is at least partially exposed; forming a connection in the process channel on the first gate stack to electrically connect the third source/drain region of the select device layer to the first gate conductor layer; forming a second gate stack on the connection portion in the process channel; and forming a plurality of selection lines extending in the second direction and arranged in the first direction, the plurality of selection lines being electrically connected to the second gate stacks formed in the corresponding columns of the process channels, respectively.

According to another aspect of the present disclosure, there is provided an electronic device including the NOR-type memory device described above.

According to the embodiments of the present disclosure, due to the introduction of the selection transistor, wiring can be reduced to save an area. A three-dimensional (3D) NOR type memory device can be built using a stack of single crystal materials as a building block. Therefore, when a plurality of memory cells are stacked on one another, an increase in resistance can be suppressed. In addition, source/drain doping can be performed by diffusion using a solid phase dopant source layer, which facilitates the formation of steep high source/drain doping.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1 to 19(c) show schematic diagrams of a middle staging of a process for fabricating a NOR-type memory device according to an embodiment of the present disclosure;

figure 20 schematically shows an equivalent circuit diagram of a NOR-type memory device according to an embodiment of the disclosure,

in which FIGS. 2(a), 7(a), 8(a), 13(a), 18(a), and 19(a) are plan views, and FIG. 2(a) shows the positions of AA 'and BB' lines,

FIGS. 1, 2(b), 3 to 6, 7(b), 8(b), 9 to 12, 13(b), 14(a), 15(a), 16(a), 17(a), 18(b), 19(b) are cross-sectional views taken along line AA',

fig. 14(b), 15(b), 16(b), 17(b), 18(c), and 19(c) are cross-sectional views along line BB'.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The memory device according to the embodiment of the present disclosure is based on a vertical type device. The vertical-type device may include an active region disposed in a vertical direction (a direction substantially perpendicular to a surface of a substrate) on the substrate, including source/drain regions disposed at upper and lower ends and a channel region located between the source/drain regions. A conductive path may be formed between the source/drain regions through the channel region. In the active region, the source/drain regions and the channel region may be defined by doping concentration, for example.

According to embodiments of the present disclosure, the active region may be defined by a device layer on the substrate. For example, the device layer may be a single semiconductor material layer or a stack of semiconductor material layers, the source/drain regions may be formed at opposite ends of the semiconductor layer or the stack, respectively, in the vertical direction, and the channel region may be formed in the middle of the semiconductor layer or the stack in the vertical direction. The gate stack may extend through the device layer such that the active region may surround a periphery of the gate stack. For the device layer (which may be referred to as "memory device layer") used to define the memory cell, the gate stack (which may be referred to as "first gate stack") passing therethrough may include a memory functional layer such as at least one of a charge trapping material or a ferroelectric material to perform a memory function. Thus, the first gate stack cooperates with the active region opposite thereto to define a memory cell. Here, the memory unit may be a flash memory (flash) unit. For the device layer used to define the select transistor (which may be referred to as the "select device layer"), the gate stack (which may be referred to as the "second gate stack") passing therethrough may not include a memory functional layer. The first gate stack and the second gate stack may be aligned in a vertical direction. They may be self-aligning, as described below.

A plurality of first gate stacks may be disposed to pass through the memory device layer and a corresponding plurality of second gate stacks to pass through the selection device layer to define a plurality of memory cells where the plurality of first gate stacks intersect the memory device layer and a plurality of selection transistors where the plurality of second gate stacks intersect the selection device layer. The memory cells are arranged in an array (e.g., a two-dimensional array typically arranged in rows and columns) corresponding to the plurality of first gate stacks in a plane in which the memory device layers are located.

Due to the easy stacking characteristic of the vertical type device, the memory device according to the embodiment of the present disclosure may be a three-dimensional (3D) array. In particular, a plurality of such memory device layers may be disposed in a vertical direction. The first gate stack may extend vertically, passing through the plurality of memory device layers. Thus, for a single first gate stack, the plurality of memory device layers stacked in the vertical direction intersect to define a plurality of memory cells stacked in the vertical direction. The select device layer may be disposed on an uppermost memory device layer of the plurality of memory device layers.

In a NOR type memory device, each memory cell may be connected to a common source line. In view of this configuration, two adjacent memory cells may share the same source line connection in the vertical direction for wiring savings. For example, for the two adjacent memory cells, their respective source/drain regions at the near end (i.e., the end where the two memory cells are close to each other) may serve as source regions and thus be electrically connected to a source line, for example, through a common contact; the source/drain regions, each of which is at a remote end (i.e., the end of the two memory cells remote from each other), may serve as drain regions and may be respectively connected to different bit lines.

The device layer may be formed by epitaxial growth and may be a single crystal semiconductor material. A monocrystalline active region (particularly the channel region) is more easily formed than in conventional processes in which a plurality of gate stacks are formed on top of each other, followed by the formation of a vertical active region through the gate stacks.

The doping of the source/drain regions in the memory device layer may be formed by diffusion. For example, solid phase dopant source layers (also serving as spacers between memory cells) may be provided at opposite ends of each memory device layer, and dopants from the solid phase dopant source layers are driven into the memory device layers (e.g., the stack or semiconductor layers grown on the sidewalls of the stack) to form source/drain regions. Accordingly, the doping profiles of the source/drain regions and the channel region in the memory device layer can be individually adjusted, and steep high source/drain doping can be formed.

A connection portion may be provided to electrically connect the selection transistor to the corresponding first gate stack. For example, one end of the selection transistor may be connected to a corresponding word line, and the other end may be connected to a corresponding first gate stack. By selecting the on/off of the transistors, the gate control voltage on the corresponding word line may be applied to the corresponding first gate stack. The control terminal of the selection transistor may be connected to a selection line. The word lines and the select lines may be arranged to cross each other such that the respective first gate stacks are individually addressable through them.

Such a vertical type memory device can be manufactured, for example, as follows. In particular, at least one memory device layer and a select device layer may be disposed on the substrate. Solid phase dopant source layers may be disposed at upper and lower ends of each memory device layer such that each memory device layer is vertically interposed between the solid phase dopant source layers. These device layers may be provided by epitaxial growth. The location of the solid phase dopant source may be defined by the sacrificial layer during epitaxial growth, and the sacrificial layer may then be replaced with the solid phase dopant source layer. In addition, during epitaxial growth, in-situ doping may be performed to achieve the desired doping polarity and doping concentration.

Process channels may be formed that extend vertically relative to the substrate to pass through the various device layers. In the process channel, the sidewalls of the sacrificial layer may be exposed so that it may be replaced with a solid phase dopant source layer. In addition, dopants may be driven from the isolation layer into opposite ends of the device layer by annealing to form source/drain regions. The solid phase dopant source layer may be replaced with an isolation layer.

In the process channel, a first gate stack overlapping each memory device layer and a second gate stack overlapping the select device layer on the first gate stack may be formed. As described above, the first gate stack may include a memory function layer.

The present disclosure may be presented in various forms, some examples of which are described below. In the following description, reference is made to the selection of various materials. The choice of material takes into account etch selectivity in addition to its function (e.g., semiconductor material for forming active regions, dielectric material for forming electrical isolation, conductive material for forming electrodes, interconnect structures, etc.). In the following description, the required etch selectivity may or may not be indicated. It will be clear to those skilled in the art that when etching a layer of material is mentioned below, such etching may be selective if it is not mentioned that other layers are also etched or it is not shown that other layers are also etched, and that the layer of material may be etch selective with respect to other layers exposed to the same etch recipe.

Fig. 1 to 19(c) show schematic diagrams of a middle stage of a process of manufacturing a NOR-type memory device according to an embodiment of the present disclosure.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, for convenience of explanation, a bulk Si substrate such as a Si wafer is described as an example.

On the substrate 1001, a memory device such as a NOR type flash memory (flash) may be formed as described below. The memory cells (cells) in a memory device may be either n-type devices or p-type devices. Here, an n-type memory cell is taken as an example for description, and a p-type well may be formed in the substrate 1001. Thus, the following description, particularly with respect to the doping type, is directed to the formation of an n-type device. However, the present disclosure is not limited thereto.

On the substrate 1001, a sacrificial layer 1003 for defining an isolation layer may be formed by, for example, epitaxial growth₁And a memory device layer 1005 for defining an active region of the memory cell₁。

Each layer grown on the substrate 1001 may be a single crystalline semiconductor layer. These layers may have a crystal interface or a doping concentration interface with each other due to the respective growth or doping.

Sacrificial layer 1003₁Which may subsequently be replaced by an isolation layer for isolating the device from the substrate, which may have a thickness corresponding to the thickness of the isolation layer desired to be formed, for example, about 10nm-50 nm. The sacrifice layer 1003 may not be provided according to the circuit design₁. Memory device layer 1005₁The active region of the memory cell is then defined, and may be, for example, about 40nm-200nm thick.

These semiconductor layers may comprise various suitable semiconductor materials, for example, elemental semiconductor materials such as Si or Ge, compound semiconductor materials such as SiGe, and the like. Consider the following sacrificial layer 1003₁Process to replace with an isolation layer, sacrificial layer 1003₁May be opposite to the memory device layer 1005₁Has etching selectivity. For example, sacrificial layer 1003₁May include SiGe (about 15% -30% Ge by atomic percent, for example), a memory device layer 1005₁May comprise Si.

In the growth of memory device layer 1005₁When used, it may be doped in situ. For example, for an n-type device, p-type doping may be performed at a doping concentration of about 1E17-1E19cm^-3. Such doping may define doping characteristics in subsequently formed channel regions, for example, to adjust device threshold voltage (V)_t) Control short channel effects, etc. Here, the doping concentration may have a non-uniform distribution in the vertical direction to optimize device performance. For example, in a region close to the drain region (and then connected to the bit line)The degree is relatively high to reduce short channel effects and relatively low in concentration in the region proximate to the source region (which is then connected to the source line) to reduce channel resistance. This can be achieved by introducing different doses of dopants at different stages of growth.

To increase integration density, multiple memory device layers may be provided. For example, memory device layer 1005 may be formed by epitaxial growth₁On which a memory device layer 1005 is disposed₂、1005₃Between the memory device layers is a sacrificial layer 1003 defining an isolation layer₂、1003₃Spaced apart. Although only three memory device layers are shown in fig. 1, the present disclosure is not so limited. Depending on the circuit design, some memory device layers may not have isolation layers disposed between them. Memory device layer 1005₂、1005₃May have a memory device layer 1005₁The same or similar thicknesses and/or materials, and may have different thicknesses and/or materials. Here, it is assumed that the memory device layers have the same configuration for convenience of description only.

On the memory device layer, a selection device layer for defining an active region of the selection transistor may be disposed. For example, the first source/drain layers 1007 may be sequentially formed by epitaxial growth₄Channel layer 1005₄And a second source/drain layer 1009₄As the select device layer. The layers grown may be monocrystalline semiconductor layers.

First source/drain layer 1007₄The (lower) source/drain regions of the selection transistor may then be defined, for example to a thickness of about 30nm-200 nm. Channel layer 1005₄The channel region of the transistor may then be selected to have a thickness of, for example, about 30nm to 100 nm. Second source/drain layer 1009₄The (upper) source/drain regions of the selection transistor may then be defined, for example to a thickness of about 10nm-100 nm. Here, the first source/drain layer 1007₄Relatively thick, which may facilitate the fabrication of the select transistor-memory cell gate stack connection in subsequent processes.

First source/drain layer 1007 is grown₄And a second source/drain layer 1009₄When used, it may be doped in situ. For example, for an n-type device, n-type devices may be implementedDoping with a doping concentration of about 1E19-1E21cm^-3. Such doping may define the doping characteristics in the source/drain regions of the selection transistor. Similarly, in growing channel layer 1005₄When this is the case, it can also be doped in situ. For example, for an n-type device, p-type doping may be performed at a doping concentration of about 1E17-1E19cm^-3. Such doping may define doping characteristics in subsequently formed channel regions, e.g., to tune device V_tControl short channel effects, etc.

In the select device layer and the memory device layer 1005₃In between, a sacrificial layer 1003 for defining an isolation layer may also be provided₄. With respect to the sacrificial layer 1003₂To 1003₄See above for sacrificial layer 1003₁The description of (1).

As described above, the device layer is selected relative to the sacrificial layer 1003 in consideration of the following process of replacing the sacrificial layer with an isolation layer₄(and 1003)₁To 1003₃They may be of the same material such as SiGe) may have etch selectivity. For example, the first source/drain layer 1007₄Channel layer 1005₄And a second source/drain layer 1009₄May each comprise Si. Here, the layers in the select device layer comprise the same material, which may facilitate the definition of the active region of the select transistor by the same etching step in a subsequent process. However, the present disclosure is not limited thereto. Adjacent layers in the select device layer may also have etch selectivity with respect to each other.

In this embodiment, memory device layer 1005₁、1005₂、1005₃Formed by a single epitaxial layer and subsequently doped by diffusion to define source/drain regions therein, as will be described further below. However, the present disclosure is not limited thereto. For example, memory device layer 1005₁、1005₂、1005₃May be formed in the form of a selective device layer including a first source/drain layer, a channel layer, and a second source/drain layer, which are sequentially stacked. In this case, the following process may be performed in the same manner, but a diffusion doping process may not be performed (of course, it may be performed, for example, to adjust the doping characteristics of the source/drain regions).

In addition, in this embodiment, select device layer includes portion 1007 that is doped in-situ to a different doping characteristic during epitaxial growth₄、1005₄、1009₄. However, the present disclosure is not limited thereto. For example, select device layers may be as in memory device layer 1005₁、1005₂、1005₃That is formed by a single epitaxial layer and the source/drain regions may then be defined therein by diffusion doping.

On these layers formed on the substrate 1001, a hard mask layer 1015 may be provided to facilitate patterning. For example, the hard mask layer 1015 may comprise a nitride (e.g., silicon nitride) having a thickness of about 100nm to 300 nm.

In the following, on the one hand, a process channel is required which can reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, it is necessary to define a region for forming a gate. According to embodiments of the present disclosure, the two may be performed in combination. In particular, the gate region may be defined by a process channel.

For example, as shown in fig. 2(a) and 2(b), a photoresist 1017 can be formed on the hard mask layer 1015 and patterned by photolithography to have a series of openings that can define the locations of the process channels. The openings can be of various suitable shapes, such as circular, rectangular, square, polygonal, etc., and of suitable size, such as about 20nm to 500nm in diameter or side length. Here, the openings (particularly in the device region) may be arranged in an array form, for example, a two-dimensional array in the horizontal direction and the vertical direction in the paper plane in fig. 2 (a). The array may then define an array of memory cells. Although the openings are shown in fig. 2(a) as being formed on the substrate (including the device region where the memory cells will be subsequently fabricated and the contact region where the contacts will be subsequently fabricated) at a substantially uniform size, substantially uniform density, the disclosure is not limited thereto. The size and/or density of the openings may vary, for example the density of openings in the contact region may be less than the density of openings in the device region to reduce resistance in the contact region.

As shown in fig. 3, the layers on the substrate 1001 may be etched by anisotropic etching such as Reactive Ion Etching (RIE) using the photoresist 1017 thus patterned as an etching mask to form the process channel T. The RIE may be performed in a substantially vertical direction (e.g., a direction perpendicular to the substrate surface) and may be performed into the substrate 1001. Thus, a series of vertical process channels T are left on the substrate 1001. The process tunnel T in the device region also defines the gate region. After that, the photoresist 1017 may be removed.

Now, the side wall of the sacrifice layer is exposed in the process passage T. The sacrificial layer can then be replaced with an isolation layer via the exposed sidewalls. Considering the memory device layer 1005 for replacement₁To 1005₃And selecting the support function of the device layer, a support layer may be formed.

For example, as shown in fig. 4, a layer of support material may be formed on a substrate 1001 by, for example, deposition such as Chemical Vapor Deposition (CVD) or the like. The layer of support material may be formed in a substantially conformal manner. The support material layer may include, for example, SiC in consideration of etching selectivity, particularly with respect to the hard mask layer 1015 (nitride in this example) and the subsequently formed isolation layer (oxide in this example). Portions of the support material layer in the process tunnel T may be removed, for example, by forming a photoresist 1021 and performing a selective etch such as RIE with the photoresist 1021, while the support material layer in the remaining process tunnel T remains. The remaining layer of support material forms support layer 1019. Thus, the sacrificial layer can be replaced by a process channel in which the support layer 1019 is not formed on the one hand, and the memory device layer 1005 can be supported by the support layer 1019 in another process channel on the other hand₁To 1005₃And selecting a device layer. After that, the photoresist 1021 may be removed.

The arrangement of the process channels in which the support layer 1019 is formed and the process channels in which the support layer 1019 is not formed may be achieved by patterning of the photoresist 1021, and they may be substantially uniformly distributed for process uniformity and uniformity. As shown in fig. 4, the processing channels in which the support layer 1019 is formed and the processing channels in which the support layer 1019 is not formed may be alternately arranged.

Then, as shown in FIG. 5, it is possible to pass through the machining passage TThe sacrificial layer 1003 is removed by selective etching₁To 1003₄. The memory device layer 1005 may be maintained due to the presence of the support layer 1019₁To 1005₃And the select device layer does not collapse. In the voids left by the removal of the sacrificial layer, a dielectric material may be filled to form the isolation layer 1023 by a process such as deposition (preferably Atomic Layer Deposition (ALD) to better control the film thickness) and then etch back (e.g., RIE in the vertical direction)₁、1023₂、1023₃And 1023₄。

To achieve source/drain doping, spacer 1023 is formed according to an embodiment of the disclosure₁To 1023₄May include dopants (n-type dopants for n-type memory cells and p-type dopants for p-type memory cells). Thus, the isolation layer 1023₁To 1023₄Can become a solid phase dopant source layer. For example, the isolation layer 1023₁To 1023₄A phosphosilicate glass (PSG) having a phosphorous (P) content of about 0.1% -10% for n-type memory cells or a borosilicate glass (BSG) having a boron (B) content of about 0.1% -10% for P-type memory cells may be included.

In this example, the source/drain doping is achieved by a solid phase dopant source layer rather than in-situ doping, which can achieve steep high source/drain doping and can suppress cross-contamination that may result from in-situ growth during epitaxial growth.

Thereafter, the support layer 1019 may be removed by selective etching.

A gate stack of a memory cell may be formed in a process channel, particularly in a process channel of a device region. Here, to form a memory device, a memory function may be implemented by the gate stack. For example, a memory structure, such as a charge trapping material or a ferroelectric material, may be included in the gate stack.

As shown in fig. 6, a memory function layer 1025 and a gate conductor layer 1027 may be sequentially formed, for example, by deposition. The memory function layer 1025 may be formed in a substantially conformal manner, and the gate conductor layer 1027 may fill a void remaining after the memory function layer 1025 is formed in the process channel T. The formed gate conductor layer 1027 and memory function layer 1025 may be subjected to a planarization process such as chemical mechanical polishing (CMP, which may stop on the hard mask layer 1015, for example), so that the gate conductor layer 1027 and memory function layer 1025 may remain in the process channel T, forming a gate stack.

The memory function layer 1025 may be based on dielectric charge trapping, ferroelectric material effect, or band gap engineered charge storage (SONOS), among others. For example, the memory function layer 1025 may include a dielectric tunneling layer (e.g., an oxide with a thickness of about 1nm-5nm, which may be formed by oxidation or ALD) -an energy band-offset layer (e.g., a nitride with a thickness of about 2nm-10nm, which may be formed by CVD or ALD) -an isolation layer (e.g., an oxide with a thickness of about 2nm-6nm, which may be formed by oxidation, CVD, or ALD). Such a three-layer structure may result in a band structure that traps electrons or holes. Alternatively, the memory function layer 1025 may include a ferroelectric material layer, such as HfZrO with a thickness of about 2nm to 20nm₂。

The gate conductor layer 1027 can comprise, for example, a (doped, e.g., p-type doped in the case of an n-type device) polysilicon or metal gate material.

An anneal process may be performed to drive dopants from the solid phase dopant source layer into the memory device layer. For memory device layer 1005₁To 1005₃Into which the dopants in the isolation layers at the upper and lower ends thereof enter from the upper and lower ends, respectively, so that highly doped regions 1007 may be formed at the upper and lower ends thereof₁、1009₁；1007₂、1009₂；1007₃、1009₃(e.g., about 1E19-1E21cm^-3N-type doping) to define source/drain regions. Here, the diffusion depth of the dopant from the isolation layer into the memory device layers can be controlled (e.g., to about 10nm-50nm) such that the middle of each memory device layer in the vertical direction can be kept relatively low doped, e.g., substantially maintaining the doping polarity (e.g., p-type doping) and doping concentration (e.g., 1E17-1E19 cm) resulting from in-situ doping during growth^-3) And may define a channel region. Of course, the isolation layer 1023₄May also enter the select device layer, particularly the first source/drain layer 1007 therein₄In (1).

The doping concentration achieved by in-situ doping is generallyLess than 1E20cm^-3. According to embodiments of the present disclosure, source/drain doping is performed by diffusion from a solid phase dopant source layer, which may enable high doping, e.g., the highest doping concentration may be higher than 1E20cm^-3And even as high as about 7E20-3E21cm^-3. In addition, due to the diffusion characteristic, the source/drain regions may have therein a doping concentration gradient that decreases from a side close to the solid-phase dopant source layer toward a side close to the channel region in the vertical direction.

Such diffusion doping can achieve a steep doping concentration profile. For example, there may be a sharp dopant concentration spike, e.g., less than about 5nm/dec-20nm/dec, between the source/drain regions and the channel region (i.e., at least an order of magnitude drop in dopant concentration occurs in a range of less than about 5nm-20 mm). Such abrupt change in the vertical direction may be referred to as an "interface layer".

Each source/drain region 1007 is formed by diffusion from the respective isolation layers into the memory device layer with substantially the same diffusion characteristics₁、1009₁；1007₂、1009₂；1007₃、1009₃May be substantially coplanar in the lateral direction. Similarly, each channel region may be substantially coplanar in a lateral direction. In addition, as described above, the channel region may have a non-uniform distribution in the vertical direction, with a relatively high doping concentration near the source/drain region (drain region) on one side and a relatively low doping concentration near the source/drain region (source region) on the other side.

As shown in fig. 6, the gate stack (1025/1027) with the memory function layer is surrounded by the memory device layer. The gate stack cooperates with the device layer to define a memory cell, as shown by the dashed circle in fig. 6. A channel region may connect the source/drain regions on opposite sides, and the channel region may be controlled by the gate stack. One of the source/drain regions at the upper and lower ends of the single memory cell serves as a source region and can be electrically connected to a source line; the other serves as a drain region and may be electrically connected to a bit line. For every two vertically adjacent memory cells, the source/drain region at the upper end of the lower memory cell and the source/drain region at the lower end of the upper memory cell may serve as source regions so that they may share the same source line connection.

The gate stack extends in a columnar shape in the vertical direction, overlapping a plurality of (in this example, three) memory device layers, and thus can define a plurality of memory cells stacked on each other in the vertical direction. The memory cells associated with a single gate stack pillar may form a memory cell string. A plurality of such memory cell strings are arranged on a substrate in correspondence with the layout of gate stack pillars (corresponding to the layout of the process channels T described above, e.g., a two-dimensional array), thereby forming a three-dimensional (3D) array of memory cells.

At the upper end of each memory cell string (in the device region), a selection transistor may be fabricated based on a selection device layer.

According to an embodiment of the present disclosure, the selection transistor may be formed based on the process channel T. For example, the gate stack of the select transistor may be formed in the process tunnel T with its active region surrounding the gate stack, similar to a memory cell. In this way, the resulting select transistor can be self-aligned to the underlying string of memory cells.

The active regions of the select transistors of the respective memory cell strings may be electrically isolated from each other to enable independent selection of the respective memory cell strings. To this end, the select device layer may be separated into localized portions around each process tunnel T as the active region for each select transistor.

To better provide a positional reference when locally selecting the device layers and to avoid affecting the gate stack (1025/1027) of the memory cell (e.g., especially in the case where the gate conductor layer 1027 comprises polysilicon), the gate stack (1025/1027) of the memory cell may be etched back to a certain thickness by anisotropic etching, such as RIE in the vertical direction, as shown in fig. 7(a) and 7 (b). In the space left in the process channel T by the etch-back, the cap layer 1011 can be filled by a method such as deposition and then planarization (e.g., CMP, which may stop on the hard mask layer 1015). The cap layer 1011 may include, for example, SiC in consideration of etching selectivity (for example, with respect to the hard mask layer 1015 such as nitride and the isolation layer such as oxide). Here, the bottom surface of the cap layer 1011 may be higher than the bottom surface of the hard mask layer 1015, so that the cap layer 1011 may be confined in the process channel portion defined by the hard mask layer 1015 and self-aligned to the gate stack of the memory cell below. The cap layer 1011 thus formed can be used as a positioning reference of an active region of a selection transistor.

Such a mask may be formed to define the active region of the select transistor: the mask includes separate portions surrounding the respective process channels T. Here, the self-aligned mask may be formed through a sidewall (spacer) forming process.

The hard mask layer 1015 may be removed, for example, by selective etching. Thus, cap layer 1011 assumes an island shape protruding from the select device layer, self-aligned to the memory cell gate stack. Side walls 1010 may be formed on the side walls of such protruding island-like portions as a mask. For example, the spacers 1010 may be formed by depositing a layer of dielectric, such as nitride, in a substantially conformal manner (with etch selectivity with respect to the cap layer 1011 and the spacer layer), and then subjecting the deposited dielectric to an anisotropic etch, such as RIE in the vertical direction, to remove the laterally extending portions of the deposited dielectric, while leaving the vertically extending portions thereof. The thickness (dimension in the horizontal direction in the figure) of the side walls 1010 may define the size of the active region of the select transistor, for example, about 5nm-20 nm.

The select device layer may be anisotropically etched, such as by vertical RIE, using the spacers 1010 as an etch mask. The RIE may stop at the isolation layer 1023₄. Thus, the device layer (first source/drain layer 1007) is selected₄Channel layer 1005₄And a second source/drain layer 1009₄) Can be separated into localized portions respectively surrounding each process tunnel T, which define the active regions of the select transistors corresponding to each memory cell string.

For the select transistor, a source/drain region at a lower end thereof may be electrically connected to a gate stack of a corresponding memory cell string (which will be described further below), and a source/drain region at an upper end thereof may be electrically connected to a word line. Thus, the gate control voltage applied on each word line may be applied to the gate stack of the corresponding memory cell string via the corresponding select transistor.

Here, a word line electrically connected to the upper source/drain region of the selection transistor may be fabricated. For example, as shown in FIGS. 8(a) and 8(b),can be on the isolation layer 1023₄An isolation layer 1012 is formed thereon. The isolation layer 1012 may be formed by depositing, for example, an oxide, planarizing the deposited oxide such as CMP (which may stop at the cap layer 1011), and then etching back the planarized oxide. The isolation layer 1012 may shield the first source/drain layer 1007₄And a channel layer 1005₄Exposing the second source/drain layer 1009₄So that a word line subsequently formed thereon can be electrically connected to the second source/drain layer 1009₄And the first source/drain layer 1007₄And a channel layer 1005₄And (4) electrically isolating. Over the isolation layer 1012, a word line 1013 may be formed. Word line 1013 may comprise a conductive material such as a metal and may be formed by, for example, deposition followed by etching or a dual damascene process, etc. The word line 1013 may be connected to the second source/drain layer 1009₄Are in contact and thus electrically connected. According to an embodiment, the second source/drain layer 1009 may be formed before the word line 1013₄The exposed portion of (a) is subjected to silicidation to form a silicide, thereby reducing the contact resistance with the word line 1013.

As shown in the top view in fig. 8(a), the plurality of word lines 1013 may be formed in a stripe shape extending in a first direction (a horizontal direction within the paper plane in the drawing), and arranged in a second direction (a vertical direction within the paper plane in the drawing) intersecting (e.g., perpendicular to) the first direction. Here, the word line 1013 may be formed in the device region without extending into the contact region to avoid interfering with a contact subsequently formed in the contact region.

As shown in fig. 9, the voids in the present structure may be filled with a dielectric to facilitate further processing. Such filling may be performed by, for example, deposition followed by planarization. The filled dielectric may comprise the same material as the isolation layer 1012, such as an oxide, and thus they are shown as one in fig. 9 and labeled 1012'.

Device layers (particularly channel layer 1005 therein) may be selectively placed in the process tunnel T₄) The gate stack of the select transistor is formed at a corresponding height.

As shown in fig. 10, for example, by selective etching,the cap layer 1011 is removed to expose the gate stack of the memory cell. The gate stack of the memory cell may be recessed to a depth by selective etching. Here, the top surface of the gate stack of the recessed memory cell may be lower than the channel layer 1005₄So that a subsequently formed gate stack of the selection transistor can be in contact with the channel layer 1005₄Overlap the entire height of (a); and on the other hand may be higher than the top surface of the uppermost memory device layer (preferably higher than the uppermost spacer layer 1023)₄Top surface of the memory cell) to avoid unwanted electrical connections between subsequently formed select transistor-memory cell gate stack connections and the uppermost memory device layer.

In this way, the upper space of each processing passage T is released. The gate stacks of the select transistors may be formed in these spaces freed.

In consideration of electrical connection between the selection transistor and the gate stack of the memory cell, a selection transistor-memory cell gate stack connection 1014 may be formed in each process channel T as shown in fig. 11. The select transistor-memory cell gate stack connection 1014 may include a conductive material, for example, a metal such as tungsten (W). The select transistor-memory cell gate stack connection 1014 may be formed by a method such as deposition and then etch back. The select transistor-memory cell gate stack connection 1014 may be a conductive layer on the top surface of the gate stack of the memory cell in each process channel T that contacts the gate stack of the memory cell (particularly the gate conductor layer 1027 therein) on the bottom surface and the first source/drain layer 1007 on the side surface₄. A top surface of the selection transistor-memory cell gate stack connection 1014 may be lower than the first source/drain layer 1007₄Of the substrate.

As shown in fig. 12, a gate stack of the select transistor may be formed on the select transistor-memory cell gate stack connection 1014 in each process channel T. A gate dielectric layer 1016 and a gate conductor layer 1018 may be formed in sequence, as described above in connection with fig. 6. Here, the gate stack (1016/1018) of the select transistor may not have a memory function. For example, the gate dielectric layer 1016 may comprise an oxide or a high-k dielectric, and the gate conductor layer 1018 may comprise (doped) polysilicon or a metal.

The gate stack (1016/1018) of the select transistor is selected by the device layer (first source/drain layer 1007)₄Channel layer 1005₄And a second source/drain layer 1009₄) Thereby defining the select transistor. Upper source/drain regions of the selection transistors (second source/drain layer 1009)₄) Electrically connected to word line 1013, and lower source/drain regions (first source/drain layer 1007)₄) The gate stacks of the respective memory cell strings are electrically connected via select transistor-memory cell gate stack connections 1014 (1025/1027).

In this way, the fabrication of the devices (including the memory cells and the select transistors) in the device region is completed.

Various electrical contacts may then be made (in the contact areas) to achieve the desired electrical connection.

To achieve electrical connection to the memory device layers, a stepped structure may be formed in the contact regions. There are a number of ways in the art to form such a stepped structure. According to an embodiment of the present disclosure, the stepped structure may be formed, for example, as follows.

As shown in fig. 12, the gate stack (of the select transistor) is now exposed. To protect the gate stack (in the device region) during the subsequent fabrication of the step structure, another hard mask layer 1029 may be formed on the isolation layer 1012', as shown in fig. 13(a) and 13 (b). For example, hard mask layer 1029 may comprise nitride. On the hard mask layer 1029, a photoresist 1031 may be formed and patterned by photolithography to shield the device regions and expose the contact regions. The hard mask layer 1029 and the sidewall 1010 (both nitride in this example), the spacer layer 1012' and the spacer layer 1023 may be etched by a selective etch such as RIE using the photoresist 1031 as an etch mask₄(in this example, oxide), the select device layer (in this example, Si), and the gate stack (and possibly word line 1013) to expose the memory device layer. The order of etching the layers may vary depending on the process. The surface of the contact region exposed by the photoresist 1031 after etching can be made substantially flat by controlling the etching depth. Thus, a step is formed between the contact region and the device region. After that, the photoresist 1031 may be removed.

As shown in fig. 14(a) and 14(b), can be passedAnd a side wall forming process, wherein a side wall 1033 is formed at the step between the contact region and the device region. The sidewall spacers 1033 may comprise, for example, an oxide. The width (in the horizontal direction in the figure) of the sidewalls 1033 may be defined to follow the device layer 1005₃Source/drain region 1009₃The size of the landing pad (landing pad) of the contact portion(s).

With the spacers 1033 thus formed as an etching mask, the exposed device layer 1005 can be etched by a selective etching such as RIE₃Source/drain region 1009₃And gate stack to expose device layer 1005₃Of the channel region. The surface of the contact region exposed by the sidewall 1033 after etching can be made substantially flat by controlling the etching depth. For example, source/drain regions 1009 may be etched first₃And a gate conductor layer 1027 (e.g., Si and poly-Si, respectively; if the gate conductor layer 1027 includes a metal gate, they may be separately etched), the etching of which may stop at the device layer 1005₃A channel region of (1); after such etching, the top of the memory function layer 1025 may protrude from the device layer 1005₃And may be removed by RIE. Thus, in the device layer 1005 in the contact region₃Source/drain region 1009₃A further step is formed with the surface exposed by the sidewall 1033.

As shown in fig. 15(a) and 15(b), a sidewall 1034 may be further formed on the sidewall of the sidewall 1033. The width of sidewall 1034 may be defined subsequently to device layer 1005₃The size of the landing pad of the contact portion of the channel region. With the spacers 1034 thus formed as etching masks, the exposed device layer 1005 can be etched by selective etching such as RIE₃To expose the device layer 1005₃Source/drain regions 1007₃. The surface of the contact region exposed by the sidewall 1034 after etching can be made substantially flat by controlling the etching depth. Thus, in the device layer 1005 in the contact region₃A further step is formed between the channel region in (a) and the surface exposed by the sidewall 1034.

Thus, the process described above in connection with fig. 14(a) and 14(b) may be repeated to form a plurality of steps in the contact region by forming the sidewalls and etching using the sidewalls as an etch mask, as shown in fig. 16(a) and 16 (b). These steps form a stepped structure such that for each source/drain region and optionally channel region in each memory device layer that requires electrical connection, the ends protrude relatively to the overlying region to define landing pads for contacts to that region. 1035 in fig. 16(a) and 16(b) indicates the remaining portion of the sidewall spacer formed at each time after the processing. Since the spacers 1035 and spacers are both oxide, they are shown here as one piece.

Thereafter, a contact may be made.

For example, as shown in fig. 17(a) and 17(b), the interlayer dielectric layer 1037 may be formed by depositing an oxide and planarizing, such as CMP. Here, the previous spacers and spacers 1035 are both shown as being integral with the interlevel dielectric layer 1037, as both are oxides. Then, as shown in fig. 18(a), 18(b), and 18(c), contact portions 1039, 1040, and 1041 may be formed in the interlayer dielectric layer 1037. Specifically, a contact 1039 is formed in the device region, electrically connected to the gate conductor layer 1018 in the gate stack of the select transistor; a contact 1040 (contact 1040 is only partially shown in the figure due to paper limitations) is formed in the device region, electrically connected to word line 1013; contacts 1041 are formed in the contact regions and are electrically connected to the source/drain regions and optionally the channel region of each memory cell. The contact 1041 in the contact region may avoid the gate stack remaining in the contact region. These contacts may be formed by etching holes in the inter-level dielectric layer 1037 and filling them with a conductive material such as a metal.

For every two adjacent memory cells in the vertical direction, the source/drain region located in the middle, i.e., the first memory device layer 1005₁Source/drain region 1009₁And a second memory device layer 1005₂Source/drain regions 1007₂(and, a third memory device layer 1005₃Source/drain region 1009₃And lower source/drain regions (not shown) in the fourth memory device layer above (if present), may be electrically connected to source lines (whose source lines may be common) via contacts 1041; source/drain regions at upper and lower ends, i.e. first memoryPiece layer 1005₁Source/drain regions 1007₁And a second memory device layer 1005₂Source/drain region 1009₂(and, a third memory device layer 1005₃Source/drain regions 1007₃And upper source/drain regions in the fourth memory device layer above) may be electrically connected to bit lines via contacts 1041, respectively. In this way, a NOR type configuration can be obtained. Here, a contact to the channel region is also formed. Such contacts may be referred to as body contacts and may receive a body bias to adjust the device threshold voltage.

Here, two memory cells adjacent in the vertical direction are provided so that the source/drain regions located near the boundary therebetween are electrically connected to the source line. This can reduce the number of wirings. However, the present disclosure is not limited thereto. For example, vertically adjacent memory cells may be arranged in the same configuration of source-channel-drain or drain-channel-source.

In this embodiment, the dopant-containing isolation layer (which serves as the solid phase dopant source layer) remains. However, the present disclosure is not limited thereto. Other materials may be substituted for the solid phase dopant source layer after diffusion doping. For example, the solid phase dopant source layer may be replaced with other dielectric materials, particularly dielectric materials that do not intentionally contain dopants, to improve isolation performance. Alternatively, each two vertically adjacent device layers are grouped, with solid phase dopant source layers between device layers of each group (e.g., device layers 1005 as a group)₁And 1005₂1023 solid phase dopant source layer therebetween₂) May be replaced by a conductive material, such as a metal or doped semiconductor layer, to reduce interconnect resistance (to the source line); while the upper and lower sides of each set of solid phase dopant source layers (e.g., device layer 1005)₁And 1005₂1023 solid phase dopant source layer on the underside of the stack₁Device layer 1005₁And 1005₂1023 solid phase dopant source layer on the upper side of the stack₃) May be replaced by a dielectric material to achieve isolation between bit lines. In the case of replacement of the solid-phase dopant source layer, an "interface" with an abrupt doping concentration as described above can also be formed on the side of the source/drain regions facing away from the channel regionLayer ".

As shown in fig. 19(a), 19(b), and 19(c), an interlayer dielectric layer (1037' is shown integrally with the interlayer dielectric layer 1037) may be further formed on the interlayer dielectric layer 1037. In the interlayer dielectric layer, a plurality of selection lines 1039' may be formed to extend in the second direction and to be arranged in the first direction. Thus, each word line 1013 may be electrically connected to a row select transistor (in a first direction) and each select line 1039' may be electrically connected to a column select transistor (in a second direction). Selection of a memory cell string can be achieved by word line 1013 and select line 1039'. Of course, in the interlayer dielectric layer, contact plugs 1040 'and 1041' electrically connected to the contact portions 1040 and 1041 are also formed.

Fig. 20 schematically shows an equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure.

In the example of FIG. 20, three internal word lines IWL1, IWL2, IWL3 and six bit lines BL1, BL2, BL3, BL4, BL5, BL6 are schematically shown. However, the specific number of bit lines and internal word lines is not limited thereto. At the intersections of the bit lines and the internal word lines, memory cells MC are provided. Also shown in FIG. 20 are three source lines SL1, SL2, SL 3. As described above, each two adjacent memory device layers may share the same source line connection. In addition, the respective source lines may be connected to each other, so that the respective memory cells MC may be connected to a common source line. In addition, optional bulk connections to the memory cells are also shown schematically in dashed lines in FIG. 20. As described below, the bulk connection of each memory cell may be electrically connected to the source line connection of the memory cell.

The internal word lines IWL1 through IWL3 in FIG. 20 may correspond to the gate stacks of the memory cells as described above. Adjacent bit lines are isolated from each other in a vertical direction with respect to the substrate.

Each memory cell string or internal word line IWL 1-IWL 3 may have a select transistor SST on top and be connected to a respective word line WL1, WL2, WL3 via the select transistor SST. A gate electrode of the selection transistor SST may be connected to a selection line SSL.

Here, a two-dimensional array of memory cells MC is shown for convenience of illustration only. A plurality of such two-dimensional arrays may be arranged in a direction intersecting this two-dimensional array (for example, a direction perpendicular to the paper surface in the figure), thereby obtaining a three-dimensional array. Accordingly, in this direction, a plurality of selection lines SSL may be provided.

The memory device according to the embodiments of the present disclosure may be applied to various electronic devices. For example, the storage device may store various programs, applications, and data required for the operation of the electronic device. The electronic device may further comprise a processor cooperating with the memory device. For example, the processor may operate the electronic device by executing a program stored in the storage device. Such as a smart phone, a Personal Computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.