阅读说明：本技术 Nor型存储器件及其制造方法及包括存储器件的电子设备 (NOR type memory device, method of manufacturing the same, and electronic apparatus including the same ) 是由 朱慧珑 于 2021-08-02 设计创作，主要内容包括：公开了一种NOR型存储器件及包括该NOR型存储器件的电子设备。根据实施例,该NOR型存储器件可以包括NOR单元阵列和外围电路。NOR单元阵列可以包括：第一衬底；第一衬底上的存储单元的阵列,每个存储单元包括相对于第一衬底竖直延伸的第一栅堆叠以及围绕第一栅堆叠的外周的有源区；电连接到第一栅堆叠的第一结合焊盘；以及电连接到存储单元的有源区的第二结合焊盘。外围电路可以包括：第二衬底；第二衬底上的外围电路元件；以及第三结合焊盘,至少一部分第三结合焊盘电连接到外围电路元件。NOR单元阵列和外围电路被设置为使得第一结合焊盘和第二结合焊盘中的至少一些与第三结合焊盘中的至少一些彼此相对。(A NOR-type memory device and an electronic apparatus including the same are disclosed. According to an embodiment, the NOR type memory device may include a NOR cell array and peripheral circuits. The NOR cell array may include: a first substrate; an array of memory cells on a first substrate, each memory cell including a first gate stack extending vertically relative to the first substrate and an active region surrounding a periphery of the first gate stack; a first bonding pad electrically connected to the first gate stack; and a second bonding pad electrically connected to the active region of the memory cell. The peripheral circuit may include: a second substrate; peripheral circuit elements on the second substrate; and a third bonding pad, at least a portion of which is electrically connected to the peripheral circuit element. The NOR cell array and the peripheral circuit are disposed such that at least some of the first and second bonding pads and at least some of the third bonding pads are opposite to each other.)

1. A NOR-type memory device comprising:

an NOR cell array comprising:

a first substrate;

an array of memory cells on the first substrate, each memory cell including a first gate stack extending vertically relative to the first substrate and an active region surrounding a periphery of the first gate stack;

a first bonding pad electrically connected to the first gate stack; and

a second bonding pad electrically connected to the active region of the memory cell, an

A peripheral circuit comprising:

a second substrate;

peripheral circuit elements on the second substrate; and

a third bonding pad, at least a portion of which is electrically connected to the peripheral circuit element,

wherein the NOR cell array and the peripheral circuit are disposed such that at least some of the first bonding pads and the second bonding pads and at least some of the third bonding pads are opposite to each other.

2. The NOR-type memory device of claim 1 wherein,

the NOR cell array further comprising a first interlayer insulating layer on the first substrate covering the array of memory cells, wherein the first and second bonding pads are exposed at a surface of the first interlayer insulating layer facing away from the first substrate,

the peripheral circuit further includes a second interlayer insulating layer on the second substrate covering the peripheral circuit elements, wherein the third bonding pads are exposed at a surface of the second interlayer insulating layer facing away from the second substrate,

the NOR cell array and the peripheral circuit are disposed such that the surface of the first interlayer insulating layer and the surface of the second interlayer insulating layer are opposite to each other.

3. NOR-type memory device of claim 1 or 2, wherein,

the first substrate includes a device region and a contact region, the memory cell is formed in the device region,

the NOR cell array further includes: a first contact formed on the device region of the first substrate, wherein the first bond pad is electrically connected to the first gate stack through the first contact; a second contact formed on the contact region of the first substrate, wherein the second bond pad is electrically connected to the active region through the second contact.

4. NOR-type memory device of claim 1 or 2, wherein,

the at least some of the first and second bonding pads and the at least some of the third bonding pads are connected to each other by a bonding member; or

The at least some of the first and second bond pads are directly bonded with the at least some of the third bond pads.

5. The NOR-type memory device of claim 4 wherein the bonding features comprise bumps and/or solder balls.

6. A NOR-type memory device as claimed in claim 1 or 2, wherein the peripheral circuitry further comprises through-silicon vias TSVs extending through the second substrate, one or more of the third bond pads being provided on respective one or more of the TSVs.

7. The NOR-type memory device of claim 3 wherein the active region comprises:

a first source/drain layer, a first channel layer and a second source/drain layer sequentially stacked in a vertical direction,

wherein the first source/drain layer, the first channel layer, and the second source/drain layer extend from the device region to the contact region,

wherein the second contact comprises a second contact landing on the first source/drain layer and the second source/drain layer.

8. The NOR-type memory device of claim 7 wherein the second contact further comprises a second contact landing on the first channel layer.

9. The NOR-type memory device of claim 7 wherein the first source/drain layer, the first channel layer, and the second source/drain layer form a stair step structure in the contact region.

10. The NOR-type memory device of claim 7, wherein the active region further comprises:

a second channel layer and a third source/drain layer sequentially stacked on the second source/drain layer,

wherein the second channel layer and the third source/drain layer extend from the device region to the contact region,

wherein the second contact comprises a second contact landing on the third source/drain layer.

11. The NOR-type memory device of claim 10, wherein the second contact further comprises a second contact landing on the second channel layer.

12. The NOR-type memory device of claim 10, wherein the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer form a stepped structure in the contact region.

13. The NOR-type memory device of claim 3 wherein the active region comprises:

a semiconductor nanosheet extending along a periphery of the first gate stack, including a first source/drain region, a first channel region, and a second source/drain region arranged sequentially in a vertical direction,

the NOR-type memory device further includes:

a first interconnect layer surrounding a periphery of the first source/drain region of the semiconductor nanoplate and extending from the device region to the contact region; and

a second interconnect layer surrounding a periphery of the first source/drain regions of the semiconductor nanoplatelets and extending from the device region to the contact region,

wherein the second contact comprises a second contact landing on the first interconnect layer and the second interconnect layer.

14. The NOR-type memory device of claim 13, wherein the first interconnect layer and the second interconnect layer form a stair step structure in the contact region.

15. The NOR-type memory device of claim 13, wherein the semiconductor nanoplatelets further comprise:

a second channel region and a third source/drain region sequentially arranged in a vertical direction on the second source/drain region,

the NOR-type memory device further includes:

a third interconnect layer surrounding a periphery of a third source/drain region of the semiconductor nanoplate and extending from the device region to the contact region,

wherein the second contact comprises a second contact landing on the third interconnect layer.

16. The NOR-type memory device of claim 13, wherein the first interconnect layer, the second interconnect layer, and the third interconnect layer form a stair step structure in the contact region.

17. The NOR-type memory device of claim 3, wherein the first gate stacks are arranged in an array in a first direction and a second direction intersecting each other in a plan view,

the NOR cell array further includes:

select transistors corresponding to the first gate stacks over the array of memory cells, each of the select transistors including a second gate stack extending vertically over a respective first gate stack and an active region surrounding a periphery of the second gate stack, the active region including a first source/drain region, a channel region, and a second source/drain region disposed sequentially in a vertical direction;

a connection electrically connecting the first source/drain region to the first gate stack;

a plurality of word lines extending in the first direction and arranged in the second direction, the word lines being electrically connected to the second/source drain regions of the selection transistors in the corresponding row, respectively; and

a plurality of selection lines extending in the second direction and arranged in the first direction, the selection lines being electrically connected to the second gate stacks of the selection transistors of the corresponding columns, respectively,

wherein the first bond pad comprises or is at least partially electrically connected to the select line.

18. The NOR-type memory device of claim 17, further comprising:

a fourth bond pad electrically connected to the word line,

wherein at least some of the fourth bond pads and at least some of the third bond pads are opposite one another.

19. The NOR-type memory device of claim 17, wherein the first gate stack, the connection, and the second gate stack are self-aligned in a vertical direction.

20. A NOR-type memory device as claimed in claim 1 or 2, wherein the active region comprises a single crystal semiconductor material.

21. An electronic device comprising a NOR-type memory device as claimed in any of claims 1 to 20.

22. The electronic device of claim 21, wherein the electronic device comprises a smartphone, a personal computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to NOR-type memory devices, methods of manufacturing the same, and electronic devices including such memory devices.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the horizontal type device is not easily further downsized. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are more easily scaled down relative to horizontal devices.

For vertical devices, integration density can be increased by stacking one on top of the other. However, this may result in poor performance. Since polysilicon is generally used as the channel material for the convenience of stacking a plurality of devices, the resistance becomes large compared to that of a channel material of single crystal silicon. In addition, it is also desirable to enable high bandwidth connections between memory cells and peripheral circuitry.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a NOR-type memory device having improved performance, a method of manufacturing the same, and an electronic apparatus including the same.

According to an aspect of the present disclosure, there is provided a NOR-type memory device including: NOR cell arrays and peripheral circuits. The NOR cell array may include: a first substrate; an array of memory cells on a first substrate, each memory cell including a first gate stack extending vertically relative to the first substrate and an active region surrounding a periphery of the first gate stack; a first bonding pad electrically connected to the first gate stack; and a second bonding pad electrically connected to the active region of the memory cell. The peripheral circuit may include: a second substrate; peripheral circuit elements on the second substrate; and a third bonding pad, at least a portion of which is electrically connected to the peripheral circuit element. The NOR cell array and the peripheral circuit are disposed such that at least some of the first and second bonding pads and at least some of the third bonding pads are opposite to each other. .

According to another aspect of the present disclosure, there is provided an electronic device including the NOR-type memory device described above.

According to an embodiment of the present disclosure, a memory cell array may be combined (bonding) with peripheral circuits, thereby realizing a high bandwidth connection therebetween. In addition, a three-dimensional (3D) NOR type memory device can be built using a stack of single crystal materials as a building block. Therefore, when a plurality of memory cells are stacked on one another, an increase in resistance can be suppressed.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1(a) to 1(d) are schematic diagrams showing a NOR cell array according to an embodiment of the present disclosure, in which fig. 1(a) is a top view showing positions of an AA 'line and a BB' line, fig. 1(b) is a cross-sectional view along the AA 'line, fig. 1(c) is a cross-sectional view along the BB' line, and fig. 1(d) is an equivalent circuit diagram;

fig. 2(a) and 2(b) are schematic views showing a NOR-type memory device according to an embodiment of the present disclosure, wherein fig. 2(a) is a sectional view along line AA ', and fig. 2(b) is a sectional view along line BB';

fig. 3 is a schematic diagram illustrating a NOR-type memory device according to another embodiment of the present disclosure, which is a cross-sectional view taken along line AA';

fig. 4(a) and 4(b) are schematic views illustrating a NOR-type memory device according to another embodiment of the present disclosure, wherein fig. 4(a) is a sectional view taken along line AA ', and fig. 4(b) is a sectional view taken along line BB';

fig. 5(a) and 5(b) are schematic views illustrating a NOR-type memory device according to another embodiment of the present disclosure, wherein fig. 5(a) is a sectional view taken along line AA ', and fig. 5(b) is a sectional view taken along line BB';

fig. 6 to 24(b) are schematic views showing a middle stage of a process of manufacturing a NOR-type memory device according to another embodiment of the present disclosure, in which fig. 7(a), 12(a), 13(a), 18(a), 22(a), 23(a) are top views, fig. 7(a) shows positions of AA 'and BB' lines, fig. 6, 7(b), 8 to 11, 12(b), 13(b), 14 to 17, 18(b), 19(a), 20(a), 21(a), 22(b), 23(b), 24(a) are cross-sectional views along the AA 'line, and fig. 19(b), 20(b), 21(b), 22(c), 23(c), 24(b) are cross-sectional views along the BB' line;

fig. 25 schematically shows an equivalent circuit diagram of a NOR cell array according to another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals may denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The present disclosure may be presented in various forms, some examples of which are described below. In the following description, reference is made to the selection of various materials. The choice of material takes into account etch selectivity in addition to its function (e.g., semiconductor material for forming active regions, dielectric material for forming electrical isolation, conductive material for forming electrodes, interconnect structures, etc.). In the following description, the required etch selectivity may or may not be indicated. It will be clear to those skilled in the art that when etching a layer of material is mentioned below, such etching may be selective if it is not mentioned that other layers are also etched or it is not shown that other layers are also etched, and that the layer of material may be etch selective with respect to other layers exposed to the same etch recipe.

Fig. 1(a) to 1(d) are schematic diagrams illustrating a NOR cell array according to an embodiment of the present disclosure.

As shown in fig. 1(a) to 1(c), a NOR cell array may be formed on a substrate 1001. On the substrate 1001, device layers L1, L2 are stacked. For example, the device layer L1 may include a first source/drain layer 1005 defining a source/drain region₁A first channel layer 1007 for defining a channel region₁A second source/drain layer 1009 for defining a source/drain region₁A second channel layer 1011 for defining a channel region₁And a third source/drain layer 1013 defining source/drain regions₁. The device layer L2 may similarly include a first source/drain layer 1005₂A first channel layer 1007₂Second source/drain layer 1009₂A second channel layer 1011₂And a third source/drain layer 1013₂. Although only two device layers are shown in the figures, the present disclosure is not so limited and fewer (e.g., one) or more (e.g., three or more) device layers may be included. The device layers may be separated from the substrate and from the device layers by isolation layers. Here, the isolation layer is shown as one body with the interlayer insulating layer 1037.

The gate stack including the memory function layer 1025 and the gate conductor layer 1027 may extend vertically to pass through the device layers L1, L2 (particularly in the device region). The memory function layer 1025 may be based on dielectric charge trapping, ferroelectric material effect, or band gap engineered charge storage (SONOS), among others.

As shown in fig. 1(b), the gate stack (1025/1027) with the memory functional layer is surrounded by an active region. The gate stack cooperates with the active region (stack of source/drain layers, channel layer and source/drain layers) to define a memory cell, as shown by the dashed circle in fig. 1 (b). A channel region formed in the channel layer may connect source/drain regions formed in the source/drain layers at opposite ends, and the channel region may be controlled by the gate stack.

The gate stack extends in a columnar shape in the vertical direction, overlapping the plurality of device layers, and thus may define a plurality of memory cells stacked on each other in the vertical direction. The memory cells associated with a single gate stack pillar may form a memory cell string. A plurality of such memory cell strings are arranged on a substrate corresponding to the layout of the gate stack pillars, thereby forming a three-dimensional (3D) array of memory cells.

In this embodiment, a single gate stack pillar may define two memory cells in a single device layer, as shown by the two dashed circles in device layer L1 in fig. 1 (b). In a NOR type memory device, the two memory cells may share the same source/drain layer (the second source/drain layer 1009 in the middle)₁Or 1009₂) And is electrically connected to the source line. In addition, the two memory cells pass through the source/drain layers (first source/drain layer 1005) on the upper and lower sides, respectively₁Or 1005₂And a third source/drain layer 1013₁Or 1013, the₂) Is electrically connected to a bit line.

A stepped structure may be formed in the contact region such that for each of the device layers that require electrical connection, such as the source/drain layers described above and optionally the channel layer, the ends protrude relatively to the overlying layer to define a landing pad to the contact of that layer.

The interlayer insulating layer 1037 covers the array of memory cells, and contacts 1039 and 1041 may be formed in the interlayer insulating layer 1037. Specifically, a contact 1039 may be formed in the device region, electrically connected to the gate conductor layer 1027 in the gate stack; a contact portion 1041 may be formed in the contact region, electrically connected to each of the source/drain layer and the channel layer. The contact 1041 in the contact region may avoid the gate stack remaining in the contact region.

Fig. 1(d) schematically shows an equivalent circuit diagram of a NOR cell array according to an embodiment of the present disclosure.

In the example of fig. 1(d), three word lines WL1, WL2, WL3 and eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8 are schematically shown. However, the specific number of bit lines and word lines is not limited thereto. At the intersection of the bit line and the word line, a memory cell MC is provided. Also shown in fig. 1(d) are four source lines SL1, SL2, SL3, SL 4. As described above, every two adjacent layers of memory cells in the vertical direction may share the same source line connection. In addition, the respective source lines may be connected to each other, so that the respective memory cells MC may be connected to a common source line. In addition, an optional bulk connection to each memory cell is also schematically shown in FIG. 1(d) in dashed lines. The body connection of each memory cell may be electrically connected to the source line connection of that memory cell.

Here, a two-dimensional array of memory cells MC is shown for convenience of illustration only. A plurality of such two-dimensional arrays may be arranged in a direction intersecting this two-dimensional array (for example, a direction perpendicular to the paper surface in the figure), thereby obtaining a three-dimensional array.

The extending direction of the word lines WL1 to WL3 in fig. 1(d) may correspond to the extending direction of the gate stack, i.e., the vertical direction with respect to the substrate in this embodiment. In this direction, adjacent bit lines are isolated from each other.

For further details, reference may be made to chinese patent application 202110252927.4, which describes in detail the NOR cell array shown in fig. 1(a) to 1(d) and the method of manufacturing the same.

Fig. 2(a) and 2(b) are schematic diagrams illustrating a NOR type memory device according to an embodiment of the present disclosure.

As shown in fig. 2(a) and 2(b), peripheral circuits are flip-chip mounted on the NOR cell array shown in fig. 1(a) to 1 (d). The peripheral circuit may include a peripheral circuit element TR such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or the like formed on the substrate SUB. The peripheral circuit elements TR may form various functional circuits by interconnect structures (e.g., including vias and interconnect lines) formed in the interlayer insulating layer ILD covering them.

The interconnect structure may also include Through Silicon Vias (TSVs) through the substrate SUB. TSVs may be exposed from a surface of the substrate SUB facing away from the NOR cell array so as to be electrically connected with other components. TSVs may be electrically connected to peripheral circuit elements TR, such as TSVs 1; it is also possible to electrically connect not to the peripheral circuit elements TR but to use them for other purposes such as achieving electrical connection between the NOR cell array (e.g., the contacts 1041) and other components, such as the TSVs 2. TSV2 may extend through substrate SUB and inter-layer insulating layer ILD.

The NOR cell array may include bond PADs PAD1 for electrical connection with peripheral circuitry and optionally other components. The bonding PAD1 may be disposed on a surface of the interlayer insulating layer 1037 opposite to the substrate 1001 (may be referred to as "top surface"). The bond PAD1 may be electrically connected to the contacts 1039, 1041. For example, the bond PAD1 may be disposed on the contacts 1039, 1041, they may be in direct contact, or there may be other interconnection features between them. The bonding PAD1 may be at least partially embedded in the interlayer insulating layer 1037 or formed over the top surface of the interlayer insulating layer 1037, but its connection surface (e.g., the surface facing the peripheral circuit) may be exposed at the top surface of the interlayer insulating layer 1038.

Similarly, the peripheral circuitry may include bond PAD2 for electrical connection with the NOR cell array and optionally other components. The bond PAD2 may be disposed on a surface of the interlayer insulating layer ILD opposite the substrate SUB (which may be referred to as a "top surface"). The bond PADs PAD2 may be electrically connected to respective components of the interconnect structure (e.g., contacts and/or TSVs) of the peripheral circuitry. For example, the bond PADs PAD2 may be disposed on respective portions of the interconnect structure, they may be in direct contact, or other interconnect features may also be present therebetween. The bond PAD2 may be at least partially embedded in the interlayer insulating layer ILD or formed above the top surface of the interlayer insulating layer ILD, but its connection surface (e.g., the surface facing the NOR cell array) may be exposed at the top surface of the interlayer insulating layer ILD.

The bonding PADs PAD1 and PAD2 may be disposed corresponding to each other so that they may face each other when a peripheral circuit is flip-chip mounted on the NOR cell array and thus may be connected to each other through the bonding part BOND. The bonding means BOND may comprise at least one of bumps, solder balls, etc., for example.

In this example, the NOR cell array and the peripheral circuits are shown to have the same size in the lateral direction, and they are perfectly aligned in the vertical direction. However, the present disclosure is not limited thereto. For example, the NOR cell array and the peripheral circuitry may be of different sizes laterally, or they may be offset from each other, such that, for example, one or more bond PADs PAD1 may not be covered by the peripheral circuitry (or one or more bond PADs PAD2 may not be covered by the NOR cell array), and thus may be electrically connected to other components by other bonding means (e.g., wire bonding).

In the example shown in fig. 2(a) and 2(b), the bonding PADs PAD1 and PAD2 are bonded to each other by a bonding part BOND. However, the present disclosure is not limited thereto. For example, as shown in fig. 3, the bond PADs PAD1 and PAD2 may be directly bonded to each other.

Fig. 4(a) and 4(b) are schematic views illustrating a NOR type memory device according to another embodiment of the present disclosure.

According to this embodiment, in the NOR cell array, device layers L1, L2, L3, L4 may be stacked on the substrate 2001. For example, device layer L1 may include first source/drain region 2005₁Channel region 2007₁And a second source/drain region 2009₁. Device layer L1 may be a single semiconductor layer in which first source/drain region 2005 is defined by a doping profile₁Channel region 2007₁And a second source/drain region 2009₁. Alternatively, similar to the above-described embodiments, the device layer L1 may include a stack of source/drain layer-channel layer-source/drain layer. Similarly, device layer L2 may include first source/drain region 2005₂Channel region 2007₂And a second source/drain region 2009₂(ii) a Device layer L3 may include first source/drain region 2005₃Channel region 2007₃And a second source/drain region 2009₃(ii) a Device layer L4 may include first source/drain region 2005₄Channel region 2007₄And a second source/drain region 2009₄. The gate stack may extend vertically to pass through the device layers L1, L2, L3, L4.

As shown in fig. 4(a), the gate stack (with the memory function layer) is surrounded by the device layer. The gate stack cooperates with the device layer to define a memory cell, as shown by the dashed circle in fig. 4 (a). A channel region may connect the source/drain regions on opposite sides, and the channel region may be controlled by the gate stack. One of the source/drain regions at the upper and lower ends of the single memory cell serves as a source region and can be electrically connected to a source line; the other serves as a drain region and may be electrically connected to a bit line. For every two vertically adjacent memory cells, the source/drain region at the upper end of the lower memory cell and the source/drain region at the lower end of the upper memory cell may serve as source regions so that they may share the same source line connection (see dashed circles in fig. 4 (b)).

For further details of the NOR cell array, see chinese patent application 202110252926. x.

Also, on the NOR cell array, peripheral circuits may be flip-chip mounted. As for the peripheral circuit, the description above in conjunction with fig. 2(a) and 2(b) can be referred to. The bonding PAD1 of the NOR cell array may be bonded with the bonding PAD2 of the peripheral circuit. Although the bonding PADs PAD1 and PAD2 are shown in fig. 4(a) and 4(b) as being bonded by the bonding part BOND, they may be directly bonded to each other as described above.

Fig. 5(a) and 5(b) are schematic diagrams illustrating a NOR type memory device according to another embodiment of the present disclosure.

According to this embodiment, in the NOR cell array, the gate stack extends vertically on the substrate 3001 to pass through the device layers L1, L2. The device layers L1 and L2 each include a semiconductor layer SEMI extending along the outer periphery of each gate stack. The semiconducting layer SEMI may be in the form of a ring nanoplate. In the semiconductor layer SEMI, source/drain regions-channel regions-source/drain regions may be defined in the vertical direction by, for example, a doping profile. In addition, in the device layer L1, a first interconnection layer 3005 surrounding the outer periphery of each semiconductor layer SEMI in the device layer L1 may be provided₁Second interconnect layer 3009₁And a third interconnect layer 3013₁. First interconnect layer 3005₁Second interconnect layer 3009₁And a third interconnect layer 3013₁May correspond to the height of the corresponding source/drain region in the semiconductor layer SEMIAnd (4) degree. Similarly, in the device layer L2, a first interconnect layer 3005 surrounding the outer periphery of each semiconductor layer SEMI in the device layer L2 may be provided₂Second interconnect layer 3009₂And a third interconnect layer 3013₂。

As shown in fig. 5(a), the gate stack (with the memory function layer) is surrounded by the semiconductor layer SEMI. The gate stack cooperates with the semiconductor layer SEMI to define a memory cell, as shown by the dashed circle in fig. 5 (a).

For further details regarding the NOR cell array, see chinese patent application 20211025287.2.

Also, on the NOR cell array, peripheral circuits may be flip-chip mounted. As for the peripheral circuit, the description above in conjunction with fig. 2(a) and 2(b) can be referred to. The bonding PAD1 of the NOR cell array may be bonded with the bonding PAD2 of the peripheral circuit. Although the bonding PADs PAD1 and PAD2 are shown in fig. 5(a) and 5(b) as being bonded by the bonding part BOND, they may be directly bonded to each other as described above.

Fig. 6 to 24(b) are schematic diagrams illustrating a middle stage of a process of manufacturing a NOR-type memory device according to another embodiment of the present disclosure.

As shown in fig. 6, a substrate 4001 is provided. The substrate 4001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, for convenience of explanation, a bulk Si substrate such as a Si wafer is described as an example.

On the substrate 4001, a memory cell array, for example, a NOR type flash memory (flash) cell array, can be formed as described below. The memory cell may be an n-type device or a p-type device. Here, an n-type memory cell is taken as an example for description, and a p-type well may be formed in the substrate 4001. Thus, the following description, particularly with respect to the doping type, is directed to the formation of an n-type device. However, the present disclosure is not limited thereto.

On the substrate 4001, a sacrificial layer 4003 for defining an isolation layer may be formed by, for example, epitaxial growth₁And storage for defining active area of memory cellDevice layer 4005₁。

Each layer grown over the substrate 4001 may be a single crystalline semiconductor layer. These layers may have a crystal interface or a doping concentration interface with each other due to the respective growth or doping.

Sacrificial layer 4003₁Which may subsequently be replaced by an isolation layer for isolating the device from the substrate, which may have a thickness corresponding to the thickness of the isolation layer desired to be formed, for example, about 10nm-50 nm. The sacrificial layer 4003 may not be provided depending on the circuit design₁. Memory device layer 4005₁The active region of the memory cell is then defined, and may be, for example, about 40nm-200nm thick.

These semiconductor layers may comprise various suitable semiconductor materials, for example, elemental semiconductor materials such as Si or Ge, compound semiconductor materials such as SiGe, and the like. Consider the following sacrificial layer 4003₁Replacement with a spacer Process, sacrificial layer 4003₁Can be opposite to the memory device layer 4005₁Has etching selectivity. For example, sacrificial layer 4003₁Can include SiGe (about 15% -30% Ge by atomic percent, for example), a memory device layer 4005₁May comprise Si.

On the growth of the memory device layer 4005₁When used, it may be doped in situ. For example, for an n-type device, p-type doping may be performed at a doping concentration of about 1E17-1E19cm^-3. Such doping may define doping characteristics in subsequently formed channel regions, for example, to adjust device threshold voltage (V)_t) Control short channel effects, etc. Here, the doping concentration may have a non-uniform distribution in the vertical direction to optimize device performance. For example, the concentration is relatively high in the region near the drain region (which is then connected to the bit line) to reduce short channel effects, and relatively low in the region near the source region (which is then connected to the source line) to reduce channel resistance. This can be achieved by introducing different doses of dopants at different stages of growth.

To increase integration density, multiple memory device layers may be provided. For example, memory device layer 4005 may be formed by epitaxial growth₁On which a memory device layer is arranged4005₂、4005₃Between the memory device layers through a sacrificial layer 4003 for defining an isolation layer₂、4003₃Spaced apart. Although only three memory device layers are shown in fig. 6, the present disclosure is not so limited. Depending on the circuit design, some memory device layers may not have isolation layers disposed between them. Memory device layer 4005₂、4005₃Can have a contact layer 4005 with a memory device₁The same or similar thicknesses and/or materials, and may have different thicknesses and/or materials. Here, it is assumed that the memory device layers have the same configuration for convenience of description only.

On the memory device layer, a selection device layer for defining an active region of the selection transistor may be disposed. For example, the first source/drain layer 4007 may be formed sequentially by epitaxial growth₄Channel layer 4005₄And a second source/drain layer 4009₄As the select device layer. The layers grown may be monocrystalline semiconductor layers.

First source/drain layer 4007₄The (lower) source/drain regions of the selection transistor may then be defined, for example to a thickness of about 30nm-200 nm. Channel layer 4005₄The channel region of the transistor may then be selected to have a thickness of, for example, about 30nm to 100 nm. Second source/drain layer 4009₄The (upper) source/drain regions of the selection transistor may then be defined, for example to a thickness of about 10nm-100 nm. Here, the first source/drain layer 4007₄Relatively thick, which may facilitate the fabrication of the select transistor-memory cell gate stack connection in subsequent processes.

First source/drain layer 4007 is grown₄And a second source/drain layer 4009₄When used, it may be doped in situ. For example, for an n-type device, n-type doping may be performed at a doping concentration of about 1E19-1E21cm^-3. Such doping may define the doping characteristics in the source/drain regions of the selection transistor. Similarly, the channel layer 4005 is grown₄When this is the case, it can also be doped in situ. For example, for an n-type device, p-type doping may be performed at a doping concentration of about 1E17-1E19cm^-3. Such doping may define doping characteristics in subsequently formed channel regions, e.g., to tune device V_tControl short channel effects, etc.

In the selection device layer and the memory device layer 4005₃A sacrificial layer 4003 for defining an isolation layer may be provided₄. With respect to the sacrificial layer 4003₂To 4003₄See above for sacrificial layer 4003₁The description of (1).

As described above, the device layer is selected relative to the sacrificial layer 4003 in view of the following process of replacing the sacrificial layer with an isolation layer₄(and 4003₁To 4003₃They may be of the same material such as SiGe) may have etch selectivity. For example, the first source/drain layer 4007₄Channel layer 4005₄And a second source/drain layer 4009₄May each comprise Si. Here, the layers in the select device layer comprise the same material, which may facilitate the definition of the active region of the select transistor by the same etching step in a subsequent process. However, the present disclosure is not limited thereto. Adjacent layers in the select device layer may also have etch selectivity with respect to each other.

In this embodiment, memory device layer 4005₁、4005₂、4005₃Formed by a single epitaxial layer and subsequently doped by diffusion to define source/drain regions therein, as will be described further below. However, the present disclosure is not limited thereto. For example, memory device layer 4005₁、4005₂、4005₃May be formed in the form of a selective device layer including a first source/drain layer, a channel layer, and a second source/drain layer, which are sequentially stacked. In this case, the following process may be performed in the same manner, but a diffusion doping process may not be performed (of course, it may be performed, for example, to adjust the doping characteristics of the source/drain regions).

Additionally, in this embodiment, the select device layer includes a portion 4007 that is in-situ doped with a different doping profile during epitaxial growth₄、4005₄、4009₄. However, the present disclosure is not limited thereto. For example, the select device layer may be as the memory device layer 4005₁、4005₂、4005₃That is formed by a single epitaxial layer and then the source/drain can be defined therein by diffusion dopingAnd (4) a zone.

On these layers formed over the substrate 4001, a hard mask layer 4015 may be provided for convenience of patterning. For example, the hard mask layer 4015 may comprise a nitride (e.g., silicon nitride) having a thickness of about 100nm to 300 nm.

In the following, on the one hand, a process channel is required which can reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, it is necessary to define a region for forming a gate. According to embodiments of the present disclosure, the two may be performed in combination. In particular, the gate region may be defined by a process channel.

For example, as shown in fig. 7(a) and 7(b), a photoresist 4017 can be formed on the hard mask layer 4015 and photolithographically patterned to have a series of openings that can define the locations of the process channels. The openings can be of various suitable shapes, such as circular, rectangular, square, polygonal, etc., and of suitable size, such as about 20nm to 500nm in diameter or side length. Here, the openings (particularly in the device region) may be arranged in an array form, for example, a two-dimensional array in the horizontal direction and the vertical direction in the paper plane in fig. 7 (a). The array may then define an array of memory cells. Although the openings are shown in fig. 7(a) as being formed on the substrate (including the device region where the memory cells will be subsequently fabricated and the contact region where the contacts will be subsequently fabricated) at a substantially uniform size, substantially uniform density, the present disclosure is not limited thereto. The size and/or density of the openings may vary, for example the density of openings in the contact region may be less than the density of openings in the device region to reduce resistance in the contact region.

As shown in fig. 8, each layer on the substrate 4001 can be etched by anisotropic etching such as Reactive Ion Etching (RIE) using the photoresist 4017 thus patterned as an etching mask to form the process channel T. The RIE can be performed in a substantially vertical direction (e.g., a direction perpendicular to the substrate surface) and can be performed into the substrate 4001. Thus, a series of vertical process channels T are left on the substrate 4001. The process tunnel T in the device region also defines the gate region. Thereafter, the photoresist 4017 may be removed.

Currently, the side of the sacrificial layerThe wall is exposed in the machining passage T. The sacrificial layer can then be replaced with an isolation layer via the exposed sidewalls. Consider the memory device layer 4005 when replacing₁To 4005₃And selecting the support function of the device layer, a support layer may be formed.

For example, as shown in fig. 9, a support material layer may be formed on the substrate 4001 by, for example, deposition such as Chemical Vapor Deposition (CVD) or the like. The layer of support material may be formed in a substantially conformal manner. The support material layer may include, for example, SiC in consideration of etching selectivity, particularly with respect to the hard mask layer 4015 (nitride in this example) and the subsequently formed isolation layer (oxide in this example). Portions of the layer of support material in process channel T may be removed, for example, by forming photoresist 4021 and performing a selective etch, such as RIE, in conjunction with photoresist 4021, while the layer of support material in the remaining process channel T remains. The remaining layer of support material forms support layer 4019. Thus, the sacrificial layer can be replaced by a process channel in which the support layer 4019 is not formed on the one hand, and the memory device layer 4005 can be supported by the support layer 4019 in another process channel on the other hand₁To 4005₃And selecting a device layer. After that, the photoresist 4021 may be removed.

The arrangement of the process channels in which the support layer 4019 is formed and the process channels in which the support layer 4019 is not formed can be achieved by patterning the photoresist 4021, and they can be distributed substantially uniformly for process uniformity and uniformity. As shown in fig. 9, the process channels in which the support layer 4019 is formed and the process channels in which the support layer 4019 is not formed may be alternately arranged.

Then, as shown in fig. 10, the sacrificial layer 4003 may be removed by selective etching through the process channel T₁To 4003₄. The memory device layer 4005 can be held due to the presence of the supporting layer 4019₁To 4005₃And the select device layer does not collapse. In the voids left by the removal of the sacrificial layer, the dielectric material may be filled by a process such as deposition (preferably Atomic Layer Deposition (ALD) to better control the film thickness) followed by etch back (e.g., vertical RIE)To form a barrier layer 4023₁、4023₂、4023₃And 4023₄。

In accordance with embodiments of the present disclosure, to achieve source/drain doping, the isolation layer 4023₁To 4023₄May include dopants (n-type dopants for n-type memory cells and p-type dopants for p-type memory cells). Thus, the separation layer 4023₁To 4023₄Can become a solid phase dopant source layer. For example, spacer layer 4023₁To 4023₄A phosphosilicate glass (PSG) having a phosphorous (P) content of about 0.1% -10% for n-type memory cells or a borosilicate glass (BSG) having a boron (B) content of about 0.1% -10% for P-type memory cells may be included.

In this example, the source/drain doping is achieved by a solid phase dopant source layer rather than in-situ doping, which can achieve steep high source/drain doping and can suppress cross-contamination that may result from in-situ growth during epitaxial growth.

Thereafter, the support layer 4019 may be removed by selective etching.

A gate stack of a memory cell may be formed in a process channel, particularly in a process channel of a device region. Here, to form a memory device, a memory function may be implemented by the gate stack. For example, a memory structure, such as a charge trapping material or a ferroelectric material, may be included in the gate stack.

As shown in fig. 11, a memory functional layer 4025 and a gate conductor layer 4027 may be formed in this order, for example, by deposition. The memory functional layer 4025 may be formed in a substantially conformal manner, and the gate conductor layer 4027 may fill a void remaining after the memory functional layer 4025 is formed in the processing passage T. The formed gate conductor layer 4027 and the memory function layer 4025 may be subjected to a planarization process such as a chemical mechanical polishing (CMP, which may stop on the hard mask layer 4015, for example), so that the gate conductor layer 4027 and the memory function layer 4025 may remain in the process channel T, forming a gate stack.

The memory function layer 4025 may be based on dielectric charge trapping, ferroelectric material effects, band gap engineered charge storage (SONOS), or the like. For example, the storage function layer 4025 may include a dielectric tunneling layer (e.g., having a thickness of about 1nm to 5 n)An oxide of m, which may be formed by oxidation or ALD) -an energy band-offset layer (e.g., a nitride having a thickness of about 2nm-10nm, which may be formed by CVD or ALD) -a spacer layer (e.g., an oxide having a thickness of about 2nm-6nm, which may be formed by oxidation, CVD or ALD). Such a three-layer structure may result in a band structure that traps electrons or holes. Alternatively, the memory functional layer 4025 may include a ferroelectric material layer, such as HfZrO having a thickness of about 2nm to 20nm₂。

Gate conductor layer 4027 may comprise, for example, a (doped, e.g., p-type doped in the case of an n-type device) polysilicon or metal gate material.

An anneal process may be performed to drive dopants from the solid phase dopant source layer into the memory device layer. For memory device layer 4005₁To 4005₃Into which the dopants in the spacers at the upper and lower ends thereof enter from the upper and lower ends, respectively, so that highly doped regions 4007 can be formed at the upper and lower ends thereof₁、4009₁；4007₂、4009₂；4007₃、4009₃(e.g., about 1E19-1E21cm^-3N-type doping) to define source/drain regions. Here, the diffusion depth of the dopant from the isolation layer into the memory device layers can be controlled (e.g., to about 10nm-50nm) such that the middle of each memory device layer in the vertical direction can be kept relatively low doped, e.g., substantially maintaining the doping polarity (e.g., p-type doping) and doping concentration (e.g., 1E17-1E19 cm) resulting from in-situ doping during growth^-3) And may define a channel region. Of course, the spacer layer 4023₄Can also enter the select device layer, particularly the first source/drain layer 4007 therein₄In (1).

The doping concentration achieved by in-situ doping is generally lower than 1E20cm^-3. According to embodiments of the present disclosure, source/drain doping is performed by diffusion from a solid phase dopant source layer, which may enable high doping, e.g., the highest doping concentration may be higher than 1E20cm^-3And even as high as about 7E20-3E21cm^-3. In addition, due to diffusion characteristics, the source/drain regions may have a dopant concentration gradient therein which decreases in the vertical direction from the side near the solid-phase dopant source layer toward the side near the channel region。

Such diffusion doping can achieve a steep doping concentration profile. For example, there may be a sharp dopant concentration spike, e.g., less than about 5nm/dec-20nm/dec, between the source/drain regions and the channel region (i.e., at least an order of magnitude drop in dopant concentration occurs in a range of less than about 5nm-20 mm). Such abrupt change in the vertical direction may be referred to as an "interface layer".

Each source/drain region 4007 diffuses from the isolation layers into the memory device layer with substantially the same diffusion characteristics₁、4009₁；4007₂、4009₂；4007₃、4009₃May be substantially coplanar in the lateral direction. Similarly, each channel region may be substantially coplanar in a lateral direction. In addition, as described above, the channel region may have a non-uniform distribution in the vertical direction, with a relatively high doping concentration near the source/drain region (drain region) on one side and a relatively low doping concentration near the source/drain region (source region) on the other side.

As shown in fig. 11, the gate stack (4025/4027) with the memory function layer is surrounded by the memory device layer. The gate stack cooperates with the device layer to define a memory cell, as shown by the dashed circle in fig. 11. A channel region may connect the source/drain regions on opposite sides, and the channel region may be controlled by the gate stack. One of the source/drain regions at the upper and lower ends of the single memory cell serves as a source region and can be electrically connected to a source line; the other serves as a drain region and may be electrically connected to a bit line. For every two vertically adjacent memory cells, the source/drain region at the upper end of the lower memory cell and the source/drain region at the lower end of the upper memory cell may serve as source regions so that they may share the same source line connection.

The gate stack extends in a columnar shape in the vertical direction, overlapping a plurality of (in this example, three) memory device layers, and thus can define a plurality of memory cells stacked on each other in the vertical direction. The memory cells associated with a single gate stack pillar may form a memory cell string. A plurality of such memory cell strings are arranged on a substrate in correspondence with the layout of gate stack pillars (corresponding to the layout of the process channels T described above, e.g., a two-dimensional array), thereby forming a three-dimensional (3D) array of memory cells.

At the upper end of each memory cell string (in the device region), a selection transistor may be fabricated based on a selection device layer.

According to an embodiment of the present disclosure, the selection transistor may be formed based on the process channel T. For example, the gate stack of the select transistor may be formed in the process tunnel T with its active region surrounding the gate stack, similar to a memory cell. In this way, the resulting select transistor can be self-aligned to the underlying string of memory cells.

The active regions of the select transistors of the respective memory cell strings may be electrically isolated from each other to enable independent selection of the respective memory cell strings. To this end, the select device layer may be separated into localized portions around each process tunnel T as the active region for each select transistor.

To better provide a positional reference when locally selecting the device layers and to avoid affecting the gate stack (4025/4027) of the memory cell (e.g., especially in the case where the gate conductor layer 4027 comprises polysilicon), the gate stack (4025/4027) of the memory cell may be etched back to a thickness by anisotropic etching, such as RIE in the vertical direction, as shown in fig. 12(a) and 12 (b). In the space left in the process channel T by the etch back, the cap layer 4011 may be filled by a method such as deposition and then planarization (e.g., CMP, which may stop on the hard mask layer 4015). The cap layer 4011 may include, for example, SiC in consideration of etching selectivity (e.g., with respect to the hard mask layer 4015 such as nitride and the isolation layer such as oxide). Here, the bottom surface of the cap layer 4011 may be higher than the bottom surface of the hard mask layer 4015, so that the cap layer 4011 may be confined in the process channel portion defined by the hard mask layer 4015 and aligned with the gate stack of the underlying memory cell. The cap layer 4011 thus formed can be used as a positioning reference of an active region of the selection transistor.

Such a mask may be formed to define the active region of the select transistor: the mask includes separate portions surrounding the respective process channels T. Here, the self-aligned mask may be formed through a sidewall (spacer) forming process.

The hard mask layer 4015 may be removed by selective etching, for example. Thus, the cap layer 4011 exhibits an island shape protruding with respect to the select device layer, self-aligned to the memory cell gate stack. Spacers 4010 may be formed as a mask on sidewalls of such protruding island-like portions. For example, the spacers 4010 may be formed by depositing a layer of dielectric, such as nitride, in a substantially conformal manner (with etch selectivity with respect to the cap layer 4011 and the spacer layer), and then anisotropically etching the deposited dielectric, such as by RIE in the vertical direction, to remove laterally extending portions of the deposited dielectric while leaving vertically extending portions thereof. The thickness (dimension in the horizontal direction in the figure) of the spacers 4010 may define the size of the active region of the select transistor, for example, about 5nm to 20 nm.

The selective device layer may be anisotropically etched, such as by vertical RIE, using the spacers 4010 as an etch mask. RIE can stop at spacer layer 4023₄. Thus, the device layer (first source/drain layer 4007) is selected₄Channel layer 4005₄And a second source/drain layer 4009₄) Can be separated into localized portions respectively surrounding each process tunnel T, which define the active regions of the select transistors corresponding to each memory cell string.

For the select transistor, a source/drain region at a lower end thereof may be electrically connected to a gate stack of a corresponding memory cell string (which will be described further below), and a source/drain region at an upper end thereof may be electrically connected to a word line. Thus, the gate control voltage applied on each word line may be applied to the gate stack of the corresponding memory cell string via the corresponding select transistor.

Here, a word line electrically connected to the upper source/drain region of the selection transistor may be fabricated. For example, as shown in FIGS. 13(a) and 13(b), a spacer layer 4023 may be provided₄Forming an isolation layer 4012 thereon. The isolation layer 4012 can be formed by depositing, for example, an oxide, planarizing the deposited oxide such as CMP (which can stop at the cap layer 4011), and then etching back the planarized oxide. The isolation layer 4012 may shield the first source/drain layer 4007₄And a channel layer 4005₄While exposing the second source/drain layer 4009₄To be subsequently formed thereonThe word lines can be electrically connected to the second source/drain layer 4009₄And the first source/drain layer 4007₄And a channel layer 4005₄And (4) electrically isolating. Over the isolation layer 4012, a word line 4013 can be formed. The word lines 4013 may include a conductive material such as a metal, and may be formed by, for example, deposition and then etching, or a dual damascene process or the like. Word line 4013 can be connected to second source/drain layer 4009₄Are in contact and thus electrically connected. According to an embodiment, the second source/drain layer 4009 may be aligned before forming the word line 4013₄The exposed portion of (a) is subjected to silicidation to form a silicide, thereby reducing contact resistance with the word line 4013.

As shown in a top view in fig. 13(a), a plurality of word lines 4013 may be formed in a stripe shape extending in a first direction (horizontal direction within the paper plane in the drawing), and arranged in a second direction (vertical direction within the paper plane in the drawing) intersecting (e.g., perpendicular to) the first direction. Here, the word line 4013 may be formed in the device region without extending into the contact region to avoid interference with a contact portion subsequently formed in the contact region.

As shown in fig. 14, the voids in the present structure may be filled with a dielectric to facilitate further processing. Such filling may be performed by, for example, deposition followed by planarization. The filled dielectric may comprise the same material as the isolation layer 4012, such as an oxide, and thus they are shown as one in fig. 14 and labeled 4012'.

Can be in contact with the select device layer (particularly the channel layer 4005 therein) in the process channel T₄) The gate stack of the select transistor is formed at a corresponding height.

For example, as shown in fig. 15, the cap layer 4011 can be removed by selective etching to expose the gate stack of the memory cell. The gate stack of the memory cell may be recessed to a depth by selective etching. Here, the top surface of the gate stack of the recessed memory cell may be lower than the channel layer 4005 on the one hand₄So that a subsequently formed gate stack of the select transistor can be in contact with the channel layer 4005₄Overlap the entire height of (a); and on the other hand may be higher than the uppermost memory device layerTop surface (preferably higher than uppermost spacer layer 4023₄Top surface of the memory cell) to avoid unwanted electrical connections between subsequently formed select transistor-memory cell gate stack connections and the uppermost memory device layer.

In this way, the upper space of each processing passage T is released. The gate stacks of the select transistors may be formed in these spaces freed.

In consideration of electrical connection between the selection transistor and the gate stack of the memory cell, as shown in fig. 16, a selection transistor-memory cell gate stack connection 4014 may be formed in each process channel T. The selection transistor-memory cell gate stack connection 4014 may include a conductive material, for example, a metal such as tungsten (W). The selection transistor-memory cell gate stack connection 4014 may be formed by a method such as deposition and then etch back. The select transistor-memory cell gate stack connection 4014 can be a conductive layer on the top surface of the gate stack of the memory cell in each process channel T that contacts the gate stack of the memory cell (particularly the gate conductor layer 4027 therein) at the bottom surface and the first source/drain layer 4007 at the side surface₄. A top surface of the selection transistor-memory cell gate stack connection 4014 may be lower than the first source/drain layer 4007₄Of the substrate.

As shown in fig. 17, a gate stack of the selection transistor may be formed on the selection transistor-memory cell gate stack connection 4014 in each process channel T. A gate dielectric layer 4016 and a gate conductor layer 4018 may be formed in sequence as described above in connection with fig. 11. Here, the gate stack (4016/4018) of the select transistor may not have a memory function. For example, the gate dielectric layer 4016 may comprise an oxide or a high-k dielectric, and the gate conductor layer 4018 may comprise (doped) polysilicon or a metal.

The gate stack (4016/4018) of the select transistor is selected by the select device layer (first source/drain layer 4007)₄Channel layer 4005₄And a second source/drain layer 4009₄) Thereby defining the select transistor. Upper source/drain regions of the selection transistor (second source/drain layer 4009)₄) Source/drain regions (first source/drain layers 4007) electrically connected to the word lines 4013 and lower ends₄) Electrically connected via a selection transistor-memory cell gate stack connection 4014To the gate stack of the corresponding memory cell string (4025/4027).

In this way, the fabrication of the devices (including the memory cells and the select transistors) in the device region is completed.

Various electrical contacts may then be made (in the contact areas) to achieve the desired electrical connection.

To achieve electrical connection to the memory device layers, a stepped structure may be formed in the contact regions. There are a number of ways in the art to form such a stepped structure. According to an embodiment of the present disclosure, the stepped structure may be formed, for example, as follows.

As shown in fig. 17, the gate stack (of the select transistor) is now exposed. To protect the gate stack (in the device region) during the subsequent fabrication of the step structure, another hard mask layer 4029 may be formed on the isolation layer 4012', as shown in fig. 18(a) and 18 (b). For example, the hard mask layer 4029 may include a nitride. Over the hard mask layer 4029, a photoresist 4031 may be formed and lithographically patterned to shield the device regions and expose the contact regions. The hard mask layer 4029 and the side wall 4010 (both nitride in this example), the isolation layer 4012' and the isolation layer 4023 can be etched by selective etching such as RIE using the photoresist 4031 as an etching mask₄(in this example, oxide), the select device layer (in this example, Si), and the gate stack (and possibly word line 4013) to expose the memory device layer. The order of etching the layers may vary depending on the process. The surface of the contact region exposed by the photoresist 4031 can be made substantially flat after etching by controlling the etching depth. Thus, a step is formed between the contact region and the device region. After that, the photoresist 4031 may be removed.

As shown in fig. 19(a) and 19(b), a sidewall 4033 may be formed at a step between the contact region and the device region by a sidewall formation process. The sidewall 4033 may include, for example, an oxide. The width (in the horizontal direction in the figure) of the sidewall 4033 may define subsequent to the device layer 4005₃Source/drain regions 4009 in₃The size of the landing pad (landing pad) of the contact portion(s).

The sidewall 4033 thus formed is used as an etching mask, and can be selectively etchedSuch as RIE, to etch the exposed device layer 4005₃Source/drain regions 4009 in₃And a gate stack to expose the device layer 4005₃Of the channel region. The surface of the contact region exposed by the sidewall 4033 after etching can be made substantially flat by controlling the etching depth. For example, source/drain regions 4009 may be etched first₃And gate conductor layer 4027 (e.g., Si and poly-Si, respectively; if gate conductor layer 4027 comprises a metal gate, they can be etched separately), etching of which can stop at device layer 4005₃A channel region of (1); after such etching, the top end of the memory function layer 4025 may protrude from the device layer 4005₃And may be removed by RIE. Thus, in the contact region, in device layer 4005₃Source/drain regions 4009 in₃And a further step is formed with the surface exposed by the sidewall 4033.

Thus, the process described above in connection with fig. 19(a) and 19(b) may be repeated to form a plurality of steps in the contact region by forming the sidewalls and etching using the sidewalls as an etch mask, as shown in fig. 20(a) and 20 (b). These steps form a stepped structure such that for each source/drain region and optionally channel region in each memory device layer that requires electrical connection, the ends protrude relatively to the overlying region to define landing pads for contacts to that region. 4035 in fig. 20(a) and 20(b) indicates the remaining portion of the sidewall spacer formed at each time after the processing. These side walls 4035 are shown as one piece here since they are oxide with the isolation layers.

Thereafter, a contact may be made.

For example, as shown in fig. 21(a) and 21(b), the interlayer insulating layer 4037 may be formed by depositing an oxide and planarizing, such as CMP. Here, since both are oxide, both the previous isolation layer and the sidewall 4035 are shown as being integral with the interlayer insulating layer 4037. Then, as shown in fig. 22(a), 22(b), and 22(c), contacts 4039, 4040, and 4041 may be formed in the interlayer insulating layer 4037. Specifically, a contact 4039 is formed in the device region, electrically connected to the gate conductor layer 4018 in the gate stack of the selection transistor; contacts 4040 (contacts 4040 are only partially shown in the figure due to paper limitations) are formed in the device region, electrically connected to word line 4013; contacts 4041 are formed in the contact regions, electrically connected to the source/drain regions and optionally the channel region of each memory cell. The contact portion 4041 in the contact region may avoid the gate stack remaining in the contact region. These contacts may be formed by etching holes in the interlayer insulating layer 4037 and filling it with a conductive material such as a metal.

For every two adjacent memory cells in the vertical direction, the source/drain region located in the middle, i.e., the first memory device layer 4005₁Source/drain regions 4009 in₁And a second memory device layer 4005₂Source/drain regions 4007 in₂(and, a third memory device layer 4005₃Source/drain regions 4009 in₃And lower source/drain regions (not shown) in the fourth memory device layer above (if present)), may be electrically connected to source lines (whose source lines may be common) via contacts 4041; source/drain regions at upper and lower ends, i.e., first memory device layer 4005₁Source/drain regions 4007 in₁And a second memory device layer 4005₂Source/drain regions 4009 in₂(and, a third memory device layer 4005₃Source/drain regions 4007 in₃And upper source/drain regions in the fourth memory device layer above) may be electrically connected to bit lines via contacts 4041, respectively. In this way, a NOR type configuration can be obtained. Here, a contact to the channel region is also formed. Such contacts may be referred to as body contacts and may receive a body bias to adjust the device threshold voltage.

Here, two memory cells adjacent in the vertical direction are provided so that the source/drain regions located near the boundary therebetween are electrically connected to the source line. This can reduce the number of wirings. However, the present disclosure is not limited thereto. For example, vertically adjacent memory cells may be arranged in the same configuration of source-channel-drain or drain-channel-source.

In this embodiment, the dopant-containing isolation layer (which serves as the solid phase dopant source layer) remains. However, the present disclosure is not limited thereto. Other materials may be substituted for the solid phase dopant source layer after diffusion doping. For example, can beThe solid phase dopant source layer is replaced with other dielectric materials, particularly dielectric materials that do not intentionally contain dopants, to improve isolation performance. Alternatively, each two vertically adjacent device layers are grouped, and a solid phase dopant source layer between the device layers of each group (e.g., device layer 4005 as a group)₁And 4005₂Solid phase dopant source layer 4023 therebetween₂) May be replaced by a conductive material, such as a metal or doped semiconductor layer, to reduce interconnect resistance (to the source line); and solid phase dopant source layers on the upper and lower sides of each group (e.g., device layer 4005, for example)₁And 4005₂Solid phase dopant source layer 4023 under the group₁And a device layer 4005₁And 4005₂Upper set of solid phase dopant source layers 4023₃) May be replaced by a dielectric material to achieve isolation between bit lines. In the case of replacing the solid phase dopant source layer, an "interface layer" with an abrupt doping concentration as described above may also be formed on the side of the source/drain regions facing away from the channel region.

As shown in fig. 23(a), 23(b), and 23(c), an interlayer insulating layer (shown as 4037' integrally with the interlayer insulating layer 4037) may be further formed on the interlayer insulating layer 4037. In the interlayer insulating layer, a plurality of selection lines 4039' extending in the second direction and arranged in the first direction may be formed. Thus, each word line 4013 may be electrically connected to a row select transistor (in a first direction), and each select line 4039' may be electrically connected to a column select transistor (in a second direction). Selection of a memory cell string can be achieved by a word line 4013 and a select line 4039'. Of course, in the interlayer insulating layer, contact plugs 4040 'and 4041' electrically connected to the contacts 4040 and 4041 are also formed.

Fig. 25 schematically shows an equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure.

In the example of FIG. 25, three internal word lines IWL1, IWL2, IWL3 and six bit lines BL1, BL2, BL3, BL4, BL5, BL6 are schematically shown. However, the specific number of bit lines and internal word lines is not limited thereto. At the intersections of the bit lines and the internal word lines, memory cells MC are provided. Also shown in FIG. 25 are three source lines SL1, SL2, SL 3. As described above, each two adjacent memory device layers may share the same source line connection. In addition, the respective source lines may be connected to each other, so that the respective memory cells MC may be connected to a common source line. In addition, optional bulk connections to the memory cells are also shown schematically in dashed lines in FIG. 25. The body connection of each memory cell may be electrically connected to the source line connection of that memory cell.

The internal word lines IWL1 through IWL3 in FIG. 25 may correspond to the gate stacks of the memory cells as described above. Adjacent bit lines are isolated from each other in a vertical direction with respect to the substrate.

Each memory cell string or internal word line IWL 1-IWL 3 may have a select transistor SST on top and be connected to a respective word line WL1, WL2, WL3 via the select transistor SST. A gate electrode of the selection transistor SST may be connected to a selection line SSL.

Here, a two-dimensional array of memory cells MC is shown for convenience of illustration only. A plurality of such two-dimensional arrays may be arranged in a direction intersecting this two-dimensional array (for example, a direction perpendicular to the paper surface in the figure), thereby obtaining a three-dimensional array. Accordingly, in this direction, a plurality of selection lines SSL may be provided.

As shown in fig. 24(a) and 24(b), on the NOR cell array shown in fig. 23(a) to 23(c), peripheral circuits may be flip-chip mounted. As for the peripheral circuit, the description above in conjunction with fig. 2(a) and 2(b) can be referred to. The selection line 4039 ' and the contact plugs 4040 ' and 4041 ' are shown bonded to the bonding PAD2 of the peripheral circuit through the bonding portion BOND. However, the present disclosure is not limited thereto. For example, bond PADs may be provided on at least some of the select line 4039 ' and the contact plugs 4040 ' and 4041 ' to facilitate bonding with the bond PAD 2. As described above, the bonding may be performed directly, and the bonding member BOND may be omitted.

The memory device according to the embodiments of the present disclosure may be applied to various electronic devices. For example, the memory device may store various programs, applications, and data required for the operation of the electronic device. The electronic device may further include a processor cooperating with the memory device. For example, the processor may operate the electronic device by executing a program stored in the storage device. Such as a smart phone, a Personal Computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.