Three-dimensional ferroelectric random access memory (FERAM)
阅读说明：本技术 三维铁电随机存取存储器（feram） (Three-dimensional ferroelectric random access memory (FERAM) ) 是由 陈荣庭 于 2020-05-08 设计创作，主要内容包括：三维垂直存储器串阵列包括低成本、低功率或高密度且适用于SCM应用的高速铁电场效应晶体管(FET)单元。本发明的存储器电路提供随机存取能力。存储器串可以形成在衬底的平坦表面上方并且包括沿着相对于平坦表面的垂直方向纵向延伸的垂直栅极电极并且可以包括(i)栅电极之上的铁电层；(ii)栅极氧化物层；(iii)提供在栅极氧化物层之上的沟道层；以及(iv)嵌入氧化物层中并由氧化物层彼此隔离的导电半导体区域,其中栅电极、铁电层、栅极氧化物层、沟道层和每对相邻的半导体区域形成存储器串的储存晶体管,并且其中一对相邻的半导体区域充当储存晶体管的源极区域和漏极区域。(The three-dimensional vertical memory string array includes high-speed ferroelectric Field Effect Transistor (FET) cells that are low cost, low power, or high density and suitable for SCM applications. The memory circuit of the present invention provides random access capability. The memory string may be formed over a planar surface of a substrate and include a vertical gate electrode extending longitudinally along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode; (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by the oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer, and each pair of adjacent semiconductor regions form a storage transistor of the memory string, and wherein the pair of adjacent semiconductor regions serve as a source region and a drain region of the storage transistor.)
1. A memory string formed over a planar surface of a substrate, comprising:
a gate electrode extending longitudinally in a perpendicular direction with respect to the planar surface,
a ferroelectric layer provided over at least a portion of the gate electrode in a horizontal direction and extending longitudinally in the vertical direction;
a gate oxide layer provided over at least a portion of the ferroelectric layer in the horizontal direction and extending longitudinally in the vertical direction;
a plurality of semiconductor structures provided adjacent to the gate oxide layer along the vertical direction, each semiconductor structure comprising: (i) a first semiconductor material of a first conductivity type; and (ii) a second semiconductor material and a third semiconductor material electrically isolated from each other and each coplanar with and adjacent to the first semiconductor material, the second semiconductor material and the third semiconductor material each having a second conductivity type different from the first conductivity type, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, and the semiconductor structure form a storage transistor of the memory string, and wherein the first semiconductor material, the second semiconductor material, and the third semiconductor material form channel, source, and drain regions of the storage transistor.
2. The memory string of claim 1, further comprising a barrier layer provided between the gate electrode and the ferroelectric layer.
3. The memory string of claim 2, wherein the barrier layer comprises titanium nitride, tungsten nitride, or tantalum nitride.
4. The memory string of claim 1, wherein the gate electrode comprises tungsten or a heavily doped semiconductor.
5. The memory string of claim 1, further comprising a conductor adjacent to each of the second semiconductor material and the third semiconductor material of each semiconductor structure.
6. The memory string of claim 5, wherein the conductor comprises tungsten, a metal adhesion layer, or a combination thereof.
7. The memory string of claim 5, wherein the drain or source regions each comprise n+Polycrystalline silicon.
8. The memory string of claim 1, wherein the memory string is one of a plurality of memory strings in a memory array, wherein the memory array comprises a stepped configuration that provides electrical contact to each of the source or drain electrodes.
9. The memory string of claim 1, wherein the memory string is one of a plurality of memory strings in a memory array, wherein the memory array includes a network of global word line conductors each connecting the gate electrodes of a selected group of the memory strings.
10. The memory string of claim 9, wherein the network of global word line conductors is provided above the memory string.
11. The memory string of claim 1, wherein the ferroelectric layer comprises HfO2A ferroelectric material.
12. The memory string according to claim 11, wherein the ferroelectric layer has a thickness of 5.0-30.0nm, preferably 8.0-20.0 nm.
13. The memory string of claim 11, wherein the ferroelectric layer comprises zirconium doped hafnium silicon oxide.
14. The memory string of claim 13, wherein the zirconium-doped hafnium silicon oxide has a zirconium content of 40-60%, preferably 45-55%.
15. The memory string of claim 13, wherein the zirconium-doped hafnium silicon oxide comprises HfxZr1-xOyFerroelectric thin film, wherein x ranges between 0.4 and 0.6, preferably between 0.45 and 0.55, and y ranges between 1.8 and 2.2, preferably between 1.9 and 2.1.
16. The memory string of claim 13, wherein HfO is deposited by using an ALD layer-by-layer lamination step2And ZrO2To prepare the zirconium doped hafnium silicon oxide.
17. The memory string of claim 11, wherein the ferroelectric layer comprises silicon-doped hafnium silicon oxide.
18. The memory string of claim 17, wherein the silicon content of the silicon doped hafnium silicon oxide is 2.0-5.0%, preferably 2.5-4.5%.
19. The memory string of claim 17, wherein the silicon-doped hafnium silicon oxide comprises HfxSi1-xOyFerroelectric thin film, wherein x ranges from 0.02 to 0.05, preferably between 0.025 and 0.04, and y ranges from 1.8 to 2.2, preferably between 1.9 and 2.1.
20. The memory string of claim 17, wherein HfO is deposited by using an ALD layer-by-layer lamination step2And SiO2To prepare the silicon doped hafnium silicon oxide.
21. The memory string of claim 1, further comprising a charge trapping layer between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and a barrier layer adjacent to the gate electrode.
22. The memory string of claim 1, wherein the barrier layer comprises titanium nitride.
23. A process for fabricating a memory structure over a planar surface of a substrate, comprising:
forming a bottom isolation layer on the planar surface;
forming and patterning an etch stop layer over the bottom isolation layer;
forming a predetermined number of alternating layers of intermediate isolation material and first dielectric material;
cutting a plurality of wells from a top of the alternating layers of intermediate isolation material and first dielectric material down to the etch stop layer;
recessing each of the layers of the first dielectric material to create a first plurality of recesses;
filling each of the recesses with a first semiconductor material of a first conductivity type;
conformally forming a gate oxide layer over a sidewall of a well, the gate oxide material being in contact with the first semiconductor material along the sidewall of the well in the recess;
conformally forming a ferroelectric layer on the gate oxide layer;
filling the well with a conductive gate material to form a gate electrode;
forming a plurality of slots between the filled wells by the alternating layers of intermediate isolation material and the first dielectric material;
recessing the exposed first dielectric material along sidewalls of the trench to form a second plurality of recesses, and exposing at least a portion of the first semiconductor material in each recess; and
a second semiconductor material of a second conductivity type is conformally formed on the inner walls of the second plurality of recesses.
24. The process of claim 23, further comprising conformally forming an adhesive conductor layer between the conductive gate material and the ferroelectric layer.
25. The process of claim 23, further comprising filling the second plurality of recesses with a metal conductor.
26. The process of claim 25, wherein the conductor comprises tungsten, a metal adhesive layer, or a combination thereof.
27. The process of claim 23 further comprising forming a barrier layer between the gate electrode and the ferroelectric layer.
28. The process of claim 27, wherein the barrier layer comprises titanium nitride, tungsten nitride, or tantalum nitride.
29. The process of claim 23, wherein the gate electrode comprises tungsten or a heavily doped semiconductor.
30. The process of claim 23, wherein the ferroelectric layer comprises HfO2A ferroelectric material.
31. The process according to claim 30, wherein the ferroelectric layer has a thickness of 5.0-30.0nm, preferably 8.0-20.0 nm.
32. The process of claim 30 wherein the ferroelectric layer comprises zirconium doped hafnium silicon oxide.
33. The process of claim 32, wherein the zirconium-doped hafnium silicon oxide has a zirconium content of 40-60%, preferably 45-55%.
34. The process of claim 32 wherein said zirconium doped hafnium silicon oxide comprises HfxZr1-xOyFerroelectric thin film, wherein x ranges between 0.4 and 0.6, preferably between 0.45 and 0.55, and y ranges between 1.8 and 2.2, preferably between 1.9 and 2.1.
35. The process of claim 32, wherein HfO is deposited by using an ALD layer-by-layer lamination step2And ZrO2To prepare the zirconium doped hafnium silicon oxide.
36. The process of claim 30 wherein the ferroelectric layer comprises silicon-doped hafnium silicon oxide.
37. The process of claim 36, wherein the silicon content of the silicon doped hafnium silicon oxide is 2.0-5.0%, preferably 2.5-4.5%.
38. The process of claim 36 wherein said silicon doped hafnium silicon oxide comprises HfxSi1-xOyFerroelectric thin film, wherein x ranges from 0.02 to 0.05, preferably between 0.025 and 0.04, and y ranges from 1.8 to 2.2, preferably between 1.9 and 2.1.
39. The process of claim 36, wherein HfO is deposited by using an ALD layer-by-layer lamination step2And SiO2To prepare the silicon doped hafnium silicon oxide.
40. The process of claim 23 further comprising forming a charge trapping layer between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and a barrier layer adjacent to the gate electrode.
Technical Field
The present invention relates to memory circuits. In particular, the present invention relates to high density ferroelectric random access memory arrays comprising memory cells provided in a three-dimensional configuration.
Background
Erase operations in three-dimensional non-volatile memory circuits (e.g., NAND-type flash memory circuits) are typically performed on a block-by-block basis, which involves long access times. Such memory circuits are not suitable for high speed (-50 ns), high density storage-like memory (SCM) applications.
For example, other alternative memory circuits include:
(i) while allowing bit-by-bit access suitable for SCM applications, 3D XPoint memory circuits developed jointly by intel corporation and photonics corporation use cross-point patterning (i.e., double exposure to pattern each material layer), which is prohibitively expensive to manufacture. Furthermore, such 3D XPoint memory circuits are based on Phase Change Materials (PCM), which results in high leakage currents, resulting in high power consumption of the sneak path. Selector devices are required to reduce leakage current from the sneak path, which increases the complexity of the process and device integration.
(ii) U.S. patents 10,249,370, 10,121,554, 10,121,553, and 9,892,800 disclose three-dimensional vertical NOR-type memory string arrays that require complex X and Y patterning schemes. Power consumption is also high due to the NOR architecture.
Ferroelectric memory circuits provide another alternative. U.S. patent 6,067,244 entitled Ferroelectric Dynamic Random Access Memory (FeFET), filed by ma on 16/9/1998, discloses a Ferroelectric field effect transistor (FeFET) that can be used as a Memory circuit because the dipole moment in the FeFET can be aligned by an electric field in either of two configurations. However, conventional ferroelectric materials, such as those based on lead zirconate titanate (PZT) and Strontium Bismuth Tantalate (SBT), for example, do not provide high density memory circuits. This is because the ferroelectric layer in fefets based on these materials must be at least 70nm thick.
However, based on hafnium oxide (HfO)2) Has a promising future. U.S. patent application publication 2018/0366547a1 ("Liu") discloses various examples of fefets. For example, fig. 2a and 2B, which are copied from fig. 4A and 4B in the disclosure of Liu, respectively, illustrate the programmed states of the exemplary FeFET 1.
As shown in fig. 2a and 2b, fefets 1 are formed on a p-type substrate 10 and respectively include n+Type source regions 101 and n+A type drain region 102, a channel region 103, a tunneling dielectric layer 13, a charge storage region 12, and a gate electrode 11. The charge region 12 includes a ferroelectric layer 120 and a paramagnetic layer 121. The paramagnetic layer 121 has a "quantum well" band structure, which makes the charge trapping capability suitable for data storage applications. For example, the compliant layer 121 can have alternating layers of a base material and a dielectric material. For example, the base material may be Hf1-xSixO2-x has a value between 0.02 and 0.65 and the dielectric material may be selected from the group consisting of hafnium oxide, zirconium oxide, titanium nitride, tantalum nitride, aluminum oxide, tantalum oxide and any combination thereof. For example, alternating layers of substrate material and dielectric material may be formed using an ALD process.
The ferroelectric layer 120 may include an alkaline earth metal oxide or a transition metal oxide (such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide) with or without 2-10% dopant selected from the group consisting of silicon, aluminum, yttrium, strontium, gadolinium, lanthanum, and any combination thereof. One example of a ferroelectric material is Hf1-xSixO2And x ranges between 0.01 and 0.05. The composite material may also include hydrogen atoms in the manufacturing process. Liu discloses a charge storage regionThe thickness of the domains 12 may be 1.0-30.0nm, preferably 5.0-15.0 nm.
As shown in fig. 2a, when a positive bias (e.g., Vt) is applied to the gate electrode 11, the electric dipole in the ferroelectric layer 12 is aligned with the electric field, such that electrons in the channel region 103 tunnel through the tunneling dielectric layer 13 into the paraelectric layer 121 and are trapped in the paraelectric layer 121. The trapped charge causes positive charge carriers (i.e., holes) to accumulate in the channel region 103 (the "0" state, which provides a polarization switching voltage for the storage transistor). In this "0" state, FeFET 1 is non-conductive at the read voltage.
As shown in fig. 2b, when a negative bias voltage (e.g., -Vt) is applied to the gate electrode 11, the electric dipole in the charge storage region 12 allows holes in the channel region 103 to tunnel to the paraelectric layer 121 and be trapped in the paraelectric layer 121. The trapped charge causes an accumulation of electrons at the channel region 103 (a "1" state, which provides a negative polarization switching voltage). In this "1" state, the FeFET 1 conducts at the read voltage.
Liu also discloses that the ferroelectric layer 120 and the paramagnetic layer 121 need not be different. The ferroelectric layer 120 and the paraelectric layer 121 may be provided as a single layer as a mixture of a ferroelectric material and a paraelectric material.
As disclosed by Liu, a FeFET based on hafnium oxide can be made with a ferroelectric layer having a thickness of less than 10 nm. Further, such fefets may provide a threshold shift window of 1 volt. For example, an article entitled "Low-Leakage Current-Like DRAM Memory Using a Single-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric" (Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric) "published by C.Cheng and A.Chin in IEEE Electronic Device Letters (vol 35, No. 1, p. 138-140), discloses an article With a 30nm thick zirconium-doped HfO (" Cheng ") that discloses a Memory cell With a high Leakage Current-Like DRAM-Gate Dielectric2A high endurance FeFET of a ferroelectric layer that can be programmed or erased within 5 ns.
FIG. 1a shows a 4F catalyst which may be conventional2The architecture of an AND-type FeFET array for layout is configured. FIG. 1a also provides a table showing selection FVoltage biasing of the word line (WL (m)), the source line (SL (m)), and the bit line (BL (m)) of the eFET, and voltage biasing of the word line (WL (m +1)), the source line (SL (m +1)), and the bit line (BL (m +1)) of the unselected FeFET during program, erase, and read operations. For example, in Cheng, the programming voltage V of such a FeFETpmgAnd a read voltage VreadMay be-4.0 volts and-0.1 volts, respectively.
Fig. 1b shows the architecture of a NOR-type FeFET array. Fig. 1b also provides a table showing the voltage bias of the word line (WL (m)), source line (SL (m)), and bit line (BL (m)) of the selected FeFET, and the voltage bias of the word line (WL (m +1)), source line (SL (m +1)), and bit line (BL (m +1)) of the unselected FeFET during program, erase, and read operations.
Disclosure of Invention
A three-dimensional vertical memory string array includes high-speed ferroelectric Field Effect Transistor (FET) cells that are low cost, low power, or high density and suitable for SCM applications. The memory circuit of the present invention provides random access capability.
According to one embodiment of the present invention, a memory string formed over a planar surface of a substrate, comprising: (a) a vertical gate electrode (e.g., tungsten or a heavily doped semiconductor) extending longitudinally in a vertical direction with respect to the planar surface, (b) a ferroelectric layer provided on at least a portion of the gate electrode in a horizontal direction substantially parallel to the planar surface and extending longitudinally in the vertical direction; (c) a gate oxide layer provided on at least a portion of the ferroelectric layer in a horizontal direction and extending longitudinally in a vertical direction; (d) a channel layer provided on at least a portion of the gate oxide layer in a horizontal direction and extending longitudinally in a vertical direction; and conductive semiconductor regions embedded in and isolated from each other by the oxide layer arranged in the horizontal direction, wherein the gate electrode, the ferroelectric layer, the channel layer, the gate oxide layer, and each pair of adjacent semiconductor regions form a storage transistor of the memory string, and wherein the pair of adjacent semiconductor regions serve as a source region and a drain region of the storage transistor. Furthermore, a barrier layer (e.g., titanium nitride, tungsten nitride, or tantalum nitride) may be provided between the gate electrode and the ferroelectric layer. Leakage netThe gate or source region may also provide a drain or source electrode (e.g., tungsten or n)+Polysilicon).
The memory strings of the present invention may be organized into a memory array, and the stepped configuration provides electrical contact to each of the source or drain electrodes. The storage transistors may be provided on opposite sides of each memory hole in which the gate electrode, the ferroelectric layer, the gate oxide layer, and the channel silicon layer are provided. One or more global word line conductor networks, each connecting the gate electrodes of a selected group of memory strings, may be provided above the memory array, below the memory array, or both.
The ferroelectric layer comprises zirconium-doped or silicon-doped HfO2A ferroelectric material. The zirconium doped hafnium silicon oxide may have a zirconium content of 40-60%, preferably 45-55%. The silicon doped hafnium silicon oxide may have a silicon content of 2.0-5.0%, preferably 2.5-4.5%. Hafnium silicon oxide is deposited by using ALD layer-by-layer lamination step to deposit HfO2And SiO2Or ZrO2To prepare the compound.
In one embodiment, the memory string further includes a charge trapping layer between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and the barrier layer.
Various fabrication processes, some of which are shown here, can be used to fabricate the memory array of the memory string of the present invention.
The invention may be better understood by considering the following detailed description in conjunction with the accompanying drawings.
Drawings
FIG. 1a shows a 4F element which may be conventional2The architecture of an AND-type FeFET array for layout is configured.
Fig. 1b shows the architecture of a NOR-type FeFET array.
Fig. 2a and 2B (reproduced from fig. 4A and 4B of U.S. patent application publication 2018/0366547a1 ("Liu")) illustrate the programmed states of an exemplary FeFET 1.
Fig. 3a shows a vertical cross-section of a memory array 300 comprising a regular arrangement of vertical three-dimensional (3D) FeFET strings; fig. 3a specifically illustrates vertical 3D FeFET strings 300a, 300b, and 300c according to one embodiment of the invention.
Fig. 3b shows a Y-Z plane cross section of a memory array 300 showing gate, drain and source connectivity for eight vertical 3D FeFET strings, according to one embodiment of the invention.
Fig. 4a, 4b, 4c, 4d (i), 4d (ii), 4e, 4f, 4g, 4h (i), 4h (ii), 4i (i), 4i (ii), 4j (i), 4j (ii), 4k (i), 4k (ii), 4l (i), and 4l (ii) illustrate an exemplary fabrication process for a memory array 400 according to one embodiment of the invention.
Fig. 5 illustrates that the memory array 400 provides electrical contact or connection to the drain or source electrode 423 via a stepped structure on both sides of the memory array 400 and contact or connection to the gate electrode 423 using a bottom global word line (e.g., global word line 401).
Fig. 6a, 6b, 6c (i), 6c (ii), 6d, 6e, 6f (i), 6f (ii), 6g (i), 6g (ii), 6h (i), 6h (ii), 6i, and 6j illustrate an exemplary fabrication process of a memory array 600 according to one embodiment of the invention.
Fig. 7a, 7b (i), 7b (ii), 7c (i), 7c (ii), 7d, 7e, 7f and 7g illustrate an exemplary fabrication process of a memory array 700 according to one embodiment of the invention.
FIGS. 8a, 8b-1, 8b-2, 8c, 8d-1, 8d-2, 8e, 8f, 8g (i), 8g (ii), 8h (i), 8h (ii), 8i (i), 8i (ii), 8i (iii), and 8j illustrate an exemplary fabrication process for a memory array 800 according to one embodiment of the invention.
To facilitate cross-reference between the figures, like elements are assigned like reference numerals. These figures may depict three-dimensional objects from different angles. For ease of describing the three-dimensional object, a cartesian coordinate system is provided, where the X and Y directions represent orthogonal horizontal directions and the Z direction represents a vertical direction. Since the detailed description relates to structures fabricated on a planar surface of a substrate, "vertical" is understood to refer to a direction substantially perpendicular to the planar surface, and "horizontal" is understood to refer to a direction substantially parallel to the planar surface.
Detailed Description
For example, the invention may be carried out by a vertical metal-ferroelectric-insulator semiconductor (MFIS) transistor comprising (i) tungsten nitride/titanium nitride or (ii) n+Polysilicon/titanium nitride gate electrode, (ii) zirconium-doped or silicon-doped HfO2A ferroelectric layer, (iii) a gate oxide layer, (iv) a p-type channel region, (v) an n-type source region, and (v) an n-type drain region.
In such an MFIS transistor, n+The polysilicon may be doped with a dopant concentration of 5.0 x 1021To 1.0X 1022cm-3Arsenic doped polysilicon. Depositing HfO by Atomic Layer Deposition (ALD)2The ferroelectric layer may have a thickness of 5.0-15.0nm, preferably 8.0-12.0 nm. If doped with zirconium, the zirconium content of the ferroelectric layer should be 40-60%, preferably 45-55%. If doped with silicon, the silicon content of the ferroelectric layer should be 2.0-5.0%, preferably 2.5-4.5%. For example, the gate oxide layer may be a silicon oxide (SiO) with a thickness of 1.0-3.0nm2) Or silicon oxynitride (SiON). For example, the p-type channel region may be of a dopant concentration of 1.0 × 1016To 1.0X 1018cm-3By using boron, diborane (H)2B2) And trimethylborane B (CH)3)3Chemical Vapor Deposition (CVD) of any of gases, or any combination thereof, to deposit the p-type channel region. For example, the n-type drain region and the source region may each be of a dopant concentration of 1.0 × 1020To 1.0X 1022cm-3With phosphorus-doped or arsenic-doped polysilicon, by using Phosphorus Hydride (PH) if doped with phosphorus3) Or phosphorus trichloride (PCl)3) By using arsenic or arsenic hydride (AsH) if arsenic is doped3) To deposit the n-type drain and source regions.
Si doped Hf1-xSixOyFerroelectric thin films can be deposited HfO by layer-by-layer lamination using ALD2And SiO2Which allows the values of x and y to pass through the HfO2And SiO2Is adjusted. For example, a range of xThe circumference may be from 0.02 to 0.05, preferably between 0.025 to 0.04, and y may range from 1.8 to 2.2, preferably between 1.9 to 2.1. For example, for FeFET memory applications, a suitable Hf1-xSixOyThe thickness of the ferroelectric thin film may be between 5.0 and 15.0nm, preferably between 8.0 and 12.0 nm. HfO2Can be prepared from any of the following precursors: tetrakis (ethylmethylamino) hafnium (TEMAH) (tetramethylethylenediamine) hafnium (TEMAH)), tetrakis (dimethylamino) hafnium (TDMAH) (tetramethylethylenediamine) hafnium (TDMAH)), and hafnium tetrachloride (HfCl)4)，O3Or H2O is used as the oxidizing agent and the deposition temperature is between 150 ℃ and 400 ℃. Similarly, SiO2Can be prepared from any of the following precursors: tetrakis (dimethylamino) silane (4DMAS) (tetramis (dimethyllamino) silane (4DMAS)), tris (dimethylamino) silane (3DMAS) (tris (dimethyllamino) silane (3DMAS)), tetrakis (ethylmethylamino) silane (TEMA-Si) (tetramis (ethylmethylamino) silane (TEMA-Si)), and silicon tetrachloride (SiCl)4)，O3Or H2O is used as the oxidizing agent and the deposition temperature is between 150 ℃ and 400 ℃.
Zr doped HfxZr1-xOyFerroelectric thin films can be deposited HfO by layer-by-layer lamination using ALD2And ZrO2Which allows the values of x and y to pass through the HfO2And ZrO2Is adjusted. For example, x may range between 0.4 and 0.6, preferably between 0.45 and 0.55, and y may range between 1.8 and 2.2, preferably between 1.9 and 2.1. For FeFET memory applications, suitable HfxZr1-xOyThe ferroelectric thin film may have a thickness of 5.0 to 15.0nm, and preferably 8.0 to 12.0 nm. HfO2Can be prepared from any of the following precursors: tetrakis (ethylmethylamino) hafnium (TEMAH) (tetramethylethylenediamine) hafnium (TEMAH)), tetrakis (dimethylamino) hafnium (TDMAH) (tetramethylethylenediamine) hafnium (TDMAH)), and hafnium tetrachloride (HfCl)4)，O3Or H2O is used as the oxidizing agent and the deposition temperature is between 150 ℃ and 400 ℃. ZrO (ZrO)2Can be prepared from any of the following precursors: tetrakis (ethylmethylamino) zirconium (TEMAZ) (tetrakis (ethylmethylami)no) zirconium (temaz), tetrakis (dimethylamino) zirconium (TDMAZ) (tetrakis (dimethyllamino) zirconium (TDMAZ)), and zirconium tetrachloride (ZrCl @4)，O3Or H2O is used as the oxidizing agent and the deposition temperature is between 150 ℃ and 400 ℃.
Fig. 3a shows a vertical cross-section in the X-Z plane of memory array 300, the vertical cross-section comprising a regular arrangement of vertical three-dimensional (3D) FeFET strings; fig. 3a specifically illustrates vertical 3D FeFET strings 300a, 300b, and 300c according to one embodiment of the invention. Fig. 3a shows three vertical 3D FeFET strings for illustration purposes only; the memory array 300 may include many more vertical 3D FeFET strings than vertical 3D FeFET strings arranged in each of the X-direction and the Y-direction.
As shown in fig. 3a, each vertical 3D FeFET string includes (i) a plurality of annular drain electrodes 301-1, 301-2, … …, and 301-n, (ii) a plurality of annular source electrodes 302-1, 302-2, … …, and 302-n, (iii) an annular channel polysilicon region 303, (iv) a gate or tunnel oxide layer 303a, and (v) an annular ferroelectric layer 304, surrounding a common gate electrode 308. The common gate electrode 308 may have a conductor core (e.g., tungsten doped or heavily doped n-type polysilicon) with an outer adhesion or barrier layer (e.g., titanium nitride) 305. Each vertical 3D FeFET string is electrically isolated by a top isolation layer 307 and a bottom isolation layer 309.
For example, each drain or source electrode may be provided by n-type polysilicon, titanium nitride, tungsten, or any combination of these materials. For example, the channel polysilicon region may be provided by p-type polysilicon. The ferroelectric layer 304 may be made of zirconium-doped or silicon-doped HfO2A ferroelectric material is provided. For example, the common gate electrode may be formed of tungsten nitride/titanium nitride or n+Polysilicon/titanium nitride is provided. For example, the gate oxide layer 303a may be made of SiO2Or SiON.
In each vertical 3D FeFET string, each memory cell is an MFIS transistor formed by a pair of adjacent drain and source electrodes (e.g., drain electrode 301-1 and source electrode 302-1) and portions of channel polysilicon region 303, gate or tunnel oxide layer 303a, annular ferroelectric-paraelectric layer 304, and common gate electrode 308 between the adjacent drain and source electrodes. Fig. 3a also shows that the gate electrodes of vertical 3D FeFET strings 300a, 300b, and 300c are electrically connected by conductive global word line 306. In memory array 300, (i) common gate electrodes in a row of vertical 3D FeFET strings along the X direction are electrically connected; (ii) the drain electrodes of the same vertical stage of a row of vertical 3D FeFET strings in the Y direction are electrically connected; and the source electrodes of the same vertical stage of a row of vertical 3D FeFET strings in the Y direction are electrically connected.
Fig. 3b shows a Y-Z plane cross section of memory array 300 showing the gate, drain and source connections of eight vertical 3D FeFET strings according to one embodiment of the invention. Likewise, fig. 3b shows eight vertical 3D FeFET strings for illustration purposes only. In any embodiment, the memory array 300 may include more vertical 3D FeFET strings than eight vertical 3D FeFET strings arranged in each of the X-direction and the Y-direction. FIG. 3b illustrates selection of an MFIS transistor or cell 401 by application of a select voltage bias across the associated gate electrode 308-m, drain electrode 301-m and source electrode 302-m. There are three types of unselected MFIS transistors: (a) "selected gate, unselected drain or source" MFIS transistors — those MFIS transistors that share a selected gate electrode 308-m but are associated with one of the unselected drain electrodes 301 and one of the unselected source electrodes 302; (b) "unselected gate, selected drain or source" MFIS transistors-those MFIS transistors associated with one of the unselected gate electrodes 308 but associated with a selected drain electrode 301-m and a selected source electrode 302-m; and (c) "unselected gate, unselected drain or source" MFIS transistors-those MFIS transistors that are associated with neither the selected gate electrode 308-m nor the selected drain electrode 301-m and the selected source electrode 302-m. In a read, program or erase operation, the selected MFIS transistor and each of the three unselected MFIS transistors require a different voltage bias.
Fig. 4a-4l illustrate an exemplary fabrication process of a memory array 400 according to one embodiment of the invention. As shown in vertical cross-section in fig. 4a, a conductor network comprising global gate lines 402 ("global gate lines") is formed over a semiconductor substrate 401, which semiconductor substrate 401 may be a semiconductor wafer. The global gate lines may be formed of tungsten, isolated from each other and from the semiconductor substrate 401 by an isolation layer (e.g., silicon oxide).
Thereafter, as shown in vertical cross-section in fig. 4b, an oxide layer 403 (e.g., silicon oxide) and a bottom etch stop layer 404 (e.g., n) are deposited over the global gate lines+Polysilicon). As shown, the etch stop layer 404 may be patterned and embedded in the oxide layer 403. As shown in vertical cross-section in fig. 4c, alternating layers of silicon oxide layers 405 and silicon nitride layers 406, herein numbered as silicon oxide layers 405-1, … …, and 405-n, respectively, and silicon nitride layers 406-1, … …, 406-n are then deposited.
An array of wells ("memory holes") 407 (e.g., memory holes 407-1, 407-2, and 407-3) are then etched down through the alternating layers of silicon oxide layer 405 and silicon nitride layer 406 to the etch stop layer 404, as shown in vertical cross-section in fig. 4d (i). Fig. 4d (ii) shows a horizontal cross-section through one of silicon nitride layers 406 showing memory holes 407-1 to 407-9 of memory array 400 at this step of formation.
A polysilicon layer 409 is then conformally deposited, followed by a thin gate oxide layer 410. The polysilicon 409 may be deposited as amorphous silicon and annealed at 850 c for 2 hours to crystallize. A protective layer 408 may then be deposited over the gate oxide layer 410. A spacer etch is then performed to remove any deposited polysilicon and gate oxide from the bottom of the memory hole 407. A Chemical Mechanical Polishing (CMP) step may be performed to remove the material of the material protection layer 408, the gate oxide 410 and the polysilicon layer 409 from the top of the structure. The resulting structure (i.e., memory array 400 at this stage of formation) is shown in vertical cross-section in fig. 4 e.
The protective layer 408 is then removed. Then a ferroelectric layer 411 (e.g., Si-doped or Zr-doped Hf) is deposited1-xSixOy、HfxZr1-xOyFerroelectric thin film). The CMP and bottom etch steps remove excess ferroelectric material from the top of the structure and the bottom of memory holes 407. The bottom of the memory hole 407 is then removedAnd portions of the etch stop layer 404 exposed at the portions. The oxide etch then creates a via that exposes a global gate line (e.g., global gate line 402) under memory hole 407. The resulting structure (vertical cross-section) is shown in fig. 4 f.
An adhesion/barrier layer of titanium nitride (TiN)412 is then conformally deposited. An etching step then removes the TiN material from portions of memory holes 407. Other barrier layers (e.g., tungsten nitride or tantalum nitride) may also be used. The memory hole 407 is then filled with a gate electrode material 413, the gate electrode material 413 may be chemical vapor deposited tungsten ("CVD W") or n+Polysilicon (i.e., heavily doped n-type polysilicon). Excess deposited material is then removed from the top of the structure by CMP. The resulting structure (vertical cross-section) is shown in fig. 4 g.
Thereafter, a top isolation layer 415 (e.g., silicon nitride) is provided over the memory array 400. The top spacer layer 415 is then patterned and an etching step creates trenches 414 (e.g., trenches 414-1, 414-2, 414-3, and 414-4) through the top spacer layer 415 and the alternating silicon nitride layer 406 and oxide layer 405. The resulting structure (vertical cross-section) is shown in fig. 4h (i). Fig. 4h (ii) shows a horizontal cross section of the memory array 400 through one of the nitride layers 406.
A wet etch step (e.g., hot phosphoric acid) is performed to remove the silicon nitride layer 406. During this step, silicon nitride material is removed from the exposed surfaces of the silicon nitride layer 406 in the sidewalls of the trenches 414. A further etch step removes the exposed portions of the channel polysilicon 409 and gate oxide 410. Then depositing and annealing a layer n+A polysilicon layer 420. A TiN layer 418 and a tungsten layer 419 are then sequentially deposited to fill the voids left after the silicon nitride removal. Removing excess n from the top of the structure and the sidewalls of the trench 414+Polysilicon, TiN and tungsten materials. The resulting structures are shown in vertical and horizontal cross-sections in fig. 4i (i) and 4i (ii), respectively. In fig. 4i (i), the resulting structure is enlarged in the inset, where the top two silicon nitride layers 406 (i.e., silicon nitride layers 406-n and 406- (n-1)) have been removed. As shown in the inset, (a) n in each silicon nitride layer+The polysilicon layer 420 is diffused after thermal annealingA recess is formed in the crystalline silicon layer 409 and the gate oxide layer 410, and (b) the TiN layer 418 is lined with n+The outside of layer 420, and (c) tungsten layer 419 fills the remaining voids. n is+The recesses of the polysilicon layer 420 become the drain and source regions of the MFIS transistor. The TiN layer 418 and the tungsten layer 419 become a source or drain electrode 423.
In some embodiments, silicon nitride layer 406 is not completely removed. As the etching of the silicon nitride layer 406 begins from the sidewalls of the trenches 414, such that the strips of silicon nitride separate and electrically isolate the resulting source or drain terminals on opposite sides of each memory hole. In this way, two vertical 3D FeFET strings are now provided per memory hole, since n is on opposite sides of each silicon nitride layer per memory hole+The polysilicon recess forms a separate drain region or source region. This alternative embodiment is illustrated in the structures shown in vertical and horizontal cross-sections in fig. 4j (i) and 4j (ii), respectively. As shown in fig. 4j (ii), incomplete removal of the silicon nitride layer 406 leaves a silicon nitride layer 421 that provides separate sets 423L and 423R of drain or source electrodes.
Silicon oxide 422 is then deposited to fill the trenches 414. The CMP step removes excess silicon oxide from the top of the memory array 400. For the embodiments of fig. 4i (i) and 4i (ii), the results obtained are shown in vertical and horizontal cross-sections in fig. 4k (i) and 4k (ii), respectively. Similarly, for the embodiments of fig. 4j (i) and 4j (ii), the resulting structures are shown in vertical and horizontal cross-sections in fig. 4l (i) and 4l (ii), respectively.
The connection to the drain or source electrodes 423 (or 423L and 423R, in alternative embodiments) may be made using a stepped configuration used in 3D NAND non-volatile memory arrays. Fig. 5 shows a memory array 400 with electrical contact or connection to drain or source electrode 423 provided via a stepped structure on both sides of memory array 400 and contact or connection to gate electrode 413 provided using a bottom global gate (e.g., global gate 402). Stepped configurations and associated manufacturing methods are known to those of ordinary skill in the art.
In one embodiment, the ferroelectrics of the MFIS for the "1" and "0" statesThe polarization switching voltages across the capacitor layers are respectively ± 1.5 volts. During a program or erase operation, the voltage across the ferroelectric layer is approximately the gate-to-source voltage (V) of the MFISGS) Half of that. Thus, a programming voltage V of 6-7 volts at the gate electrode can be usedPGMTo implement the programming of the MFIS. Table 1 shows the voltage bias of the MFIS transistors in the memory array 400 during a programming operation.
TABLE 1
As shown in Table 1, program disturb is avoided in the unselected MFIS transistors because in each case, the gate-to-source voltage (V)GS) Are less than 1/3VPGMThis is, by design, less than the polarization switching voltage of state "0".
Similarly, an erase voltage V of 6-7 volts at the gate electrode can be usedERATo implement an erase operation on the MFIS transistor. Table 2 shows the voltage bias of the MFIS transistors in memory array 400 during an erase operation.
TABLE 2
As shown in Table 2, erase disturb is avoided in the unselected MFIS transistors because in each case, the gate-to-source voltage (V)GS) Are less than 1/3VERAThis is smaller in design than the polarization switching voltage of state "1".
A read voltage V of 0.0-0.5 volts at the gate electrode can be usedREADAnd a drain voltage V of 0.5-2.0 voltsDDTo implement a read operation. Table 3 shows the data in the memory array 400 during a read operationThe voltage bias of the MFIS transistor.
TABLE 3
As shown in table 3, MFIS transistors that are not on the same wordline (i.e., unselected gate electrodes) are provided with a gate voltage of 0.0 volts or less, which results in very low currents being drawn in these transistors.
Fig. 6 a-6 j illustrate an exemplary fabrication process of a memory array 600 according to one embodiment of the invention. Unlike memory array 400, the gate electrodes of the MFIS transistors in memory array 600 are not connected by a network of global gate lines formed below the memory array. In contrast, as shown in vertical cross-section in fig. 6a, an oxide layer 603 (e.g., silicon oxide) and a bottom etch stop layer 604 (e.g., silicon nitride) are sequentially deposited on a planar surface of a semiconductor substrate 601. As shown, the etch stop layer 604 may be patterned and embedded in the oxide layer 603. As shown in vertical cross-section in fig. 6b, alternating layers of silicon oxide layers 605 and silicon nitride layers 606, here numbered silicon oxide layers 605-1, … …, and 605-n, respectively, and silicon nitride layers 606-1, … …, 606-n are then deposited. An array of memory holes 607 (e.g., memory holes 607-1, 607-2, and 607-3) is then etched down through alternating layers of silicon oxide 605 and silicon nitride 606 layers to the etch stop layer 604, as shown in vertical cross-section in fig. 6c (i). Fig. 6c (ii) shows a horizontal cross-section through one of the silicon nitride layers 606, the horizontal cross-section showing the memory holes 607-1 to 607-9 of the memory array 600 at this stage of formation.
A polysilicon layer 609 is then conformally deposited, followed by a thin gate oxide layer 610. The polysilicon 609 may be deposited as amorphous silicon and annealed at 850 c for 2 hours to crystallize. A ferroelectric layer 611 is then deposited (e.g., Si doping)Hf doped with hetero or Zr1-xSixOy、HfxZr1-xOyFerroelectric thin film). The resulting structure (vertical cross-section) is shown in fig. 6 d.
An adhesion/barrier layer of titanium nitride (TiN)612 is then conformally deposited. The memory hole 607 is then filled with a gate electrode material 613, the gate electrode material 613 may be CVD W or n+Polycrystalline silicon. The CMP step removes excess gate oxide material 613 from the top of the memory array 600. The resulting structure (vertical cross-section) is shown in fig. 6 e.
Thereafter, a top isolation layer 615 (e.g., silicon nitride) is provided over the memory array 600. The top isolation layer 615 is then patterned and an etching step creates trenches 614 (e.g., trenches 614-1, 614-2, 614-3, and 614-4) through the top isolation layer 615, TiN layer 612, ferroelectric layer 611, gate oxide layer 610, tunnel polysilicon layer 609, and alternating silicon nitride layers 606 and oxide layers 605. The resulting structure (vertical cross-section) is shown in fig. 6f (i). Fig. 6f (ii) shows a horizontal cross section of memory array 600 through one of nitride layers 606.
An etching step (hot phosphoric acid) is performed to remove the silicon nitride layer 606. During this step, silicon nitride material is removed from the exposed surfaces of the silicon nitride layer 606 in the sidewalls of the trench 614. A further etch step removes the exposed portions of the channel polysilicon 609 and gate oxide 610. Then depositing and annealing a layer n+A polysilicon layer 620. A TiN layer 618 and tungsten 619 are then sequentially deposited to fill the voids left after the silicon nitride removal. Substantially removing excess n from the top of the structure and the sidewalls of the trench 614+Polysilicon, TiN and tungsten materials. These steps are provided in substantially the same manner as discussed above with respect to the vertical and horizontal cross-sections in fig. 4i (i) and 4i (ii), respectively. n is+The recessed portions of the polysilicon layer 620 become the drain and source regions of the MFIS transistor. The TiN layer 618 and the tungsten layer 619 become a source or drain electrode 623. Silicon oxide 622 is then deposited to fill the trenches 614. The CMP step removes excess silicon oxide from the top of the memory array 600. The resulting structures are shown in vertical and horizontal cross-sections in fig. 6g (i) and fig. 6g (ii), respectively.
At one endIn some embodiments, the silicon nitride layer 606 is not completely removed, as discussed above with respect to fig. 4j (i) and 4j (ii). As the etching of the silicon nitride layer 606 begins from the sidewalls of the trenches 614, a strip of silicon nitride is caused to separate and electrically isolate the resulting source or drain terminals on opposite sides of each memory hole. In this way, two vertical 3D FeFET strings are now provided per memory hole, since n is on opposite sides of each silicon nitride layer per memory hole+The polysilicon recess forms a separate drain region or source region. This alternative embodiment is illustrated in the structures shown in vertical and horizontal cross-sections in fig. 6h (i) and 6h (ii), respectively. As shown in fig. 6h (ii), the incomplete removal of the silicon nitride layer 606 leaves the silicon nitride layer 621 providing separate sets 623L and 623R of drain or source electrodes.
A silicon oxide layer 618 is deposited on the top isolation layer 615, and the silicon oxide layer 618 fills any gaps on the memory array 600 and is planarized by a CMP step. Thereafter, the silicon oxide layer 618 is patterned. The etching step creates a via through the silicon oxide layer 618 and the top isolation layer 615 to expose the gate electrode material 613. Metal conductors (e.g., TiN and tungsten plugs) 616 are then provided to fill the vias. The CMP step planarizes the surface of the memory array 600. The resulting structure is shown in vertical cross-section in fig. 6 i. Thereafter, a top global gate (e.g., global gate 617) is provided over silicon oxide layer 618 to electrically connect gate electrode 613 through the conductor-filled via, as shown in fig. 6 j.
Fig. 7 a-7 g illustrate an exemplary fabrication process of a memory array 700 according to one embodiment of the invention. Unlike the MFIS transistors of memory arrays 400 and 600 discussed above, the MFIS transistors of memory array 700 include an additional charge storage layer between the gate oxide layer and the ferroelectric layer.
FIG. 7a shows memory array 700 after (i) a network of global gate lines (e.g., tungsten) including global gate line 702 is formed over a semiconductor substrate 701, which semiconductor substrate 701 may be a semiconductor wafer; and (ii) an oxide layer 703 (e.g., silicon oxide) and a bottom etch stop layer 704 (e.g., n+Polysilicon) is deposited onOn the local gate line; and (iii) depositing a silicon oxide layer 705 and n+Alternating layers of polysilicon 706, here numbered as silicon oxide layers 705-1, … …, and 705-n, and n, respectively+Polysilicon layers 706-1, … …, 706-n. In addition to conducting n+The structure of fig. 7a may be formed using substantially the same steps as those described above with respect to fig. 4a-4 c, except that a polysilicon material is substituted for the silicon nitride in the alternating layers. Using n+Polysilicon is an option for the drain and source electrodes, although n+Polysilicon has a higher resistivity than metal. However, if metals are selected for the drain and source electrodes, then metal replacement steps may be required (e.g., see fig. 4i and 4j for memory array 400 and fig. 6f and 6g for memory array 600).
Rather than creating slots 714 at this point after the MFIS transistors have been substantially formed (see, e.g., fig. 4h (i) and 6f (i)), they create slots 414 of memory array 400 and slots 614 of memory array 600 because no metal replacement step is required. (the metal replacement step accesses the silicon nitride layer through the trenches.) the trenches 714 separating the memory array 700 into portions 708 may then be filled with oxide, as shown in vertical and horizontal cross-sections in fig. 7b (i) and fig. 7b (i).
Then through the silicon oxide layers 705 and n+Alternating layers of polysilicon layer 706 etch memory holes 707 (e.g., memory holes 707-1, 707-2, and 707-3) down to etch stop layer 704, as shown in vertical cross-section in fig. 7c (i). FIG. 7c (ii) shows the passage of n+A horizontal cross-section of one of polysilicon layers 706 showing memory holes 707-1 to 707-9 of memory array 700 at this step of formation.
A polysilicon layer 709 is then conformally deposited, followed by a thin gate oxide layer 710. The polysilicon 709 may be deposited as amorphous silicon and annealed at 850 c for 2 hours to crystallize. A protective layer 708 may then be deposited over the gate oxide layer 710. A spacer etch is then performed to remove any deposited polysilicon and gate oxide from the bottom of the memory hole 707. A CMP step may be performed to remove the material of the protection layer 708, gate oxide 710 and polysilicon layer 709 from the top of the structure. The resulting structure (i.e., memory array 700 at this stage of formation) is shown in vertical cross-section in fig. 7 d.
The protective layer 708 is then removed. Thereafter, a charge trapping layer 733 is conformally deposited. The anisotropic etch then removes the charge trapping material at the bottom of the memory hole 707 to expose the underlying etch stop layer 704. The exposed portions of etch stop layer 704 and portions of oxide layer 703 are removed in successive etching steps to create vias that expose the underlying global gate lines. The resulting structure is shown in vertical cross-section in fig. 7 e.
Then a ferroelectric layer 711 (e.g., Si-doped or Zr-doped Hf) is deposited1-xSixOy、Hf1-xZrxOyFerroelectric thin film). The CMP and bottom etch steps remove excess ferroelectric material from the top of the structure and the bottom of the memory holes 707. An adhesion/barrier layer 712 of titanium nitride (TiN) is then conformally deposited. An etching step then removes the TiN material from portions of the memory holes 707. The memory holes 707 are then filled with a gate electrode material 713, the gate electrode material 713 may be CVD W or n+Polycrystalline silicon. Excess deposited material is then removed from the top of the structure by CMP. The resulting structure (vertical cross-section) is shown in fig. 7 f.
Thereafter, a top isolation layer 715 (e.g., silicon nitride) is provided over the memory array 700. The resulting structure (vertical cross-section) is shown in fig. 7 g.
Fig. 8 a-8 j illustrate an exemplary fabrication process of a memory array 800 according to one embodiment of the invention. Unlike the MFIS transistors of memory arrays 400, 600, and 700 discussed above, the MFIS transistors of memory array 800 have unit cells in which the source and drain lines are made of the same semiconductor material layer.
FIG. 8a shows memory array 800 after (i) a network of global gate lines (e.g., tungsten) including global gate line 802 is formed over a semiconductor substrate 801, which semiconductor substrate 801 may be a semiconductor wafer; and (ii) an oxide layer 803 (e.g., silicon oxide) and a bottom etch stop layer 804 (e.g., n+Polysilicon) is deposited onOn the local gate line; and (iii) depositing alternating layers of silicon oxide layers 805 and silicon nitride layers 806, herein numbered as silicon oxide layers 805-1, … …, and 805-n and silicon nitride layers 806-1, … …, 806-n, respectively. (in fig. 8a, semiconductor substrate 801 and global gate layer 802 are omitted; semiconductor substrate 801 and global gate layer 802 have substantially the same structures and are formed in substantially the same manner as semiconductor substrate 701 and global gate layer 702 discussed above.) the structure of fig. 8a may be formed using substantially the same steps as those described above with respect to fig. 4a-4 c.
Memory holes 807 (e.g., memory holes 407-1, 407-2, and 407-3) are then etched down through alternating layers of silicon oxide layer 805 and silicon nitride layer 806 to etch stop layer 804, as shown in vertical cross-section in fig. 8b (i). Fig. 8b (ii) shows a horizontal cross-section through one of silicon nitride layers 706, which shows memory holes 807-1 to 807-9 of memory array 800 at this formation step.
Thereafter, a silicon nitride recess etch using, for example, hot phosphoric acid is performed to recess the silicon nitride layer 806 from the exposed sidewalls of the memory holes 807, as shown in FIG. 8 c. A polysilicon layer 809 (e.g., p) is then deposited-Type) to fill the recesses created by the silicon nitride recess etch. The anisotropic etch step removes excess polysilicon material from the memory holes 809 (including the sidewalls), exposing the etch stop layer 804. Excess polysilicon material may also be removed from the top oxide layer 805-n. The resulting structure is shown in fig. 8d (i). Fig. 8d (ii) shows a horizontal cross section through one of the silicon nitride layers 806. The polysilicon 709 may be deposited as amorphous silicon and annealed at 850 c for 2 hours to crystallize.
A thin gate oxide layer 810 and a ferroelectric layer 811 (e.g., Si-doped or Zr-doped Hf) are then formed1-xSixOy、Hf1- xZrxOyFerroelectric thin film) is conformally deposited into the memory holes 807. The CMP step removes excess gate oxide and ferroelectric material from the top of the structure. An adhesion/barrier layer of titanium nitride (TiN)812 is then conformally deposited. The resulting structure is shown in fig. 8 e.
The deposition may then be CVD W or n+A gate electrode material 813 of polysilicon fills the remaining memory hole 807. The excess deposited gate electrode and TiN material are then removed from the top of the memory array 800 by CMP. The resulting structure (vertical cross-section) is shown in fig. 8 f. Thereafter, a top spacer layer 815 (e.g., silicon nitride) is provided over the memory array 800. The grooves 814 are then cut. The resulting structure is shown in fig. 8g (i). The horizontal structure of one of the polysilicon layers through the silicon nitride channel is shown in fig. 8g (ii).
The hot phosphoric acid etch causes silicon nitride layer 806 to recess from the sidewalls of trench 814, as shown in fig. 8h (i). The horizontal structure of one of the polysilicon layers through the silicon nitride channel is shown in fig. 8g (ii). Thereafter, n is conformally deposited by diffusion+Polysilicon layer 818 lines the layers from the recesses of recessed silicon nitride layer 805. The annealing step provides crystallization and activates the dopants if necessary. Thereafter, the remaining layers of the recess are lined with the adhesive layer 817 and filled with the tungsten layer 819. Excess TiN, tungsten, and n are then removed from the sidewalls and bottom of trench 814 and from the top of the structure+A polysilicon material. The recess in each slot is designated as either a source region 821 or a drain region 822, where adjacent slots are assigned opposite types. The resulting structure is shown in fig. 8i (i). The horizontal structure through one of the recess layers is shown in fig. 8i (ii). A portion 820 of the structure of fig. 8i (i) is enlarged in fig. 8i (iii).
The trenches 814 are then filled with an insulator 825 (e.g., silicon oxide), the insulator 825 also providing a top gap fill layer. After planarization using CMP, gate line contact 826 passes through top gap fill layer 825 and top isolation layer 813. One or more layers of conductors ("gate lines") 827 may be provided to electrically connect to gate line contacts 826. The resulting structure is shown in fig. 8 j.
The above detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the invention. For example, with respect to fig. 7a to 7g, the positions of the ferroelectric layer 711 and the charge trap layer 733 may be interchanged, and an additional barrier oxide layer may be interposed between the titanium nitride layer 712 and the ferroelectric layer 711. The invention is illustrated in the accompanying drawings.