Synchronization system and method of dual-redundancy data bus
阅读说明：本技术 一种双余度数据总线的同步系统及方法 (Synchronization system and method of dual-redundancy data bus ) 是由 熊小军 胡博 赵安才 于 2021-08-03 设计创作，主要内容包括：一种双余度数据总线的同步系统,包括,两个同步信号发起单元、两个同步信号接收单元,其中,两个所述同步信号发起单元之间互为余度关系；两个所述同步信号接收单元之间互为余度关系；两个所述同步信号发起单元分别生成同步脉冲信号并进行同步,将同步后的主、备同步脉冲信号发送给所述同步信号接收单元；两个所述同步信号接收单元,跟随所述同步信号发起单元生成的同步信号；两个所述同步信号发起单元和两个所述同步信号接收单元,根据所述同步信号的相位,确定本地数据的发送时机和接收时机。本发明还提供一种双余度数据总线的同步方法,能够稳定无间断地在飞控计算机的不同的异步工作的扩展板卡之间实现时间同步,达到同步数据传输的目的,并根据各个扩展板卡的实际工作需求简化了系统架构,从而使不同的异步工作的板卡之间的同步数据传输成为一项简单易行的工作。(A synchronous system of a dual-redundancy data bus comprises two synchronous signal initiating units and two synchronous signal receiving units, wherein the two synchronous signal initiating units are in a redundancy relation with each other; the two synchronous signal receiving units are in a redundancy relation with each other; the two synchronous signal initiating units respectively generate synchronous pulse signals and synchronize the synchronous pulse signals, and the synchronized main and standby synchronous pulse signals are sent to the synchronous signal receiving unit; the two synchronous signal receiving units follow the synchronous signals generated by the synchronous signal initiating unit; and the two synchronous signal initiating units and the two synchronous signal receiving units determine the sending time and the receiving time of the local data according to the phases of the synchronous signals. The invention also provides a synchronization method of the dual-redundancy data bus, which can stably and uninterruptedly realize time synchronization among different asynchronously-working expansion board cards of the flight control computer to achieve the purpose of synchronous data transmission, and simplifies the system architecture according to the actual working requirements of each expansion board card, thereby enabling the synchronous data transmission among the different asynchronously-working board cards to be a simple and easy work.)
1. A synchronous system of a dual-redundancy data bus is characterized by comprising two synchronous signal initiating units and two synchronous signal receiving units, wherein,
the two synchronous signal initiating units are in a redundancy relation with each other;
the two synchronous signal receiving units are in a redundancy relation with each other;
the two synchronous signal initiating units respectively generate synchronous pulse signals and synchronize the synchronous pulse signals, and the synchronized main and standby synchronous pulse signals are sent to the synchronous signal receiving unit;
the two synchronous signal receiving units follow the synchronous pulse signal generated by the synchronous signal initiating unit;
and the two synchronous signal initiating units and the two synchronous signal receiving units determine the sending time and the receiving time of the local data according to the phase of the synchronous pulse signal.
2. The dual-redundancy data bus synchronization system according to claim 1, wherein two synchronization signal initiating units are capable of establishing a synchronization relationship through automatic contention at startup, and generating a local synchronization pulse signal according to the generation states of the local and remote synchronization pulse signals, or detecting and following the remote synchronization pulse signal during standby time, or independently generating the local synchronization pulse signal after the standby time is exhausted and detecting the response condition of the remote triggered after the local synchronization pulse signal is generated; establishing a synchronous relation between the main station and the standby station by the mechanism and determining the main station and the standby station; if the synchronization is failed to be established, either the master or the slave can independently generate a synchronization pulse signal;
the synchronization pulse signal generated by the synchronization signal initiating unit in the master position can interrupt the synchronization pulse signal generated by the synchronization signal initiating unit in the following position.
3. The synchronization system of dual redundancy data buses according to claim 2, wherein when the synchronization signal initiating unit in the master position works normally, the synchronization signal initiating unit in the following position performs phase detection on the synchronization pulse signal of the synchronization signal initiating unit in the master position, and selects a timing to follow the synchronization pulse signal initiated by the synchronization signal initiating unit in the master position.
4. The system according to claim 1, wherein two of said synchronization signal initiators perform phase detection with each other, and perform redundancy management if one of the phase detections times out.
5. The dual redundancy data bus synchronization system of claim 1, wherein the synchronization signal initiating unit comprises a phase detection module and a first pulse initiating module, wherein,
the phase detection module is used for carrying out phase detection on the input synchronous pulse signal, and when the input synchronous pulse signal is detected to have the initiating pulse overtime, redundancy management is carried out;
and the pulse initiating module receives the control of the phase detection module and generates a synchronous pulse signal.
6. The dual redundancy data bus synchronization system of claim 5, wherein the phase detection module comprises a first flip-flop, a second flip-flop, an inverter, and a logic AND gate, wherein,
the clock input end of the first trigger is connected with a system clock signal, and the trigger input end of the first trigger is connected with a synchronous pulse signal; the output end of the first trigger is connected with the trigger input end of the first trigger and the input end of the phase inverter respectively;
the clock input end of the second trigger is connected with a system clock signal, and the output end of the second trigger is connected with one input end of the logic AND gate;
and the output end of the phase inverter is connected with the other input end of the logic AND gate.
7. The dual redundancy data bus synchronization system of claim 5, wherein the pulse initiation module comprises a synchronization logic unit, a counter, and a comparator, wherein,
the input end of the synchronous logic unit is respectively connected with a main/standby unit mark signal and an asynchronous synchronous pulse signal which are input from the outside and a local synchronous pulse signal which is output by the comparator, and the output end of the synchronous logic unit is connected with the input end of the counter and sends a synchronous effective mark signal to the counter;
the counter receives and counts the synchronous effective mark signal from the synchronous logic unit and sends a counting result to the comparator;
and the comparator is used for judging the counting result output by the counter and generating and outputting a local synchronous pulse signal.
8. A dual-redundancy flight control computer comprising a motherboard and an expansion daughter board, wherein the expansion daughter board employs the dual-redundancy data bus synchronization system of claims 1 to 7.
9. A method for synchronizing dual-redundancy data bus comprises the following steps,
the synchronous signal initiating unit generates synchronous pulse signals, synchronizes the synchronous signal initiating units and determines the main-standby relation of the synchronous signal initiating units;
determining an output synchronous pulse signal according to the main-standby relation;
and carrying out phase detection on the synchronous pulse signals, and carrying out redundancy management according to a detection result.
10. The method for synchronizing a dual redundancy data bus according to claim 9,
the method comprises the steps that a synchronous signal initiating unit generates synchronous pulse signals, the synchronous signal initiating units are synchronized, and the main-standby relation of the synchronous signal initiating units is determined;
the step of carrying out phase detection on the synchronous pulse signals and carrying out redundancy management according to the detection result also comprises two synchronous signal initiating units, wherein the two synchronous signal initiating units carry out phase detection on the synchronous pulse signals, and if one phase detection is overtime, the redundancy management is carried out.
Technical Field
The present invention relates to computer bus communication technology, and is especially one kind of double-redundancy data bus synchronizing system and method.
Background
Most of the existing flight control computer systems adopt a multi-redundancy flight control computer, which generally adopts a combined architecture of a motherboard and expansion board cards (expansion units), and adopts a high-speed digital bus to exchange data among the expansion board cards. Due to the fact that the expansion board cards work cooperatively, the problem that how to transmit data among different expansion board cards needs to be solved.
Because each expansion board card forming the flight control computer usually works asynchronously, a direct system architecture adopts an asynchronous transmission mechanism of 'request-response-data transmission' to complete data transmission. However, because the amount of data to be transmitted is large and the specific length is uncertain, when a plurality of expansion boards send data transmission requests at the same time, the asynchronous transmission mechanism cannot properly coordinate the sending and receiving work, so that the overall coordination capability of the asynchronous system is poor, and data transmission can cause transmission jam or even packet loss due to request congestion.
If synchronous transmission is adopted, how to synchronize different expansion board cards which work asynchronously is a difficult point of design, and if forced alignment is adopted, data loss is easily caused by forced transmission interruption due to an undetermined working state of an aligned party.
In addition, due to the fact that the functions of the expansion board cards forming the data transmission stream of the redundancy flight control computer are different, the function positioning of the expansion board cards in synchronization is different, the existence form of the expansion board cards is required to be properly understood, the synchronization process is simplified according to the actual needs of the system, the redundancy management function of the expansion board cards is prevented from being processed indiscriminately, and further the complexity of the system is prevented from being increased due to over-design.
Disclosure of Invention
In order to solve the defects in the prior art, an object of the present invention is to provide a synchronous system and method for dual-redundancy data bus, which can stably and uninterruptedly implement time synchronization between different asynchronously-operating expansion boards, and appropriately simplify the system architecture according to the actual working requirements of each expansion board, so as to enable synchronous data transmission between different asynchronously-operating expansion boards.
In order to achieve the above object, the present invention provides a synchronization system for dual redundancy data bus, comprising two synchronization signal initiating units and two synchronization signal receiving units, wherein,
the two synchronous signal initiating units are in a redundancy relation with each other;
the two synchronous signal receiving units are in a redundancy relation with each other;
the two synchronous signal initiating units respectively generate synchronous pulse signals and synchronize the synchronous pulse signals, and the synchronized main and standby synchronous pulse signals are sent to the synchronous signal receiving unit;
the two synchronous signal receiving units follow the synchronous pulse signal generated by the synchronous signal initiating unit;
and the two synchronous signal initiating units and the two synchronous signal receiving units determine the sending time and the receiving time of the local data according to the phase of the synchronous pulse signal.
Furthermore, the two synchronization signal initiating units can establish a synchronization relationship through automatic competition when starting, and generate a local synchronization pulse signal according to the generation states of the local and remote synchronization pulse signals, or detect and generate the local synchronization pulse signal along with the remote synchronization pulse signal within the standby time, or independently generate the local synchronization pulse signal after the standby time is exhausted and detect the response condition of the remote end triggered after the local synchronization pulse signal is generated; establishing a synchronous relation between the main station and the standby station by the mechanism and determining the main station and the standby station; if the synchronization is failed to be established, either the master or the slave can independently generate a synchronization pulse signal;
the synchronization pulse signal generated by the synchronization signal initiating unit in the master position can interrupt the synchronization pulse signal generated by the synchronization signal initiating unit in the following position.
Further, when the synchronization signal initiating unit in the main control position works normally, the synchronization signal initiating unit in the following position performs phase detection on the synchronization pulse signal of the synchronization signal initiating unit in the main control position, and selects a timing to follow the synchronization pulse signal initiated by the synchronization signal initiating unit in the main control position.
Furthermore, the two synchronization signal initiating units perform phase detection with each other, and perform redundancy management if one of the phase detections is overtime.
Further, the synchronization signal initiating unit comprises a phase detection module and a first pulse initiating module, wherein,
the phase detection module is used for carrying out phase detection on the input synchronous pulse signal, and when the input synchronous pulse signal is detected to have the initiating pulse overtime, redundancy management is carried out;
and the pulse initiating module receives the control of the phase detection module and generates a synchronous pulse signal.
Further, the phase detection module comprises a first flip-flop, a second flip-flop, an inverter, and a logic and gate, wherein,
the clock input end of the first trigger is connected with a system clock signal, and the trigger input end of the first trigger is connected with a synchronous pulse signal; the output end of the first trigger is connected with the trigger input end of the first trigger and the input end of the phase inverter respectively;
the clock input end of the second trigger is connected with a system clock signal, and the output end of the second trigger is connected with one input end of the logic AND gate;
and the output end of the phase inverter is connected with the other input end of the logic AND gate.
Further, the pulse initiation module comprises a synchronization logic unit, a counter, and a comparator, wherein,
the input end of the synchronous logic unit is respectively connected with a main/standby unit mark signal and an asynchronous synchronous pulse signal which are input from the outside and a local synchronous pulse signal which is output by the comparator, and the output end of the synchronous logic unit is connected with the input end of the counter and sends a synchronous effective mark signal to the counter;
the counter receives and counts the synchronous effective mark signal from the synchronous logic unit and sends a counting result to the comparator;
and the comparator is used for judging the counting result output by the counter and generating and outputting a local synchronous pulse signal.
In order to achieve the above object, the present invention further provides a dual-redundancy flight control computer, which includes a motherboard and an expansion daughter board card, and is characterized in that the expansion daughter board card adopts the dual-redundancy data bus synchronization system.
In order to achieve the above object, the present invention further provides a synchronization method for dual-redundancy data bus, comprising the following steps:
the synchronous signal initiating unit generates synchronous pulse signals, synchronizes the synchronous signal initiating units and determines the main-standby relation of the synchronous signal initiating units;
determining an output synchronous pulse signal according to the main-standby relation;
and carrying out phase detection on the synchronous pulse signals, and carrying out redundancy management according to a detection result.
Furthermore, the step of generating the synchronization pulse signal by the synchronization signal initiating unit, synchronizing the synchronization signal initiating units and determining the main-standby relationship of the synchronization signal initiating units further comprises the step of determining that one of the synchronization signal initiating units is in a main control position and the other synchronization signal initiating unit is in a following position;
the step of carrying out phase detection on the synchronous pulse signals and carrying out redundancy management according to the detection result also comprises two synchronous signal initiating units, wherein the two synchronous signal initiating units carry out phase detection on the synchronous pulse signals, and if one phase detection is overtime, the redundancy management is carried out.
Compared with an asynchronous transmission mechanism, the synchronous system and the synchronous method of the dual-redundancy data bus have the defects, can stably and uninterruptedly realize time synchronization among different asynchronously-working expansion board cards to achieve the aim of synchronous data transmission, and simplify the system architecture according to the actual working requirements of each expansion board card, so that the synchronous data transmission among the different asynchronously-working board cards becomes simple and easy work.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a dual redundancy data bus synchronization system according to the present invention;
FIG. 2 is a schematic diagram of a synchronization signal generating unit according to the present invention;
FIG. 3 is a schematic diagram of a phase detection module according to the present invention;
FIG. 4 is a schematic diagram of a pulse initiation module according to the present invention;
FIG. 5 is a flow chart of a dual redundancy data bus synchronization method according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1
Fig. 1 is a schematic structural diagram of a dual-redundancy data bus synchronization system according to the present invention, and as shown in fig. 1, the dual-redundancy data bus synchronization system of the present invention includes a first synchronization signal generating unit 10, a second synchronization signal generating unit 20, a first synchronization signal receiving unit 30, and a second synchronization signal receiving unit 40, wherein,
the first synchronization signal generating unit 10 and the second synchronization signal generating unit 20 are in a redundancy relationship;
the first synchronous signal generating unit 10 and the second synchronous signal generating unit 20 respectively generate a main synchronous signal and a standby synchronous signal and establish a synchronous relation;
the first synchronization signal receiving unit 30 and the second synchronization signal receiving unit 40 are in a redundancy relationship;
the first and second synchronization signal receiving units 30 and 40 receive the synchronization signals from the first and second synchronization signal generating units 10 and 20, respectively, and determine the time when data is locally transmitted and received.
In the embodiment of the present invention, the first synchronization signal generating unit 10 is in a main control position, the second synchronization signal generating unit 20 is in a following position, and the synchronization signal output by the first synchronization signal generating unit 10 can interrupt the synchronization signal output by the second synchronization signal generating unit 20.
In the embodiment of the present invention, the first synchronization signal generating unit 10 and the second synchronization signal generating unit 20 perform phase detection with each other, the first synchronization signal generating unit 10 detects whether the second synchronization signal generating unit 20 has an initiation pulse timeout, the second synchronization signal generating unit 20 detects whether the first synchronization signal generating unit 10 has an initiation pulse timeout, and if the phase detection is timeout, redundancy management is performed.
In the embodiment of the present invention, during normal operation, the first synchronization signal generating unit 10 autonomously initiates a synchronization signal, the second synchronization signal generating unit 20 is in a following position, and when the first synchronization signal generating unit 10 normally operates, the timing follows the synchronization signal initiated by the first synchronization signal generating unit 10 by performing phase detection on the synchronization signal sent by the first synchronization signal generating unit 10. If the phase detection of the first synchronous signal generation unit 10 is overtime and the synchronous signal of the second synchronous signal generation unit 20 is failed, the first synchronous signal generation unit 10 continues to normally operate in the master control position; if the phase detection of the second synchronization signal generation unit 20 is overtime, and the synchronization signal of the first synchronization signal generation unit 10 fails, the second synchronization signal generation unit 20 switches from the following status to the main control status, and continues to operate with the main control status.
Fig. 2 is a schematic structural diagram of a synchronization signal generation unit according to the present invention, and as shown in fig. 2, the first synchronization signal generation unit 10 includes a first phase detection module 11 and a first pulse initiation module 12. The second synchronization signal generating unit 20 includes a second phase detecting module 21 and a second pulse initiating module 22.
In the embodiment of the present invention, the first phase detection module 11 is connected to the second pulse initiation module 22, and performs phase detection on the synchronization signal output by the second pulse initiation module 22, and detects whether the second synchronization signal generation unit 20 has an initiation pulse timeout; the second phase detection module 21 is connected to the first pulse initiation module 12, and performs phase detection on the synchronization signal output by the first pulse initiation module 12 to detect whether the first synchronization signal generation unit 10 has an initiation pulse timeout; and if the phase detection is overtime, performing redundancy management.
Fig. 3 is a schematic structural diagram of a phase detection module according to the present invention, and as shown in fig. 3, the phase detection module (11 or 21) of the present invention is a signal transition detection circuit driven by a system clock, and is capable of effectively identifying the phase of a periodic synchronization signal, and when the phase detection module detects an event of generating a synchronization signal, it will trigger a pulse initiation module to complete local generation of the synchronization signal. The phase detection module of the present invention comprises a first flip-flop 301, a second flip-flop 302, an inverter 303, and a logic and gate 304, wherein,
a first flip-flop 301, having a clock input terminal connected to a system clock signal and a trigger input terminal connected to a synchronization signal output terminal of the pulse initiation module; the output terminal of the second flip-flop is connected to the trigger input terminal of the second flip-flop 302 and the input terminal of the inverter 303.
A second flip-flop 302 has a clock input coupled to the system clock signal and an output coupled to one input of a logic and gate 304.
The output of inverter 303 is connected to the other input of logic and gate 304.
The output of the logic and gate 304 is connected to the burst initiator.
Fig. 4 is a schematic structural diagram of a pulse initiation module according to the present invention, as shown in fig. 4, the pulse initiation module (12 or 22) of the present invention,
comprising a synchronization logic unit 401, a counter 402, and a comparator 403, wherein,
the input end of the synchronous logic unit 401 is connected to the main/standby unit flag signal and the asynchronous synchronous signal from the external input, and the local synchronous signal output by the comparator 403, and the output end is connected to the input end of the counter 402, and sends the synchronous valid flag signal to the counter 402.
And a counter 402 that receives and counts the synchronization valid flag signal from the synchronization logic unit 401, and sends the count result to the comparator 403.
And a comparator 403 for determining a count result output from the counter 402 and generating a local synchronization signal output.
In the embodiment of the invention, the main/standby unit mark signal is used as external input to indicate whether the local main synchronous signal generation unit or the standby synchronous signal generation unit is a constant logic level.
The synchronous logic unit 401 can stably and reliably detect the generation of the externally input asynchronous synchronous signal input.
In the embodiment of the present invention, when the local master synchronization signal generation unit mode is used, the counter 402 and the comparator 403 are used to generate a local synchronization signal with a fixed period (when the comparator 403 determines that the counter 402 counts one bus cycle, the local master synchronization signal is normally reset), and the local master synchronization signal is used to normally reset. And simultaneously detecting whether the externally input standby synchronous signal is overtime, and if so, indicating that the standby board has a fault. When the local is in a standby synchronous signal generation unit mode, the local counter follows an externally input asynchronous synchronous signal under the normal condition, when the external synchronous signal is interrupted, the following mode is exited by using local monitoring timeout reset (when the comparator judges that the counter counts the timeout duration), and the local synchronous signal is generated forcibly, so that the redundancy management is finished.
The pulse initiating module is controlled by the synchronous logic, when the synchronous logic analyzes to the synchronous time, the counter and the comparator at the rear end of the pulse initiating module are triggered to generate a local synchronous signal, and the generated local synchronous signal is synchronous with the synchronous signal input by a far end or independently generates the synchronous signal locally under the condition of no synchronous signal input by the far end.
After power is on, the dual-redundancy data bus synchronization system initiates synchronization work between the first synchronization signal generation unit 10 and the second synchronization signal generation unit 20, and after the synchronization is successful, the main and standby two paths of bus synchronization signals with time alignment can be obtained, and then the main and standby two paths of synchronization signals are transmitted to the first synchronization signal receiving unit 30 and the second synchronization signal receiving unit 40, so that the construction of the synchronization signals of the dual-redundancy data bus is completed. Based on the two paths of synchronous signals, the first synchronous signal generating unit 10 and the second synchronous signal generating unit 20 which complete synchronization and the first synchronous signal receiving unit 30 and the second synchronous signal receiving unit 40 divide time slices of data transmission, and complete data transmission and reception in appointed time slices.
Example 2
The invention also provides a dual-redundancy flight control computer which adopts a system architecture of a mother board and an expansion daughter board card, wherein the expansion daughter board card comprises a main power supply board, a first synchronous signal initiating board, a second synchronous signal initiating board, a first synchronous signal receiving board and a second synchronous signal receiving board. The first synchronization signal initiation board, the second synchronization signal initiation board, the first synchronization signal reception board, and the second synchronization signal reception board respectively correspond to the first synchronization signal generation unit 10, the second synchronization signal generation unit 20, the first synchronization signal reception unit 30, and the second synchronization signal reception unit 40 in embodiment 1, and form a dual-redundancy data bus synchronization system. The first synchronous signal initiating board and the second synchronous signal initiating board are in a redundancy relationship with each other, and the first synchronous signal receiving board and the second synchronous signal receiving board are in a redundancy relationship with each other. The work positions in the system are different, and high-speed digital buses are used for connecting and exchanging data. In order to avoid the existence of a single-point structure, a data bus of the dual-redundancy flight control computer adopts a dual-redundancy framework.
In the embodiment of the invention, data transmission only occurs between the first synchronous signal initiating board and the second synchronous signal initiating board and between the first synchronous signal receiving board and the second synchronous signal receiving board, data exchange does not exist between the first synchronous signal initiating board and the second synchronous signal initiating board, and data exchange does not exist between the first synchronous signal receiving board and the second synchronous signal receiving board. All generated data transmission is carried out under the mark of the synchronous signal, specifically, a first synchronous signal initiating board and a second synchronous signal initiating board are initiating units of the synchronous signal, and have the function of generating the synchronous signal and respectively generate a main synchronous signal and a standby synchronous signal. The first synchronous signal receiving board and the second synchronous signal receiving board are not initiating units of synchronous signals and are receivers of the synchronous signals, and the time for locally sending and receiving data is determined according to the synchronous signals sent by the first synchronous signal initiating board and the second synchronous signal initiating board.
In the normal operation process of the dual-redundancy flight control computer, the first synchronization signal initiating board is in a master control position and autonomously initiates synchronization signals. The second synchronous signal initiating board is in a following position, and under the condition that the first synchronous signal initiating board works normally, the synchronous signal initiated by the first synchronous signal initiating board is followed at a selected time through carrying out phase detection on the synchronous signal initiated by the first synchronous signal initiating board.
Example 3
Fig. 5 is a flowchart of a dual-redundancy data bus synchronization method according to the present invention, and the dual-redundancy data bus synchronization method of the present invention will be described in detail with reference to fig. 5.
In the embodiment of the present invention, for convenience of description, the first synchronization signal initiating unit 10 or the second synchronization signal initiating unit 20 is referred to as a local synchronization signal initiating unit, and the other synchronization signal initiating unit (the second synchronization signal initiating unit 20 or the first synchronization signal initiating unit 10) is referred to as a remote synchronization signal initiating unit.
Firstly, in step 501, the system is powered on, the local synchronization signal initiating unit receives the synchronization pulse signal of the remote synchronization signal initiating unit, and judges whether the synchronization pulse signal is received, if yes, the step 503 is skipped, otherwise, the next step is performed.
In step 502, it is determined whether the time for the local synchronization signal initiating unit to receive the synchronization pulse signal exceeds a predetermined time, if yes, the next step is performed, otherwise, the step 501 is returned to continue receiving the synchronization pulse signal.
In step 503, the local synchronization signal initiation unit generates a local synchronization pulse signal.
In the steps 501-503 of the embodiment of the present invention, after the system starts to operate, the local synchronization signal initiation unit first waits for a certain time (T), waits for the remote synchronization signal initiation unit to transmit the synchronization pulse signal, and if the synchronization pulse signal of the remote synchronization signal initiation unit arrives within the time T, the local synchronization signal initiation unit generates the standby synchronization pulse signal; if the synchronization pulse signal of the remote synchronization signal initiating unit is not received after T, the local synchronization signal initiating unit generates a local synchronization pulse signal.
In step 504, it is continuously detected whether the far-end synchronization signal initiating unit has the arrival of the synchronization pulse signal, if not, the next step is entered, and if so, the step 507 is skipped.
At step 505, a predetermined time period is waited for.
In step 504 and 505 of the embodiment of the present invention, the local synchronization signal initiating unit continues to detect whether a synchronization pulse signal arrives at the remote synchronization signal initiating unit in the process of generating the local synchronization pulse signal, where the arriving remote synchronization pulse signal is synchronized with the locally generated synchronization signal. If not, locally generating a local synchronization pulse signal and then waiting for 10 clock cycles, if the arrival of a far-end synchronization signal is not detected in the process, judging that the synchronization fails due to the far-end fault, and locally and independently generating a synchronization pulse.
In step 506, it is determined whether the generated local synchronization pulse signal triggers the remote synchronization signal initiating unit to generate a synchronization pulse signal, if so, the next step is entered, otherwise, the synchronization fails, and the local synchronization signal initiating unit operates independently.
In the embodiment of the present invention, a local synchronization signal initiating unit first detects whether a remote synchronization signal can be received within a waiting time, and if not, generates a local synchronization signal; continuously detecting whether the remote synchronizing signal can be received while generating the local synchronizing signal, wherein if the remote synchronizing signal can be received, the local synchronizing signal and the remote synchronizing signal are synchronous at the moment; the time for locally generating the synchronization signal lasts for 10 clock cycles, and whether the local synchronization signal can trigger the remote synchronization signal initiating unit to generate the synchronization signal is continuously checked during the period, if so, the local synchronization signal and the remote synchronization signal are synchronous, and if not, the remote fault is considered to cause synchronization failure. All three cases either build up synchronization of the local synchronization pulse signal with the remote synchronization pulse signal or generate a separate local synchronization pulse signal.
In step 507, the local synchronization signal initiating unit and the remote synchronization signal initiating unit are synchronized, and the master synchronization signal initiating unit and the slave synchronization signal initiating unit are confirmed.
In the embodiment of the invention, a local synchronous signal initiating unit sets a main state and a standby state for a locally generated synchronous signal according to the attribute of a locally generated main synchronous pulse signal or the attribute of a locally generated standby synchronous pulse signal, a main synchronous pulse signal generating unit independently generates a synchronous pulse signal, and a standby synchronous pulse signal generating unit generates the synchronous pulse signal. If the synchronization fails, the local self-generates the synchronization pulse signal, and the local is set to the master state.
In the embodiment of the invention, in the normal operation process of the main synchronization pulse signal generating unit and the standby synchronization pulse signal generating unit, the main synchronization pulse signal generating unit is in a main control position, and the standby synchronization pulse signal generating unit is in a following position, namely, the synchronization signal of the main synchronization pulse signal generating unit can interrupt the synchronization signal of the standby synchronization pulse signal generating unit, but the synchronization signal of the standby synchronization pulse signal generating unit cannot interrupt the synchronization signal of the main synchronization pulse signal generating unit.
In the embodiment of the invention, the operation mode of the fault process of the main synchronization pulse signal generation unit and the standby synchronization pulse signal generation unit is that the main synchronization pulse signal generation unit and the standby synchronization pulse signal generation unit which normally operate actively perform phase detection, the main synchronization pulse signal generation unit detects whether the standby synchronization pulse signal generation unit has initiating pulse overtime, the standby synchronization pulse signal generation unit detects whether the main synchronization pulse signal generation unit has initiating pulse overtime, and if the phase detection is overtime, redundancy switching is required. In this case, if the phase detection of the primary synchronization pulse signal generation unit is overtime, which indicates that the synchronization signal of the standby synchronization pulse signal generation unit is failed, the primary synchronization pulse signal generation unit continues to operate normally in the primary control position. If the phase detection of the standby synchronization pulse signal generation unit is overtime, which indicates that the synchronization signal of the main synchronization pulse signal generation unit is in fault, the standby synchronization pulse signal generation unit is switched to the main control position from the following position and continues to operate with the main control position.
In the embodiment of the invention, the local synchronizing signal initiating unit and the remote synchronizing signal initiating unit are synchronized, and after the main synchronizing signal initiating unit and the standby synchronizing signal initiating unit are confirmed, the main and standby two paths of bus synchronizing signals aligned in time can be obtained, and then the main and standby two paths of synchronizing signals are transmitted to the synchronizing signal receiving unit, so that the construction of the synchronizing signal of the high-speed data bus of the dual-redundancy flight control computer is completed. Based on the two paths of synchronous signals, the synchronous signal initiating unit and the synchronous signal receiving unit which finish the synchronization divide the time segment of data transmission, and finish the sending and receiving of data on the appointed time segment.
The invention relates to a dual-redundancy data bus synchronization system and a method, aiming at the defects of an asynchronous transmission mechanism, a data transmission method for synchronous data transmission is adopted, and the premise of synchronous data transmission is that time synchronization is realized among a plurality of different asynchronously-working board cards.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.