阅读说明：本技术 一种并行总线抗干扰的数字滤波方法 (Anti-interference digital filtering method for parallel bus ) 是由 张涛 刘志江 唐俊 于 2021-07-27 设计创作，主要内容包括：本发明涉及一种并行总线抗干扰的数字滤波方法,包含以下步骤：S1：利用FPGA或CPLD的总线采样时钟采样干扰信号,并在测试引脚上输出该干扰信号；S2：根据干扰信号宽度和采样时钟周期确定滤波位数；S3：对所述干扰信号进行滤波处理。本发明提供的数字滤波方法能够很好地滤除一些信号毛刺干扰,可提高总线的准确性和可靠性,同时并不会降低总线的速率；相比于在硬件上进行布局的改进,这种方法简单灵活,只需要在FPGA或CPLD的代码上进行优化就可以很好地解决问题；针对不同的干扰强度,可以灵活调整滤波器的宽度,提高时序的可靠性；并行总线易受干扰,可以灵活选择对特定信号做滤波。(The invention relates to an anti-interference digital filtering method for a parallel bus, which comprises the following steps: s1: sampling an interference signal by using a bus sampling clock of the FPGA or the CPLD, and outputting the interference signal on a test pin; s2: determining the filtering digit according to the width of the interference signal and the sampling clock period; s3: and carrying out filtering processing on the interference signal. The digital filtering method provided by the invention can well filter some signal glitch interferences, can improve the accuracy and reliability of the bus, and can not reduce the speed of the bus; compared with the improvement of layout on hardware, the method is simple and flexible, and can well solve the problem only by optimizing the codes of the FPGA or the CPLD; aiming at different interference intensities, the width of the filter can be flexibly adjusted, and the reliability of a time sequence is improved; the parallel bus is easy to interfere, and filtering of specific signals can be flexibly selected.)

1. An anti-interference digital filtering method for a parallel bus is characterized by comprising the following contents:

sampling an interference signal for an input signal by using a bus sampling clock of the FPGA or the CPLD, and outputting the interference signal on a test pin;

determining the filtering digit according to the width of the interference signal and the sampling clock period;

filtering the interference signal: the signal filtering register stores the input signal of the previous period through a sampling clock, the composition values of the input signal of the previous period and the input signal of the current period stored in the signal filtering register are judged in each clock sampling period, if the composition values are equal high level or low level, the input signal of the current period is considered to be correct and non-interfering, the signal filtering register shifts and outputs the current composition value to the output register, and the input signal of the current period is stored in the signal filtering register; if the component values are not equal, the interference is considered, the input signal of the current period is stored in the signal filtering register, but the output register is maintained unchanged.

2. The digital filtering method of claim 1, wherein the component value refers to a combined signal of the input signal stored by the signal filtering register and the input signal of the current cycle.

3. The digital filtering method of claim 1, wherein the width of the interference signal is determined by an oscilloscope waveform test before sampling the interference signal, and the number of bits of the signal filtering register is determined with reference to a sampling clock period.

4. The digital filtering method of claim 1, wherein the interference signal comprises: a convex interference signal on a low level and a concave interference signal on a high level.

5. The digital filtering method according to claim 4, wherein it is guaranteed for a convex interference signal that the test pin is sampled to a high level of m sampling clock pulse widths;

ensuring that the test pin is sampled to obtain low levels of n sampling clock pulse widths for the concave interference signal; the number of bits of the signal filtering register is equal to the larger value of m and n, and m and n are positive integers.

6. The digital filtering method according to claim 1, wherein the signal filter register shifts and outputs a current component value to the output register if the input signal is at a high level and has no interference signal, and if the component values of the input signal of the current period and the signal filter register are all 1 and equal to the input signal of the previous period, the signal filter register stores the input signal of the current period in the signal filter register; if there is interference signal, that is, if there is concave interference in the high level signal, the composition values of the input signal and the signal filter register in the current period are not all 1, the input signal in the current period is stored in the signal filter register, but the level of the output register is maintained unchanged.

7. The digital filtering method according to claim 1, wherein the signal filter register shifts and outputs the current component value to the output register if the input signal is low and has no interference signal, if the component values of the input signal of the current period and the signal filter register are all 0 and equal to the input signal of the previous period, and the input signal of the current period is saved to the signal filter register, according to the number of the filtering bits; if there is interference signal, that is, convex interference occurs in the low level signal, the composition values of the input signal of the current period and the signal filtering register are not all 0, and the input signal of the current period is stored in the signal filtering register, but the level of the output register is maintained unchanged.

Technical Field

The invention relates to the field of digital filtering, in particular to an anti-interference digital filtering method for a parallel bus.

Background

In an embedded system, there is often a connection between the CPU and Peripheral devices through a parallel bus, such as an ISA (Industry Standard Architecture), a PCI (Peripheral Component Interconnect) bus, or a local bus. The parallel bus often uses FPGA (field programmable gate array) or CPLD (complex programmable logic device) to expand the timing function, and during the process of bus data transmission, the single-ended signal is easy to generate the problem of signal integrity, which is reflected in the occurrence of interference on the address bus or the data bus. The input ends vil (max)/vih (min) of the FPGA/CPLD chip of the CMOS (complementary metal oxide semiconductor) process are all low, and are sensitive to interference, and a phenomenon of data transmission error is easily generated.

If the address signal of the parallel bus is sampled wrongly, the data is likely to be stored to the wrong address; if the data bus samples incorrectly, it is likely that the wrong data will be stored at that address. Similarly, other signals may cause timing errors, resulting in bus failure.

Disclosure of Invention

In order to solve the above problems, the present invention provides an anti-interference digital filtering method for a parallel bus, which specifically includes the following steps: sampling an interference signal by using a bus sampling clock of the FPGA or the CPLD, and outputting the interference signal on a test pin; determining the number of bits of a signal filtering register according to the width of the interference signal and the period of a sampling clock; compiling a filtering code to filter the interference signal; writing a filtering code to filter the interference signal: the signal filtering register stores the input signal of the previous period through a sampling clock, the composition values of the input signal stored by the signal filtering register and the input signal of the current period are judged in each clock sampling period, if the composition values are equal high level or low level, the input signal of the current period is considered to be correct and non-interfering, the signal filtering register shifts and outputs the current composition value to the output register, and the input signal of the current period is stored in the signal filtering register; if the input signal level is not equal to the output signal level, the interference is considered to exist, the input signal of the current period is stored in the signal filtering register, and the output register level is maintained unchanged.

Preferably, the component value refers to a combined signal of the input signal stored by the signal filtering register and the input signal of the current cycle.

Before sampling an interference signal by using a bus sampling clock of an FPGA or a CPLD, determining the width of the interference signal by waveform testing of an oscilloscope, and determining the bit number of a signal filtering register according to the period of the sampling clock.

Preferably, the interference signal includes: a convex interference signal on a low level and a concave interference signal on a high level.

Preferably, the convex interference signal is ensured to be sampled by the test pin to obtain m high levels with sampling clock widths; ensuring that the test pin adopts a low level with n sampling clock widths for the concave interference signal; the number of bits of the signal filtering register is equal to the larger value of m and n, and m and n are positive integers.

Preferably, the signal filter register shifts and outputs the current component value to the output register if the input signal is at a high level and if the input signal is an interference-free signal and if the component values of the input signal and the signal filter register are all 1 and equal to the input signal of the previous period according to the filtering bit number, and the input signal of the current period is stored in the signal filter register; if there is interference signal, that is, if there is concave interference in the high level signal, the composition values of the input signal and the signal filter register are not all 1, the input signal of the current period is saved in the signal filter register, but the output register level is maintained unchanged.

Preferably, the signal filter register shifts and outputs the current component value to the output register if the input signal is at a low level and has no interference signal, and if the component values of the input signal and the signal filter register are all 0, the input signal of the current period is stored in the signal filter register; if there is interference signal, that is, convex interference appears in low level signal, the composition values of input signal and signal filter register are not all 0, then the input signal of current period is stored in signal filter register, but the output register level is maintained unchanged.

The invention has the following beneficial effects:

1. the filtering method provided by the invention can well filter some signal glitch interferences, improve the accuracy and reliability of the bus within the range allowed by the bus timing sequence margin, and simultaneously can not reduce the speed of the bus;

2. compared with the improvement of layout on hardware, the method is simple and flexible, and can well solve the problem only by optimizing the codes of the FPGA/CPLD;

3. aiming at different interference intensities, the width of a signal filtering register can be flexibly adjusted, and the reliability of a time sequence is improved;

4. The parallel bus is easy to interfere, the scheme is applied to a parallel bus interface, but the method is not limited to the parallel bus and can flexibly select to filter a specific signal.

Drawings

FIG. 1 is a flow chart of a filtering method according to the present invention;

fig. 2 is an electrical schematic diagram of a CPLD filter according to an embodiment of the present invention.

Detailed Description

The following describes in detail a digital filtering method for interference resistance of a parallel bus according to the present invention with reference to the accompanying drawings and the detailed description. The advantages and features of the present invention will become more apparent from the following description.

As shown in fig. 1, a flow chart of the digital filtering method of the present invention specifically includes the following steps:

1. through oscilloscope waveform testing and oscilloscope trigger conditions, an oscilloscope is used for capturing interference signals, and a proper oscilloscope model is formulated. When a low level appears on an address line of a high level signal, the low level signal has a width of about 10ns and a convex interference signal having an amplitude of up to 2.3V, and the interference signal is sampled by a bus sampling clock of 50MHz of CPLD (MAX V series, vil (MAX) ═ 0.8V, vih (min) ═ 1.7V). The frequency of the sampling clock is 10 times or more of the frequency of the sampled signal in general engineering, a sampling clock (period 20ns) of 50MHz is used in the embodiment, and the narrowest part of the sampled input signal is 250ns width. The sampling clock samples signals and then outputs the signals on a test pin, and the widest value which can be sampled by the pin is ensured to be a high level with the width of m being 1 sampling clock (20 ns).

2. Through oscilloscope waveform testing, when a high level appears on an address line of a certain low-level signal, the low-level signal has a width of about 5ns and an amplitude of as low as 0.7V, for a concave interference signal in the input signal, the concave interference signal is sampled by a bus sampling clock of 50MHz in a CPLD (such as MAX V series, vil (MAX) ═ 0.8V, vih (min) ═ 1.7V), a very large rate is obtained by sampling the concave interference signal, and then the concave interference signal is output on a test pin, so that the widest value that the pin can sample is the low level with the width of n ═ 1 clock (20 ns).

3. The values of m and n are determined according to different bus sampling clocks, and the signal filtering register bit number fbit is max (m, n) is 1.

4. As shown in fig. 2, a filter code function is added in the CPLD to sample the input signal of the parallel interface, a signal filter register in the CPLD stores the input signal of the previous cycle by a sampling clock, and in each sampling clock cycle, the signal filter register judges the stored input signal of the previous cycle and the current input signal, that is, performs comparison and judgment on the value of the input signal, if the input signal of the previous cycle is equal to the input signal of the current cycle, the current input signal is considered to be correct and non-interfering, the signal filter register shifts and outputs the composition values of the input signal of the previous cycle and the input signal of the current cycle to an output register, and the input signal of the current cycle is stored in the signal filter register; if not, the interference is considered, the input signal of the current period is stored in the signal filtering register, but the level of the output register is maintained unchanged. The input signal of the current period is interfered, but the level of the output register is not changed, which is equivalent to that the interference is filtered.

Since the signal output register holds the correct input signal each time, the signal stored in the output register filters the signal at the output of the register, which must be a correct, non-interfering signal. The filtering digit of the signal filtering register is 1bit, if there is no interference signal, the value of the input signal i _ ab and the signal filtering register sa1 sampled each time is all 1 or all 0 (wherein 1 represents high level, 0 represents low level); if there is an interference signal, i.e., a concave interference occurs in the high level signal or a convex interference occurs in the low level signal, the values of the input signal i _ ab and the signal filtering register sa1 are not all 1 or all 0.

The filtering method provided by the invention can well filter some signal glitch interferences, improve the accuracy and reliability of the bus within the range allowed by the bus timing sequence margin, and simultaneously can not reduce the speed of the bus; compared with the improvement of layout on hardware, the method is simple and flexible, and can well solve the problem only by optimizing the codes of the FPGA/CPLD; aiming at different interference intensities, the width of the filter can be flexibly adjusted, and the reliability of a time sequence is improved; the parallel bus is easy to interfere, the scheme is applied to a parallel bus interface, but the method is not limited to the parallel bus and can flexibly select to filter a specific signal.

To sum up, the filtering method is used for the interlocking product board card, and filtering is performed on some interference signals, which proves that the field requirements can be completely met: the adverse effect of certain interference on the system is effectively avoided, the normal transmission of data is ensured, and the stable operation of the system is ensured.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.