阅读说明：本技术 跨单板菊花链传输结构、master单板、slave单板和系统 (Cross-veneer daisy chain transmission structure, master veneer, slave veneer and system ) 是由 阮建 于 2021-08-03 设计创作，主要内容包括：本发明提供了一种跨单板菊花链传输结构、master单板、slave单板和系统,所述跨单板菊花链传输结构包括采用菊花链方式串联连接的一个master单板和N个slave单板,N≥1,N为整数；其中：所述master单板和所述slave单板、以及所述slave单板之间的时钟线和数据线直接连接；所述master单板和所述slave单板、以及所述slave单板之间的地址线按预设交错方式连接。与现有技术相比,本发明提供的跨单板菊花链传输结构、master单板、slave单板和系统,不仅减少了master单板连接器和驱动器的个数,而且能够显著降低了连接master单板以及slave单板的信号线的物料数量,具备较好的扩充性。(The invention provides a cross-single-board daisy chain transmission structure, a master single board, a slave single board and a system, wherein the cross-single-board daisy chain transmission structure comprises a master single board and N slave single boards which are connected in series in a daisy chain mode, N is not less than 1, and N is an integer; wherein: the master single board is directly connected with the slave single board and the clock line and the data line between the slave single boards; the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode. Compared with the prior art, the cross-veneer daisy chain transmission structure, the master veneer, the slave veneer and the system provided by the invention not only reduce the number of the master veneer connectors and the drivers, but also can obviously reduce the material quantity of the signal lines connecting the master veneer and the slave veneer, and have better expandability.)

1. A cross-single-board daisy chain transmission structure is characterized by comprising a master single board and N slave single boards which are connected in series in a daisy chain mode, wherein N is not less than 1 and is an integer; wherein:

the master single board is connected with the slave single board end to end, and a clock line and a data line between the slave single boards are connected end to end;

the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode.

2. The cross-board daisy chain transmission structure of claim 1, wherein the master board includes a first connector having M first address output pins, and the slave board includes a second connector having M address input pins and M second address output pins; m is not less than N and is an integer;

the address lines between the master single board and the slave single board directly connected with the master single board are connected in a preset staggered mode, and the method comprises the following steps:

the mth first address output pin of the first connector is connected to the 1 st address input pin of the first slave board, and the nth first address output pin of the first connector is connected to the n +1 th address input pin of the first slave board; the first slave single board is the slave single board directly connected with the master single board.

3. The inter-board daisy chain transmission structure of claim 2, wherein the address lines between the slave boards are connected in a preset interleaving manner, including:

the mth address output pin of the second connector of the source slave single board is connected with the 1 st address input pin of the second connector of the terminal slave single board adjacent to the mth address output pin; the nth address output pin of the second connector of the source slave single board is connected to the (n + 1) th address input pin of the second connector of the terminal slave single board; the source slave single board is arranged close to the master single board, and the terminal slave single board is arranged far away from the master single board;

wherein n is more than or equal to 1 and less than M, and n is an integer.

4. The cross-board daisy chain transmission structure according to claim 2, wherein the nth address input pin of the slave board is directly connected to the nth second address output pin thereof.

5. The inter-board daisy chain transmission structure of claim 2, wherein according to a preset addressing rule, each of the first address output pins of the master board is configured to address one slave board; the slave single board is configured to determine whether the master single board communicates with the master single board according to a chip selection signal received by the address input pin corresponding to the first address output pin for addressing the master single board.

6. The cross-board daisy chain transmission structure of claim 5, wherein the preset addressing rules comprise:

the master single board sets the chip selection signal of the nth first address output pin to be 1, and sets the chip selection signals of other first address output pins to be 0;

and each slave single board acquires a chip selection signal from the 1 st address input pin.

7. The inter-board daisy chain transmission structure according to any one of claims 1 to 6, wherein the parameter information of the N slave boards is the same; the cross-single-board daisy chain transmission structure further comprises N-1 signal lines, and the physical information of the N-1 signal lines is the same; the lengths of the N-1 signal lines are the same.

8. A master single board is characterized by being used for a cross-single-board daisy chain transmission structure, wherein the cross-single-board daisy chain transmission structure comprises one master single board and N slave single boards which are connected in series in a daisy chain mode, N is more than or equal to 1, and N is an integer;

the master single board is configured to be directly connected with a clock line and a data line of the slave single board which are directly connected with the master single board, and the address lines are connected according to a preset staggered mode.

9. A slave single board is characterized in that the slave single board is used for a cross-single-board daisy chain transmission structure, the cross-single-board daisy chain transmission structure comprises a master single board and N slave single boards which are connected in series in a daisy chain mode, N is more than or equal to 1, and N is an integer;

the slave single board is configured to be directly connected with the clock line and the data line between the master single board and other slave single boards, and the address lines are connected according to a preset staggered mode.

10. A cross-board daisy chain transmission system, wherein the board daisy chain transmission system comprises a master board, and the cross-board daisy chain transmission structure according to any one of claims 1 to 7 is adopted.

Technical Field

The invention relates to the technical field of data transmission, in particular to a cross-veneer daisy chain transmission structure, a master veneer, a slave veneer and a system.

Background

With the continuous progress of the technology, the functions of the computer tend to be diversified, various Peripheral devices are also becoming more and more new, and in order to facilitate users to enhance the computer performance or expand the computer functions, the motherboard of the computer is generally configured with bus slots such as Accelerated Graphics Port (AGP), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), etc. for users to insert expansion cards such as video cards, sound cards, network cards, etc. In addition, the computer host may also be configured with an expansion interface such as a Firewire (Firewire), a Universal Serial Bus (USB), an IIC Bus and/or an SPI Bus, so that a user can connect external devices such as a hard disk and a printer to realize the interconnection among a plurality of devices.

Currently, in practical applications, there are a large number of functional chips, which use IIC bus or SPI bus as interface to communicate with processors, such as ADC, temperature sensor, digital potentiometer, etc. If applied only inside a single board, it will not generally encounter much problems. However, in practical application, a bus is often used to span a board, and a master board often corresponds to a plurality of slave boards, and the boards often have different distances of several meters. Taking an SPI bus as an example, a master board is usually connected to a plurality of slave boards, where an SPI device providing an SPI serial clock is an SPI master or a master device (master board), and other devices are SPI slaves or slave devices (slave boards). These slave boards are identical and are distinguished by chip select signals. Or an IIC bus plus star topology is used, and a plurality of address lines are added for replacement without chip selection signals. Referring to fig. 1, fig. 1 is a schematic diagram of a conventional star topology in the prior art, and as can be seen from fig. 1, the star topology has the following two problems:

firstly, the number of the required drivers is one to many, the corresponding signal lines and connectors are also one to many, and higher requirements are put on a master single board with a processor, and a plurality of connectors and a plurality of drivers are required to be arranged. Taking the example that 1 master board in fig. 1 is connected with 3 slave boards, the master end needs 3 connectors.

And secondly, the positions of different slave veneers possibly placed are different, and the distances from the master veneer are also different, so that cables need to be configured independently, and the material quantity of the whole machine is increased. Still taking fig. 1 as an example, a star topology structure composed of 1 master board (motherboard) and 3 slave boards (slave boards), as can be seen from fig. 1, one master board needs three buffers to process a group of SPI buses or IIC buses into three groups, and then the three groups of buses are connected to the three slave boards at different positions in the star topology by using three connectors. Because of the different distances, the lengths of the cables are different, which means that three additional items are required in the system. A total of 3 cables (signal lines) of different lengths and a total of 15M are required, 1 2M, 5M and 1 8M, respectively.

Therefore, how to provide a new transmission structure across multiple nodes of a single board, so that the single board and the cable are unified as much as possible to reduce the material amount of the whole machine, is becoming one of the technical problems to be solved by those skilled in the art.

It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a cross-single-board daisy chain transmission structure, a master single board, a slave single board and a system aiming at the defect of material waste of a star topology structure in the prior art, and the aim of reducing the material quantity of the whole machine is achieved by solving the problem of addressing of the slave single board.

In order to achieve the purpose, the invention is realized by the following technical scheme: a cross-veneer daisy chain transmission structure comprises a master veneer and N slave veneers which are connected in series in a daisy chain mode, wherein N is not less than 1 and is an integer; wherein:

the master single board is connected with the slave single board end to end, and a clock line and a data line between the slave single boards are connected end to end;

the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode.

Optionally, the master single board includes a first connector having M first address output pins, and the slave single board includes a second connector having M address input pins and M second address output pins; m is not less than N and is an integer;

the address lines between the master single board and the slave single board directly connected with the master single board are connected in a preset staggered mode, and the method comprises the following steps:

the mth first address output pin of the first connector is connected to the 1 st address input pin of the first slave board, and the nth first address output pin of the first connector is connected to the n +1 th address input pin of the first slave board; the first slave single board is the slave single board directly connected with the master single board.

Optionally, the address lines between the slave boards are connected in a preset staggered manner, including:

the mth address output pin of the second connector of the source slave single board is connected with the 1 st address input pin of the second connector of the terminal slave single board adjacent to the mth address output pin; the nth address output pin of the second connector of the source slave single board is connected to the (n + 1) th address input pin of the second connector of the terminal slave single board; the source slave single board is arranged close to the master single board, and the terminal slave single board is arranged far away from the master single board; wherein n is more than or equal to 1 and less than M, and n is an integer.

Optionally, an nth address input pin of the slave board is directly connected to an nth address output pin of the slave board.

Optionally, according to a preset addressing rule, each first address output pin of the master board is used for addressing one slave board; the slave single board is configured to determine whether the master single board communicates with the master single board according to a chip selection signal received by the address input pin corresponding to the first address output pin for addressing the master single board.

Optionally, the preset addressing rule includes:

the master single board sets the chip selection signal of the nth first address output pin to be 1, and sets the chip selection signals of other first address output pins to be 0;

and each slave single board acquires a chip selection signal from the 1 st address input pin.

Optionally, the parameter information of the N slave boards is the same; the cross-single-board daisy chain transmission structure further comprises N-1 signal lines, and the physical information of the N-1 signal lines is the same; optionally, the lengths of the N-1 signal lines are the same.

In order to achieve the above object, the present invention further provides a master single board, where the master single board is used in a cross-single-board daisy chain transmission structure, the cross-single-board daisy chain transmission structure includes one master single board and N slave single boards connected in series in a daisy chain manner, where N is greater than or equal to 1, and N is an integer;

the master single board is configured to be directly connected with a clock line and a data line of the slave single board which are directly connected with the master single board, and the address lines are connected according to a preset staggered mode.

In order to achieve the above object, the present invention further provides a slave single board, where the slave single board is used in a cross-single-board daisy chain transmission structure, the cross-single-board daisy chain transmission structure includes a master single board and N slave single boards connected in series in a daisy chain manner, where N is greater than or equal to 1, and N is an integer;

the slave single board is configured to be directly connected with the clock line and the data line between the master single board and other slave single boards, and the address lines are connected according to a preset staggered mode.

In order to achieve the above object, the present invention further provides a cross-board daisy chain transmission system, where the single-board daisy chain transmission system includes a master single board, and adopts a cross-board daisy chain transmission structure as described in any one of the above.

Compared with the prior art, the cross-veneer daisy chain transmission structure, the master veneer, the slave veneer and the system provided by the invention have the following beneficial effects:

according to the cross-single-board daisy chain transmission structure provided by the invention, the master single board and the slave single board are directly connected with each other, and a clock line and a data line between the slave single boards are directly connected with each other; the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode. With the configuration, the cross-veneer daisy chain transmission structure provided by the invention can reduce the number of master connectors and drivers, and can connect all slave veneers only by one group of non-bifurcated wires.

Furthermore, the possible long wires of the star topology are avoided, and the long wires are divided into a plurality of uniform short wires.

Furthermore, the address lines between the slave single boards are connected in a preset staggered manner, so that the addressing problem is solved, and the hardware unification of the slave single boards is ensured.

Furthermore, according to the cross-board daisy chain transmission structure provided by the present invention, according to a preset addressing rule, each of the first address output pins of the master board is used for addressing one slave board; the slave single board is configured to determine whether the master single board communicates with the master single board according to a chip selection signal received by the address input pin corresponding to the first address output pin for addressing the master single board. By the configuration, even if the cable and the slave single board are completely unified materials, the master single board can also ensure the communication with the expected slave single board. The addressing problem of daisy chain series connection is solved by the address line staggered connection mode, and the hardware unification of the slave single board is ensured.

Still further, in the cross-board daisy chain transmission structure provided by the present invention, since the cable realizes the transparent transmission function through the connector, the receiving end of the slave board is isolated by the buffer (buffer), and particularly, the IIC extender provides a CS port, which ensures the isolation of part of nodes (slave boards) under the condition of damage. Therefore, even if a certain slave single board (IIC device) fails or is even damaged, the signal reception of other slave single boards will not be affected. Further, the buffer can also play a role in reducing bus capacitance and optimizing signal integrity, and can solve the problem of poor signal integrity caused by overlarge capacitance on a long-distance transmission bus of a plurality of slave single plates, so that the capacitance on the bus is greatly reduced through the isolation of the IIC extender, thereby ensuring the signal integrity of long-distance multi-node topology, and better supporting the signal transmission of long-distance and multi-slave single plates.

The master single board, the slave single board and the system provided by the invention belong to the same inventive concept as the cross-single-board daisy chain transmission structure provided by the invention, so the master single board, the slave single board and the system have at least the same beneficial effects and are not repeated.

Drawings

FIG. 1 is a schematic diagram of a conventional star topology in the prior art;

fig. 2 is a schematic topology diagram of a cross-board daisy chain transmission structure according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a connection principle of address lines of a cross-board daisy chain transmission structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating connection of address lines of a cross-board daisy chain transmission structure according to an embodiment of the present invention;

wherein the reference numerals are as follows:

101. 102, 103-cable.

Detailed Description

In order to make the objects, advantages and features of the present invention clearer, the cross board daisy chain transmission structure, the master board, the slave board and the system proposed by the present invention are further described in detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It should be understood that the drawings are not necessarily to scale, showing the particular construction of the invention, and that illustrative features in the drawings, which are used to illustrate certain principles of the invention, may also be somewhat simplified. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, locations, and configurations, will be determined in part by the particular intended application and use environment. In the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings. These terms, as used herein, are interchangeable where appropriate.

Before specifically introducing the cross-single-board daisy chain transmission structure provided by the present invention, an exploration process of the cross-single-board daisy chain transmission structure provided by the present invention is briefly described. As described above, the star topology structure in the prior art has a problem of material waste, and the inventors of the present application have found, through long-term and intensive research, that for the IIC bus, a daisy chain topology can be adopted, one bus is led out from a master terminal (single board), and it is good to connect each slave terminal (single board). No matter the master single board is arranged between the slave single boards, or the slave single boards are arranged between the slave single boards, cables with equal length can be manufactured more easily, and therefore materials are saved. The slave single board which is farther away from the master single board is placed at the later stage as if the slave single board is placed at the later stage. However, the daisy chain serial connection method has a problem how to implement addressing of the slave board for a long time. Obviously, if the slave boards are different, each slave board configures its own address, which is not problematic. However, if the slave boards are completely unified, they cannot be distinguished. In order to solve the problem, in the process of long-term exploring the solution, the inventor of the present application has also proposed to separate the address line and the clock data line, and to use a star topology structure, so as to solve the addressing problem of the slave board. However, part of the whole topology structure is daisy chain, and part of the topology structure is star, so that not only is the expansibility poor, but also the topology is not ethical. On the basis, after a lot of research and continuous and intensive practice for a long time, the inventor of the present application finally and creatively provides a cross-board daisy chain transmission structure, which not only can save materials, but also can be applied to a plurality of same slave boards. Next, the cross-board daisy chain transmission structure proposed by the present invention will be described.

The embodiment provides a cross-single-board daisy chain transmission structure, which comprises a master single board and N slave single boards which are connected in series in a daisy chain mode, wherein N is not less than 1, and is an integer; wherein:

the master single board and the slave single board are connected end to end (directly) with a clock line and a data line between the slave single boards;

the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode.

Specifically, a cross-board daisy chain transmission structure composed of 1 master board and 3 slave boards is taken as an example to explain the cross-board daisy chain transmission structure provided by the present invention. It should be understood by those skilled in the art that this is only an example, the number of slave boards is not a limitation of the present invention, and in other embodiments, the slave boards may be 4, 5, 10, and so on, which are not listed and exemplified. Referring to fig. 2, fig. 2 is a schematic topology diagram of a cross-board daisy chain transmission structure according to an embodiment of the present invention. In combination with the star topology fig. 1 in the prior art, it can be seen that, in the prior art, one Master board needs three buffers to connect one group of SPI buses or IIC buses into three groups, and then the three groups of buses are connected to three Slave boards at different positions in a star topology by using three connectors. Because the distances are different, the lengths of the cables are different, which means that three materials need to be added in the system; the total length of the signal line is 2m +5m +8m, which is 15m, and can actually cover only a range of 8m in length. As can be seen from fig. 2, if a cross-board structure of externally hanging 3 slave boards on a master board, which is the same as that in fig. 1, is implemented, in the cross-board daisy chain transmission structure provided in the present application, the master board only needs to use one Buffer and a connector, and simultaneously uses cables 101, 102, and 103 with a standard length of 3m, so that three slave boards (actually supported to 3m, 6m, and 9m) with distances of 2m, 5m, and 8m can be covered. Therefore, the cross-veneer daisy chain transmission structure provided by the invention has the advantages of fewer interfaces as much as possible, longer driving distance, capability of unifying the slave veneer and the cable as much as possible, and convenience in management and expansion.

Those skilled in the art can understand that, although the master single board and the slave single board, and the clock line and the data line between the slave single boards are directly connected; the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode. However, in practical implementation, the clock line, the data line and the address line may be integrated into one cable: that is, one cable includes a plurality of signal transmission lines for different purposes. Further, the master single board includes, but is not limited to, a server, a computer and other computer devices, and the slave single board includes, but is not limited to, an ADC, a temperature sensor, a digital potentiometer and the like.

According to the cross-single-board daisy chain transmission structure provided by the invention, the master single board and the slave single board are directly connected with each other, and a clock line and a data line between the slave single boards are directly connected with each other; the master single board, the slave single board and the address lines between the slave single boards are connected in a preset staggered mode. With the configuration, the cross-veneer daisy chain transmission structure provided by the invention can reduce the number of master connectors and drivers, and can connect all slave veneers only by one group of non-bifurcated wires; furthermore, the possible long routing of the star topology is avoided, and the long routing is divided into a plurality of uniform short routing sections; the address lines between the slave single boards are connected in a preset staggered mode, so that the addressing problem is solved, and the hardware unification of the slave single boards is ensured.

Preferably, in a preferred embodiment, the master board includes a first connector having M first address output pins, the slave board includes a second connector having M address input pins and M second address output pins, M ≧ N, M is an integer.

Wherein, the address line between master veneer and the slave veneer directly connected with it is connected according to the preset staggered mode, including:

the mth first address output pin of the first connector is connected to the 1 st address input pin of the first slave board, and the nth first address output pin of the first connector is connected to the n +1 th address input pin of the first slave board; the first slave single board is the slave single board directly connected with the master single board.

Further, the address lines between the slave boards are connected in a preset staggered manner, including:

the mth address output pin of the second connector of the source slave single board is connected with the 1 st address input pin of the second connector of the terminal slave single board adjacent to the mth address output pin; the nth address output pin of the second connector of the source slave single board is connected to the (n + 1) th address input pin of the second connector of the terminal slave single board; the source slave single board is arranged close to the master single board, and the terminal slave single board is arranged far away from the master single board; wherein n is more than or equal to 1 and less than M, and n is an integer. Taking fig. 2 as an example, corresponding to the slave board 1, the slave board 2 is a terminal slave board; and the slave single board 2 is a source end slave single board corresponding to the slave single board 3. Specifically, referring to fig. 3, fig. 3 is a schematic diagram illustrating An address line connection principle of a cross-board daisy chain transmission structure according to An embodiment of the present invention, and a master board and a slave board 1 directly connected to the master board are taken as An example to describe, where the first address output pin of the master board is a1 (which is An nth first address output pin of the master board and is used to address a1 st slave board), a2 (which is An n-1 th first address output pin of the master board and is used to address a2 nd slave board), An (which is a1 st first address output pin of the master board and is used to address the nth slave board), and the address input pin of the slave board 1 is 1, 2, and … n. The connection between the slave single board and the slave single board is similar to this, and is not described again.

For ease of understanding, fig. 2 and 4 illustrate that M and N are both 3, which is obviously not a limitation of the present invention. Those skilled in the art can understand that M is greater than or equal to N, which is more convenient for expanding the number of slave boards of the cross-board daisy chain transmission structure, in practical application, one should be done against the other, and specific values of M and N are reasonably selected according to actual working condition needs and expectations.

Preferably, an nth address input pin of the slave board is directly connected to an nth address output pin.

Specifically, referring to fig. 4, fig. 4 is a schematic diagram illustrating connection of address lines of the cross-board daisy chain transmission structure according to an embodiment of the present invention. As can be seen from fig. 4, the clock line SCL and the data line SDA in the IIC are directly connected. For the address lines, a uniform interleaving pattern is used. The pin 1 of the source end is connected with the pin 2 of the terminal, the pin 2 of the source end is connected with the pin 3 of the terminal, and the pin 3 of the source end is connected with the pin 1 of the terminal. A1 in the Master board indicates addressing (chip select) to slave board 1, a2 indicates addressing (chip select) to slave board 2, and A3 indicates addressing (chip select) to said slave board 3.

In particular, in fig. 3 and 4, in order to avoid confusion of the illustration, no serial numbers are labeled on the first address output pin of the master board and the second address output pin of the slave board, and those skilled in the art can understand that, like the address input pin of the slave board, the serial numbers are analogized from top to bottom in the illustration direction. Taking the master single board in fig. 4 as an example, the first address output pin labeled as A3 is the 1 st first address output pin, the first address output pin labeled as a2 is the 2 nd first address output pin, and the first address output pin labeled as a1 is the 3 rd first address output pin. And similarly, the second address output pin of the slave single board is not described again.

Preferably, in one exemplary embodiment, according to a preset addressing rule, the cross-board daisy chain transmission structure, each of the first address output pins of the master board is configured to address one slave board; the slave single board is configured to determine whether the master single board communicates with the master single board according to a chip selection signal received by the address input pin corresponding to the first address output pin for addressing the master single board.

Specifically, the preset addressing rule includes: the master single board sets the chip selection signal of the nth first address output pin to be 1, and sets the chip selection signals of other first address output pins to be 0; and each slave single board acquires a chip selection signal from the 1 st address input pin. Specifically, the cross-board daisy chain transmission structure with one master board and 3 slave boards is still taken as an example for description. Referring to fig. 4, for all slave boards, a signal is uniformly taken from pin 1 as a chip select signal, and the chip select signal may be connected to a CS end of an IIC device (slave board) itself or a buffer CS end of a receiving IIC device (slave board). When the slave board 1 needs to be communicated, a1 is set to 1, a2 and A3 are set to 0, and for the slave board 1 that receives the chip selection set to 1, the other slave boards 2 and 3 are subjected to the chip selection set to 0. Similarly, when communicating with the slave board 2, setting a2 to 1, a1, and A3 to 0, and for the slave board 2 receiving the chip option set to 1, the slave board 1 and the slave board 3 receive the chip option set to 0. By the configuration, even if the cable and the slave single board are completely unified materials, the master single board can also ensure the communication with the expected slave single board. The addressing problem of daisy chain series connection is solved by the address line staggered connection mode, and the hardware unification of the slave single board is ensured.

Obviously, this is only a description of the preferred embodiment, and in other embodiments, the preset addressing rule may also be addressed by other embodiments different from those listed in the above embodiments, and only one slave board is addressed at the same time, which is not described herein again.

Preferably, in one exemplary embodiment, the parameter information of the N slave boards is the same. Furthermore, the cross-single-board daisy chain transmission structure further comprises N-1 signal lines, and the physical information of the N-1 signal lines is the same. Preferably, the lengths of the N-1 signal lines are the same.

Preferably, in one exemplary embodiment, the master board further includes a first buffer, the slave board further includes a second buffer, and the first buffer and/or the second buffer are used to reduce the capacitance of the signal line; the signal line is used for connecting the master single board, the first slave single board, and the N slave single boards. Preferably, the first buffer and/or the second buffer may be IIC extensions.

With the configuration, according to the cross-board daisy chain transmission structure provided by the invention, as the cable realizes the transparent transmission function through the connector, the receiving end of the slave board is well isolated by the buffer (buffer), especially the IIC extender provides a CS port, and the isolation of part of nodes (slave boards) under the condition of damage is ensured. Therefore, even if a certain slave single board (IIC device) fails or is even damaged, the signal reception of other slave single boards will not be affected. Furthermore, the buffer can also play a role in reducing the bus capacitance and optimizing the signal integrity, and can solve the problem of poor signal integrity caused by too large capacitance on a long-distance transmission bus of a plurality of slave single plates, so that the capacitance on the bus is greatly reduced through the isolation of the IIC extender, and the signal integrity of the long-distance multi-node topology can better support the signal transmission of the long-distance multi-slave single plates.

Based on the same inventive concept, a further embodiment of the present invention further provides a master single board, where the master single board is used in a cross-board daisy chain transmission structure, the cross-board daisy chain transmission structure includes one master single board and N slave single boards connected in series in a daisy chain manner, N is greater than or equal to 1, and N is an integer;

the master single board is configured to be directly connected with a clock line and a data line of the slave single board which are directly connected with the master single board, and the address lines are connected according to a preset staggered mode.

Based on the same inventive concept, another embodiment of the present invention further provides a slave single board, where the slave single board is used in a cross-board daisy chain transmission structure, the cross-board daisy chain transmission structure includes a master single board and N slave single boards connected in series in a daisy chain manner, N is greater than or equal to 1, and N is an integer;

the slave single board is configured to be directly connected with the clock line and the data line between the master single board and other slave single boards, and the address lines are connected according to a preset staggered mode.

Since the master board and the slave board provided in the foregoing embodiments have the same basic idea as the cross-board daisy chain transmission structure provided in the foregoing embodiments of the present invention, the introduction is relatively simple, and for the specific description of the master board and the slave board, reference may be made to each embodiment of the cross-board daisy chain transmission structure. Further, the master board and the slave board provided in the foregoing embodiments and the cross-board daisy chain transmission structure provided in the foregoing embodiments of the present invention belong to the same inventive concept, and therefore, at least the same beneficial effects are achieved, and no further description is given here.

Based on the same inventive concept, the invention further provides a cross-single-board daisy chain transmission system, wherein the single-board daisy chain transmission system comprises a master single board and adopts the cross-single-board daisy chain transmission structure implemented according to any one of the above.

In summary, the cross-board daisy chain transmission structure, the master board, the slave board and the system provided by the invention not only reduce the number of the master board connectors and the drivers, but also can significantly reduce the material quantity of the signal lines connecting the master board and the slave board, and have better expandability.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

In summary, the above embodiments have described in detail different configurations of the cross board daisy chain transmission structure, the master board, the slave board and the system according to the present invention, and it should be understood that the above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention in any way.