阅读说明：本技术 解码方法、存储器存储装置及存储器控制电路单元 (Decoding method, memory storage device and memory control circuit unit ) 是由 林玉祥 于 2021-09-14 设计创作，主要内容包括：本发明提供一种解码方法、存储器存储装置及存储器控制电路单元。所述方法包括：对从实体单元集合读取的多个第一数据帧分别执行单帧解码,其中所述实体单元集合包含可复写式非易失性存储器模块中的多个第一实体单元；响应于所述多个第一数据帧的整体解码结果符合第一条件,获得与所述实体单元集合有关的错误评估信息,其中所述错误评估信息反映所述实体单元集合的比特错误状态；根据所述错误评估信息获得可靠度信息；以及根据所述可靠度信息对从所述多个第一实体单元的其中之一读取的第二数据帧执行所述单帧解码。藉此,可提升对于此实体单元集合中的数据帧的解码能力。(The invention provides a decoding method, a memory storage device and a memory control circuit unit. The method comprises the following steps: performing single-frame decoding on a plurality of first data frames read from an entity unit set respectively, wherein the entity unit set comprises a plurality of first entity units in a rewritable nonvolatile memory module; obtaining error assessment information related to the set of physical units in response to a global decoding result of the plurality of first data frames meeting a first condition, wherein the error assessment information reflects a bit error status of the set of physical units; obtaining reliability information according to the error evaluation information; and performing the single frame decoding on the second data frame read from one of the plurality of first entity units according to the reliability information. Therefore, the decoding capability of the data frame in the entity unit set can be improved.)

1. A decoding method for a memory storage device, wherein the memory storage device includes a rewritable nonvolatile memory module including a plurality of physical units, and the decoding method includes:

performing single frame decoding on a plurality of first data frames read from a set of entity units, respectively, wherein the set of entity units includes a plurality of first entity units of the plurality of entity units;

obtaining error assessment information related to the set of physical units in response to a global decoding result of the plurality of first data frames meeting a first condition, wherein the error assessment information reflects a bit error status of the set of physical units;

obtaining reliability information according to the error evaluation information; and

performing the single frame decoding on the second data frame read from one of the plurality of first entity units according to the reliability information.

2. The decoding method of claim 1, wherein the error assessment information comprises a count value, and the count value positively correlates to a bit error rate of the set of physical units.

3. The decoding method of claim 1, wherein the step of obtaining the error assessment information related to the set of physical units comprises:

counting the total number of frames which fail to be decoded in the plurality of first data frames according to the overall decoding results of the plurality of first data frames; and

and obtaining the error evaluation information according to the total number.

4. The decoding method of claim 1, wherein the step of obtaining the error assessment information related to the set of physical units comprises:

performing an integration logic operation on the plurality of first data frames; and

and obtaining the error evaluation information according to the execution result of the integrated logic operation.

5. The decoding method of claim 4, wherein the step of obtaining the error assessment information according to the execution result of the integrated logical operation comprises:

obtaining a sequence of data reflecting the execution result of the integrated logical operation;

counting the total number of at least one specific bit in the data sequence; and

and obtaining the error evaluation information according to the total number.

6. The decoding method of claim 1, wherein the step of obtaining the reliability information from the error assessment information comprises:

adjusting at least part of the reliability information from first information to second information according to the error assessment information, wherein the first information is different from the second information.

7. The decoding method of claim 1, further comprising:

performing multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

8. The decoding method of claim 1, wherein the first condition comprises a total number of frames of the plurality of first data frames that failed decoding being greater than a threshold value.

9. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module including a plurality of entity units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to perform single frame decoding on a plurality of first data frames read from a set of physical units, respectively, the set of physical units including a plurality of first physical units of the plurality of physical units,

in response to the overall decoding result of the plurality of first data frames meeting a first condition, the memory control circuitry unit is further configured to obtain error assessment information related to the set of physical units, wherein the error assessment information reflects a bit error status of the set of physical units,

the memory control circuit unit is further configured to obtain reliability information based on the error evaluation information, an

The memory control circuit unit is further configured to perform the single frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

10. The memory storage device of claim 9, wherein the error assessment information comprises a count value, and the count value positively correlates to a bit error rate of the set of physical units.

11. The memory storage device of claim 9, wherein obtaining the error assessment information related to the set of physical units comprises:

counting the total number of frames which fail to be decoded in the plurality of first data frames according to the overall decoding results of the plurality of first data frames; and

and obtaining the error evaluation information according to the total number.

12. The memory storage device of claim 9, wherein obtaining the error assessment information related to the set of physical units comprises:

performing an integration logic operation on the plurality of first data frames; and

and obtaining the error evaluation information according to the execution result of the integrated logic operation.

13. The memory storage device of claim 12, wherein obtaining the error evaluation information as a result of the execution of the consolidated logical operation comprises:

obtaining a sequence of data reflecting the execution result of the integrated logical operation;

counting the total number of at least one specific bit in the data sequence; and

and obtaining the error evaluation information according to the total number.

14. The memory storage device of claim 9, wherein obtaining the reliability information from the error assessment information comprises:

adjusting at least part of the reliability information from first information to second information according to the error assessment information, wherein the first information is different from the second information.

15. The memory storage device of claim 9, wherein the memory control circuitry unit is further to:

performing multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

16. The memory storage device of claim 9, wherein the first condition comprises a total number of frames of the plurality of first data frames that failed to decode being greater than a threshold value.

17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

error checking and correcting circuit, and

memory management circuitry connected to the host interface, the memory interface, and the error checking and correcting circuitry,

wherein the error checking and correcting circuit is configured to perform single frame decoding on a plurality of first data frames read from a set of physical units respectively, the set of physical units including a plurality of first physical units of the plurality of physical units,

in response to a global decoding result of the plurality of first data frames meeting a first condition, the memory management circuitry is further to obtain error assessment information related to the set of physical units, wherein the error assessment information reflects a bit error status of the set of physical units,

the memory management circuit is further configured to obtain reliability information based on the error assessment information, an

The error checking and correcting circuit is further configured to perform the single frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

18. The memory control circuitry unit of claim 17, wherein the error assessment information comprises a count value, and the count value positively correlates to a bit error rate of the set of physical cells.

19. The memory control circuitry unit of claim 17, wherein the operation of obtaining the error assessment information related to the set of physical units comprises:

counting the total number of frames which fail to be decoded in the plurality of first data frames according to the overall decoding results of the plurality of first data frames; and

and obtaining the error evaluation information according to the total number.

20. The memory control circuitry unit of claim 17, wherein the operation of obtaining the error assessment information related to the set of physical units comprises:

performing an integration logic operation on the plurality of first data frames; and

and obtaining the error evaluation information according to the execution result of the integrated logic operation.

21. The memory control circuitry unit of claim 20, wherein obtaining the error evaluation information as a result of the execution of the consolidated logic operation comprises:

obtaining a sequence of data reflecting the execution result of the integrated logical operation;

counting the total number of at least one specific bit in the data sequence; and

and obtaining the error evaluation information according to the total number.

22. The memory control circuitry unit of claim 17, wherein the operation of obtaining the reliability information from the error assessment information comprises:

adjusting at least part of the reliability information from first information to second information according to the error assessment information, wherein the first information is different from the second information.

23. The memory control circuitry unit of claim 17, wherein the error checking and correction circuitry is further to:

performing multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

24. The memory control circuit unit of claim 17, wherein the first condition comprises a total number of frames of the plurality of first data frames that failed decoding being greater than a threshold value.

25. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module including a plurality of entity units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to perform single frame decoding on a plurality of first data frames read from a set of physical units, respectively, the set of physical units including a plurality of first physical units of the plurality of physical units,

in response to the overall decoding result of the plurality of first data frames satisfying a first condition, the memory control circuit unit updates reliability information and performs the single frame decoding on a second data frame read from one of the plurality of first entity units according to the updated reliability information, and

the memory control circuit unit is further configured to perform multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not complying with the first condition.

26. The memory storage device of claim 25, wherein the first condition comprises a total number of frames of the plurality of first data frames that failed decoding being greater than a threshold value.

Technical Field

The present invention relates to a memory management technology, and more particularly, to a decoding method, a memory storage device and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown rapidly in these years, so that the demand of consumers for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable electronic devices as exemplified above.

Generally, to ensure the correctness of data in the rewritable nonvolatile memory module, the data is encoded and then stored in the rewritable nonvolatile memory module. When reading data, the data read from the rewritable nonvolatile memory module is decoded to try to correct errors in the data. If the errors in the data are corrected, the corrected data is transmitted back to the host system. In some encoding/decoding techniques, data stored in multiple physical pages may be encoded into the same block code. Data belonging to the same block code can be protected from each other. For example, when a certain data in a block code cannot be corrected by its own error correction code, the data stored in other physical pages in the block code can be used to assist the data in error correction. However, conventionally, the coding/decoding of block codes and the single-page coding/decoding of physical pages are independent of each other.

Disclosure of Invention

The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the decoding capability of a data frame in a specific entity unit set according to error evaluation information of the entity unit set.

An exemplary embodiment of the present invention provides a decoding method for a memory storage device. The memory storage device comprises a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The decoding method comprises the following steps: performing single frame decoding on a plurality of first data frames read from a set of entity units, respectively, wherein the set of entity units includes a plurality of first entity units of the plurality of entity units; obtaining error assessment information related to the set of physical units in response to a global decoding result of the plurality of first data frames meeting a first condition, wherein the error assessment information reflects a bit error status of the set of physical units; obtaining reliability information according to the error evaluation information; and performing the single frame decoding on the second data frame read from one of the plurality of first entity units according to the reliability information.

In an exemplary embodiment of the present invention, the step of obtaining the error-assessment information related to the set of physical units comprises: counting the total number of frames which fail to be decoded in the plurality of first data frames according to the overall decoding results of the plurality of first data frames; and obtaining the error assessment information according to the total number.

In an exemplary embodiment of the present invention, the step of obtaining the error-assessment information related to the set of physical units comprises: performing an integration logic operation on the plurality of first data frames; and obtaining the error assessment information according to the execution result of the integrated logic operation.

In an exemplary embodiment of the present invention, the step of obtaining the error-assessment information according to the execution result of the integrated logic operation comprises: obtaining a sequence of data reflecting the execution result of the integrated logical operation; counting the total number of at least one specific bit in the data sequence; and obtaining the error assessment information according to the total number.

In an exemplary embodiment of the invention, the step of obtaining the reliability information according to the error assessment information comprises: adjusting at least part of the reliability information from first information to second information according to the error assessment information, wherein the first information is different from the second information.

In an exemplary embodiment of the present invention, the decoding method further includes: performing multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for respectively performing single-frame decoding on a plurality of first data frames read from an entity unit set, wherein the entity unit set comprises a plurality of first entity units in the entity units. In response to the overall decoding result of the plurality of first data frames meeting a first condition, the memory control circuit unit is further configured to obtain error assessment information related to the set of physical units, wherein the error assessment information reflects a bit error status of the set of physical units. The memory control circuit unit is also used for obtaining reliability information according to the error evaluation information. The memory control circuit unit is further configured to perform the single frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

In an example embodiment of the present invention, the memory control circuit unit is further configured to perform multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit comprises a host interface, a memory interface, an error checking and correcting circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuitry is coupled to the host interface, the memory interface, and the error checking and correcting circuitry. The error checking and correcting circuit is used for respectively performing single-frame decoding on a plurality of first data frames read from the entity unit set. The set of entity units includes a first plurality of entity units of the plurality of entity units. In response to a result of overall decoding of the plurality of first data frames meeting a first condition, the memory management circuitry is further to obtain error assessment information related to the set of physical units, wherein the error assessment information reflects a bit error status of the set of physical units. The memory management circuitry is also to obtain reliability information from the error evaluation information. The error checking and correcting circuit is further configured to perform the single frame decoding on a second data frame read from one of the plurality of first physical units according to the reliability information.

In an exemplary embodiment of the invention, the error assessment information includes a count value, and the count value is positively correlated to the bit error rate of the set of physical units.

In an exemplary embodiment of the present invention, the operation of obtaining the error-assessment information related to the set of physical units comprises: counting the total number of frames which fail to be decoded in the plurality of first data frames according to the overall decoding results of the plurality of first data frames; and obtaining the error assessment information according to the total number.

In an exemplary embodiment of the present invention, the operation of obtaining the error-assessment information related to the set of physical units comprises: performing an integration logic operation on the plurality of first data frames; and obtaining the error assessment information according to the execution result of the integrated logic operation.

In an exemplary embodiment of the present invention, obtaining the error-assessment information based on the execution result of the integrated logic operation comprises: obtaining a sequence of data reflecting the execution result of the integrated logical operation; counting the total number of at least one specific bit in the data sequence; and obtaining the error assessment information according to the total number.

In an exemplary embodiment of the invention, the operation of obtaining the reliability information according to the error-assessment information comprises: adjusting at least part of the reliability information from first information to second information according to the error assessment information, wherein the first information is different from the second information.

In an exemplary embodiment of the invention, the error checking and correcting circuit is further configured to perform multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not meeting the first condition.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for respectively performing single-frame decoding on a plurality of first data frames read from the entity unit set. The set of entity units includes a first plurality of entity units of the plurality of entity units. In response to the overall decoding result of the plurality of first data frames meeting a first condition, the memory control circuit unit updates reliability information and performs the single frame decoding on a second data frame read from one of the plurality of first entity units according to the updated reliability information. The memory control circuit unit is further configured to perform multi-frame decoding on the plurality of first data frames in response to the overall decoding result of the plurality of first data frames not complying with the first condition.

In an exemplary embodiment of the invention, the first condition includes that a total number of frames of the plurality of first data frames that failed to be decoded is greater than a threshold value.

Based on the above, after performing multi-frame encoding on a plurality of first data frames stored to a specific set of entity units, error assessment information related to the set of entity units may be obtained. In particular, the error-assessment information may reflect the bit error status of the entire set of physical units. Thereafter, reliability information may be obtained from the error evaluation information and single frame decoding may be performed on the second data frame read from one of the plurality of first entity units according to the reliability information. Therefore, the decoding capability of the data frame in the entity unit set can be improved.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

fig. 7 is a diagram illustrating multi-frame encoding according to an exemplary embodiment of the present invention;

FIG. 8 is a diagram illustrating obtaining error-assessment information according to an exemplary embodiment of the present invention;

FIG. 9 is a diagram illustrating obtaining error-assessment information according to an exemplary embodiment of the present invention;

FIG. 10 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention;

FIG. 11 is a diagram illustrating a table of reliability information according to an exemplary embodiment of the present invention;

fig. 12 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention;

fig. 13 and 14 are flowcharts illustrating a decoding method according to an exemplary embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.

In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner.

In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) storage device 342, which connect the memory module directly to the host system motherboard.

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash) interface standard, CF interface standard, Device interface standard, and Electronic drive interface (Electronic interface), IDE) standard or other suitable standard. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53 and an error checking and correcting circuit 54.

The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.

In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Thereafter, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 54 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correcting circuit 54 may support various encoding/decoding algorithms such as Low Density Parity Check (LDPC) code, BCH code, Reed-solomon (RS) code, Exclusive OR (XOR) code, and the like.

The basic unit of encoding/decoding performed by the error checking and correction circuit 54 is a frame (also referred to as a data frame). One frame may include a plurality of data bits. In an exemplary embodiment, one frame includes 256 bits. However, in another exemplary embodiment, a frame may also include more (e.g., 4K bytes) or less bits.

Error checking and correction circuit 54 may perform single-frame (single-frame) encoding and decoding on data in a single frame, and error checking and correction circuit 54 may also perform multi-frame (multi-frame) encoding and decoding on data in multiple frames. In an exemplary embodiment, the error checking and correcting circuit 54 performs single frame encoding and decoding based on the LDPC code, and the present invention is not limited thereto. In an exemplary embodiment, the error checking and correcting circuit 54 performs multi-frame encoding and decoding based on BCH codes, RS codes and/or XOR codes, and the invention is not limited thereto. Depending on the encoding/decoding algorithm employed, the error checking and correction circuit 54 may encode the data to be protected to produce a corresponding error correction code and/or error check code. Thereafter, the error correction code and/or the error check code generated by the encoding can be used to correct errors in the data to be protected. For convenience of explanation, the error correction codes and/or error check codes generated through encoding will be collectively referred to as parity data hereinafter.

In an exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.

In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a Virtual Block (VB). A virtual block may include a plurality of physical addresses or a plurality of physical programming units.

Physical units 610(0) -610 (A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG. 1). For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.

Memory management circuitry 51 may configure logic units 612(0) - (612 (C) to map physical units 610(0) - (610 (A) in memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses.

It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, it indicates that the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing mapping relationships between the logical units and the physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, the memory management circuit 51 may manage the physical units 610(0) 610(A) using the set of physical units. A set of physical units may contain multiple physical units. One set of physical units may be used to store multiple frames. One physical unit may be used to store one or more frames. A single set of physical cells may include physical cells in the same (or different) memory planes, the same (or different) memory dies, and/or the same (or different) Chip Enable (CE) areas.

In an example embodiment, error checking and correction circuitry 54 may perform multi-frame encoding on frames stored to a set of physical units to protect data in such frames by parity data generated by the multi-frame encoding. In an exemplary embodiment, the error checking and correcting circuit 54 may perform multi-frame decoding on a plurality of frames read from a certain physical unit set to correct errors in the frames through parity data generated by the multi-frame encoding. In an exemplary embodiment, error checking and correction circuit 54 may perform single frame encoding on a single frame stored to a physical unit to protect data in the single frame by parity data generated by the single frame encoding. In an exemplary embodiment, the error checking and correcting circuit 54 may perform single frame decoding on a single frame read from a physical unit to correct errors in the single frame by parity data generated by the single frame encoding.

Fig. 7 is a diagram illustrating multi-frame encoding according to an exemplary embodiment of the present invention. Referring to fig. 7, frames 710(1) -710 (n) contain data stored in a certain set of physical units (also referred to as a first set of physical units). For example, the first set of physical units may include the physical units (also referred to as first physical units) 610(1) -610 (n) in FIG. 6. Where frame 710(k) includes data to be stored to physical unit 610(k), and k is between 1 and n. The data in frames 710(1) through 710(n) may include data stored as instructed by the write command sent by host system 10. Alternatively, the data in the frames 710(1) - (710 (n) may also include data that is read from the rewritable nonvolatile memory module 43 and waits to be restored back to the rewritable nonvolatile memory module 43.

In an exemplary embodiment, the error checking and correcting circuit 54 may perform multi-frame encoding on the frames 710(1) - (710 (n) to generate the frame 710 (p). The data in frame 710(p) includes parity data to protect frames 710(1) -710 (n). For example, when performing multi-frame decoding on frames 710(1) - (710 (n), the parity data in frame 710(p) may be used to detect and/or correct errors in frames 710(1) - (710 (n).

In an exemplary embodiment, in multi-frame encoding, the data in the frames 710(1) -710 (n) is encoded according to the position of each bit (or byte). For example, bits b (11), b (21), …, b (n1) at position 701(1) may be encoded to obtain bit b (p1) in frame 710(p), bits b (12), b (22), …, b (n2) at position 701(2) may be encoded to obtain bit b (p2) in frame 710 (p); by analogy, bits b (1m), b (2m), …, b (nm) at position 701(m) may be encoded to obtain bits b (pm) in frame 710 (p). Thereafter, in multi-frame decoding, bits (also referred to as parity bits) in frame 710(p) may be used to detect and/or correct erroneous bits in frames 710(1) -710 (n). For example, bit b (p2) in frame 710(p) may be used to detect or correct one or more erroneous bits in locations 701 (2).

It should be noted that, in an exemplary embodiment, the arrangement of the bits covered by any one of the positions 701(1) to 701(m) may be different from the arrangement shown in fig. 7, and the invention is not limited thereto. In addition, in an exemplary embodiment, the number of the frames 710(p) containing parity data may also be 2 or more, so as to provide different or better multi-frame decoding capability, which is not limited by the invention.

In an exemplary embodiment, the error checking and correcting circuit 54 may perform single frame encoding on the frame 710(j) of the frames 710(1) -710 (n) and 710(p) to generate parity data for protecting the frame 710(j), where j is between 1 and n or j may be p. Thereafter, in single frame decoding, parity data generated via single frame encoding of frame 710(j) may be used to detect and/or correct erroneous bits in frame 710 (j).

In an example embodiment, the parity data generated in the frame 710(p) by performing multi-frame encoding is also referred to as Redundant Array of Independent Disks (RAID) error correction code. In an exemplary embodiment, frames 710(1) -710 (n) and 710(p) may also be combined to be considered a block code. Frames 710(1) -710 (n) and 710(p) may be stored into the plurality of first physical units.

In an exemplary embodiment, when data stored in one of the physical units in the first physical unit set is to be read, the memory management circuit 51 can send a read command sequence to the rewritable nonvolatile memory module 43. The read command sequence can instruct the rewritable nonvolatile memory module 43 to read data from a specific physical unit. The rewritable nonvolatile memory module 43 can transmit the data read from the specific physical unit back to the memory management circuit 51 according to the read command sequence. Error checking and correction circuitry 54 may perform single frame decoding on the frame containing the data. For example, if the data in the frame is encoded based on an LDPC code for a single frame, error checking and correction circuit 54 may decode the frame based on the LDPC code for a single frame. If the decoding is successful (indicating that the data in the frame is correct and/or the error has been corrected), the error checking and correcting circuit 54 may output the data that was decoded successfully. However, if the decoding fails (indicating that the frame is a frame that cannot be corrected by single-frame decoding), the error checking and correcting circuit 54 may initiate a multi-frame decoding procedure to perform multi-frame decoding on a plurality of frames including the frame. For example, if the frame was originally multi-frame encoded based on an RS (or XOR) code, error checking and correction circuit 54 may multi-frame decode the frame based on the RS (or XOR) code as well. In an exemplary embodiment, a frame that cannot be corrected by single frame decoding is also referred to as a UECC frame.

It should be noted that in multi-frame decoding based on RS codes, at most two UECC frames can exist simultaneously in the frames to be decoded. If three or more UECC frames are included in the frame to be decoded at the same time, multi-frame decoding based on RS codes cannot correct errors in these frames. Similarly, in multi-frame decoding based on XOR codes, at most one UECC frame can exist simultaneously in the frames to be decoded. If two or more UECC frames are included in the frame to be decoded at the same time, the multi-frame decoding based on the XOR code cannot correct errors in these frames. Therefore, after entering the multi-frame decoding procedure, the decoding success rate of multi-frame decoding can be effectively improved by reducing the total number of UECC frames in the frames to be decoded.

In an example embodiment, upon entering the multi-frame decoding procedure (e.g., a single-frame decoding failure for a frame), the memory management circuit 51 may instruct the error checking and correcting circuit 54 to perform single-frame decoding on a plurality of frames (also referred to as first data frames) read from the first set of physical units, respectively. For example, each first data frame is read from one physical unit (i.e. the first physical unit) in the first set of physical units. Then, the memory management circuit 51 may determine whether the overall decoding result of the plurality of first data frames meets a specific condition (also referred to as a first condition).

In an example embodiment, the first condition includes that a total number of frames (i.e., UECC frames) of the plurality of first data frames, which fail to be decoded in single frame decoding, is greater than a threshold value. For example, the threshold value may be 1 or 2. For example, in an exemplary embodiment, if the multi-frame encoding/decoding is performed based on an XOR code, the threshold may be 1. Alternatively, in an exemplary embodiment, if the multi-frame encoding/decoding is performed based on the RS code, the threshold may be 2. In an example embodiment, in response to the total number of UECC frames in the first data frames being greater than the threshold value, the memory management circuit 51 may determine that the overall decoding result of the first data frames meets the first condition. Conversely, in response to the total number of UECC frames in the first data frames not being greater than the threshold value, the memory management circuit 51 may determine that the overall decoding result of the first data frames does not meet the first condition.

In an example embodiment, in response to the overall decoding result of the plurality of first data frames meeting the first condition, the memory management circuit 51 may attempt to update the reliability information used in the single frame decoding. Then, the error checking and correcting circuit 54 may perform single frame decoding on the frame (also referred to as a second data frame) read from one of the plurality of first physical units according to the updated reliability information. By updating the reliability information, an attempt can be made to increase the decoding success rate of performing single frame decoding on the second data frame. If the second data frame is successfully decoded, the total number of UECC frames in the plurality of first data frames may be correspondingly decreased (e.g., by 1). If the total number of UECC frames in the first data frames is reduced to be not greater than the threshold, the memory management circuit 51 may determine that the overall decoding result of the first data frames does not meet the first condition.

In an example embodiment, in response to the overall decoding result of the plurality of first data frames not meeting the first condition, the memory management circuitry 51 may instruct the error checking and correcting circuitry 54 to perform multi-frame decoding on the plurality of first data frames. In such multi-frame decoding, data in the first data frames may be subjected to cross-frame logic operations in an attempt to correct errors in such data. In particular, in the case that the overall decoding result of the first data frames does not satisfy the first condition (i.e. the total number of UECC frames in the first data frames is not greater than the threshold), the multi-frame decoding has a high probability (even guaranteed) to completely correct all errors in the first data frames. Therefore, after entering the multi-frame decoding program, the decoding success rate of multi-frame decoding can be effectively improved by gradually reducing or converging the total number of the UECC frames in the frames to be decoded.

In an example embodiment, the memory management circuit 51 may obtain the error assessment information related to the first set of physical units in response to the overall decoding result of the plurality of first data frames meeting the first condition. The error-assessment information may reflect a bit error status of the first set of physical units. For example, the error-assessment information may roughly reflect whether the total number of error bits included in the data read from the first physical unit set (i.e., the first data frames) is more or less. The memory management circuit 51 can obtain reliability information according to the error evaluation information. For example, such reliability information may include a Log Likeness Ratio (LLR) that may be used in single frame decoding. Error checking and correction circuit 54 may perform single frame decoding on the second data frame in accordance with this reliability information.

In an example embodiment, the memory management circuit 51 may adjust at least a portion of the reliability information (e.g., LLR) from one information (also referred to as first information) to another information (also referred to as second information) according to the error-assessment information. The first information may be different from the second information. Memory management circuitry 51 may adjust the reliability information (e.g., LLRs) to different degrees based on different error-assessment information. Thereafter, the error checking and correcting circuit 54 may perform single frame decoding on the second data frame based on the adjusted reliability information, thereby increasing a decoding success rate of the second data frame. On the premise of improving the decoding success rate of the single-frame decoding of the second data frame, the total number of frames which cannot be corrected by the single-frame decoding of the frame to be decoded can be reduced, and the decoding success rate of the multi-frame decoding is further improved.

In an exemplary embodiment, the error assessment information includes a count value. The count value may positively correlate to the bit error rate of the first set of physical units as a whole. For example, the higher the bit error rate of the first entity unit set as a whole, the more the total number of UECC frames and/or the total number of error bits in the data read from the first entity unit set, the larger the count value will be. Alternatively, from another perspective, the count value may also be positively correlated to a total number of UECC frames and/or a total number of error bits in the data read from the first set of physical units.

In an example embodiment, the memory management circuit 51 may obtain the error assessment information according to an overall decoding result of the plurality of first data frames. For example, the memory management circuit 51 may count the total number of frames that fail to be decoded (i.e., the total number of UECC frames) in the first data frames according to the overall decoding result of the plurality of first data frames. Memory management circuitry 51 may obtain the error evaluation information from this total.

FIG. 8 is a diagram illustrating obtaining error-assessment information according to an exemplary embodiment of the present invention. Referring to fig. 8, the plurality of first data frames are represented by frames 810(1) to 810 (p). After performing single frame decoding on frames 810(1) -810 (p), respectively, the UECC frames (e.g., frame 810(i)) in frames 810(1) -810 (p) may be recorded, as shown in fig. 8. Memory management circuit 51 may count the total number of UECC frames in frames 810(1) -810 (p) and obtain a count value N based on this total number. For example, the count value N may be equal to or reflect the total number of frames labeled UECC from frames 810(1) -810 (p). Thereafter, a count value N may be included in the error assessment information and used to adjust the reliability information.

In an exemplary embodiment, the error checking and correcting circuit 54 may perform an integrated logic operation on the plurality of first data frames. The memory management circuit 51 may obtain the error evaluation information according to the execution result of the integrated logic operation. In an example embodiment, the integrating logic may include performing a logic operation including an XOR operation on the plurality of first data frames. Therefore, the execution result of the integration logic operation may roughly reflect the total number of error bits in the plurality of first data frames. For example, after performing the consolidated logical operation, memory management circuitry 51 may obtain a data sequence that reflects the results of the execution of the consolidated logical operation. Memory management circuitry 51 may count the total number of particular bits (e.g., bits "1" or "0") in this data sequence. Memory management circuitry 51 may obtain the error evaluation information from this total.

FIG. 9 is a diagram illustrating obtaining error-assessment information according to an exemplary embodiment of the present invention. Referring to fig. 9, the plurality of first data frames are represented by frames 910(1) to 910 (p). After performing logical operations including XOR operations on frames 910(1) -910 (p), data sequence 920 may be obtained. For example, data sequence 920 may include bits b (r1) through b (rm). For example, the bit b (r1) reflects the XOR execution result of the bits b (11), b (21) … through b (p1), as shown in fig. 9. Memory management circuit 51 may count the total number of bits "1" in data sequence 920 and obtain a count value N based on the total number. For example, the count value N may be equal to or reflect the total number of bits "1" in the data sequence 920. The count value N may roughly reflect the total number of error bits in the frames 910(1) -910 (p). For example, the greater the total number of error bits in frames 910(1) -910 (p), the greater the probability that there will be a total number of bits "1" in data sequence 920. Thereafter, a count value N may be included in the error assessment information and used to adjust the reliability information.

FIG. 10 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention. Referring to fig. 10, it is assumed that the threshold voltage distributions of the memory cells in the first plurality of physical cells include states 1010 and 1020. The state 1010 can be used to represent the distribution of threshold voltages of memory cells of the memory cells storing the first bit (or the first combination of bits). The state 1020 can be used to represent the distribution of the threshold voltages of the memory cells storing the second bit (or the second combination of bits) among the memory cells. For example, the first bit may be the bit "0" (or the first combination of bits may be the bit "000", etc.) and the second bit may be the bit "1" (or the second combination of bits may be the bit "101", etc.). In addition, the present invention does not limit the bits or bit combinations corresponding to the states 1010 and 1020, respectively.

In an exemplary embodiment, the memory management circuit 51 can send a read command sequence to the rewritable non-volatile memory module 43 to indicate that the memory cells are read using the read voltage levels 1001-1005. The total number of read voltage levels 1001-1005 can be more or less. Based on the read results of the memory cells at the read voltage levels 1001-1005, the memory management circuit 51 can identify the threshold voltage of each of the memory cells as belonging to one of the voltage ranges A-F. Thereafter, assuming that the threshold voltage of a memory cell belongs to the voltage range a, the reliability information (e.g., LLR) corresponding to the voltage range a may be used in single frame decoding to decode the data bit read from the memory cell. Alternatively, assuming that the threshold voltage of a memory cell belongs to the voltage range C, the reliability information (e.g., LLR) corresponding to the voltage range C can be used in a single frame decoding to decode the data bit read from the memory cell, and so on.

Fig. 11 is a diagram illustrating a reliability information table according to an exemplary embodiment of the invention. Referring to fig. 11, it is assumed that the table data 1101 describes reliability information that can be correspondingly adopted by different error evaluation information. In an example embodiment, if the count value N in the obtained error evaluation information is equal to N (1), the parameter values (e.g., LLR values) corresponding to the voltage ranges a to F in the reliability information LLR (0) may be used in single-frame decoding after starting a multi-frame decoding procedure according to the table data 1101 to decode data read from a certain physical unit (i.e., single-frame decoding). Similarly, if the count value N in the obtained error evaluation information is equal to N (2) or N (3), the parameter values (e.g., LLR values) corresponding to the voltage ranges a to F in the reliability information LLR (1) or LLR (2) may be used in single-frame decoding after the start of the multi-frame decoding procedure according to the table data 1101.

In an exemplary embodiment, it is assumed that the reliability information used in the previous single frame decoding is LLR (0). After the latest count value N is obtained as N (2), the reliability information used for single frame decoding may be adjusted from LLR (0) to LLR (1). Thereafter, at least one frame (i.e., the second data frame) read from the first entity unit may perform single frame decoding based on the reliability information LLR (1). In the bit error state corresponding to the count value N-N (2), performing single frame decoding based on the reliability information LLR (1) may improve the decoding success rate of single frame decoding, compared to the reliability information LLR (0). Therefore, after the multi-frame decoding procedure is started, the total number of frames which are originally judged to be uncorrectable (namely UECC) can be reduced by adopting the reliability information which is more consistent with the bit error state of the current first entity unit set to execute single-frame decoding, and the decoding success rate of multi-frame decoding is further improved.

Fig. 12 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention. Referring to fig. 12, in step S1201, single frame decoding is performed on a plurality of first data frames read from a physical unit set, wherein the physical unit set includes a plurality of first physical units. In step S1202, it is determined whether the overall decoding result of the plurality of first data frames meets a first condition. If yes, in response to that the overall decoding result of the plurality of first data frames meets the first condition, in step S1203, error evaluation information related to the entity unit set is obtained, where the error evaluation information reflects a bit error status of the entity unit set. In step S1204, reliability information is obtained from the error evaluation information. In step S1205, the single frame decoding is performed on the second data frame read from one of the plurality of first entity units according to the reliability information. On the other hand, if the determination in step S1202 is no, in response to that the overall decoding results of the plurality of first data frames do not meet the first condition, in step S1206, multi-frame decoding is performed on the plurality of first data frames.

Fig. 13 and 14 are flowcharts illustrating a decoding method according to an exemplary embodiment of the invention. Referring to fig. 13, in step S1301, a multi-frame decoding procedure for a specific entity unit set is started. In step S1302, single frame decoding is performed on a plurality of data frames read from a plurality of first entity units in the entity unit set, respectively. In step S1303, it is determined whether the overall decoding result of the plurality of data frames meets a first condition (e.g., whether the total number of UECC frames is greater than a threshold value). If the overall decoding result of the data frame does not meet the first condition (e.g., the total number of UECC frames is not greater than the threshold), in step S1304, multi-frame decoding is performed on the data frames. On the other hand, if the overall decoding result of the plurality of data frames meets the first condition (for example, the total number of UECC frames is greater than the threshold), the process proceeds to step S1401 of fig. 14.

Referring to fig. 14, in step S1401, error assessment information related to the entity unit set is obtained. In step S1402, reliability information is adjusted according to the error evaluation information. In step S1403, single frame decoding is performed on one of the plurality of data frames according to the adjusted reliability information. In step S1404, it is determined whether the single frame decoding is successful. If the decoding is not successful (i.e., the decoding fails), in step S1405, it is determined whether all reliability information tables are used. For example, the reliability information tables are all pre-stored in the rewritable nonvolatile memory module. In single frame decoding, such reliability information tables may be used sequentially to provide available reliability information.

Taking fig. 11 as an example, different reliability information tables may record different table data 1101. After the multi-frame decoding process is started, the count value N (or the error evaluation information) may be used to query one of the reliability information tables to obtain the corresponding reliability information. If all the reliability information tables are not used, the process returns to step S1402, and uses the count value N (or the error evaluation information) to query another reliability information table to adjust the reliability information and then proceeds to step S1403. On the other hand, if it is determined in step S1404 that the decoding is successful (indicating that the number of UECC frames is decreased by one) or it is determined in step S1405 that all reliability information tables have been used, the process proceeds to step S1305 of fig. 13.

Returning to fig. 13, in step S1305, it is determined again whether or not the overall decoding result of the plurality of data frames meets the first condition. If the overall decoding result of the data frames does not meet the first condition (e.g., the total number of UECC frames is not greater than the threshold), in step S1304, multi-frame decoding is performed on the data frames. However, if the overall decoding result of the plurality of data frames meets the first condition (for example, the total number of UECC frames is greater than the threshold), in step S1306, it is determined whether the process flow of fig. 14 has been performed on all data frames belonging to the entity unit set. If there is a data frame that has not been processed in the processing flow of fig. 14, the process returns to step S1401 of fig. 14 to process the data frame. However, if it is determined in step S1306 that all data frames have been processed, it is determined in step S1307 that decoding has failed and an error handling procedure is performed (e.g., an access error occurred in the host system is reported).

However, the steps in fig. 12 to 14 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 12 to fig. 14 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 12 to 14 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the exemplary embodiments of the invention may obtain the appropriate reliability information according to the error evaluation information of a specific set of physical units and perform single-frame decoding on the data frames read from the specific set of physical units according to the reliability information after starting the multi-frame decoding procedure. In particular, after the multi-frame decoding procedure is initiated, if the total number of UECC frames in the physical unit set is still higher than the threshold, the reliability information for single-frame decoding may be updated or adjusted, and single-frame decoding may be re-performed based on this new reliability information. Therefore, the total number of the UECC frames in the entity unit set can be effectively reduced, and the decoding capability of the data frames in the entity unit set is synchronously improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.