阅读说明：本技术 一种栅极接地nmos型esd器件及其实现方法 (Grid grounding NMOS (N-channel metal oxide semiconductor) ESD (electro-static discharge) device and implementation method thereof ) 是由 朱天志 于 2021-08-30 设计创作，主要内容包括：本发明公开了一种栅极接地NMOS型ESD器件及其实现方法,所述方法将现有栅极接地NMOS型ESD器件下方的P型防静电植入层(28)去掉,并在其第二高浓度N型掺杂(26)的外侧加入浮接的第二高浓度P型掺杂(22)以降低触发电压,由源极、栅极以及第一高浓度P型掺杂(20)接在一起构成阴极,在第二高浓度N型掺杂(26)上方的金属硅化物(30)引出电极构成阳极,从而得到所述栅极接地NMOS型ESD器件。(The invention discloses a grid grounding NMOS type ESD device and a realization method thereof, the method removes a P type anti-static implantation layer (28) below the existing grid grounding NMOS type ESD device, adds a floating second high-concentration P type doping (22) at the outer side of a second high-concentration N type doping (26) thereof to reduce trigger voltage, connects a source electrode, a grid electrode and the first high-concentration P type doping (20) together to form a cathode, and leads out an electrode from a metal silicide (30) above the second high-concentration N type doping (26) to form an anode, thereby obtaining the grid grounding NMOS type ESD device.)

1. A grounded-gate NMOS-type ESD device, comprising:

a semiconductor substrate (80);

a low voltage P-well (70) created on the semiconductor substrate (80);

a first high-concentration P-type doping (20), a first high-concentration N-type doping (24), a second high-concentration N-type doping (26) and a floating second high-concentration P-type doping (22) are sequentially generated on the low-voltage P well (70), a non-metal silicide (50) is arranged on the part, close to the first high-concentration N-type doping (24), right above the second high-concentration N-type doping (26), and a metal silicide (30) is arranged on the part, close to the floating second high-concentration P-type doping (22), right above the second high-concentration N-type doping (26);

a gate oxide and an N-type gate (40) formed over the active region between the first high concentration N-type doping (24) and the second high concentration N-type doping (26);

the first high-concentration N-type doping (24), the N-type grid electrode (40) and the first high-concentration P-type doping (20) are connected together to form a cathode, and the metal silicide 30 leading-out electrode above the second high-concentration N-type doping (26) forms an anode.

2. A grounded-gate NMOS-type ESD device as claimed in claim 1, wherein: a shallow trench isolation (10) is disposed between the first high concentration P-type dopant (20) and the first high concentration N-type dopant (24).

3. A grounded-gate NMOS-type ESD device as claimed in claim 1, wherein: and metal silicides (30) are respectively generated above the first high-concentration P-type doping (20), the floating second high-concentration P-type doping (22), the first high-concentration N-type doping (24) and the N-type grid electrode (40).

4. A grounded-gate NMOS-type ESD device as claimed in claim 3, wherein: and a metal silicide (30) extraction electrode above the first high-concentration P-type doping (20), the first high-concentration N-type doping (24) and the N-type grid (40) forms the cathode.

5. A grounded-gate NMOS-type ESD device as claimed in claim 4, wherein: the first high concentration N-type dopant (24) is a source of the grounded-gate NMOS ESD device, the second high concentration N-type dopant (26) is a drain of the grounded-gate NMOS ESD device, and the N-type gate (40) is a gate of the grounded-gate NMOS ESD device.

6. A grounded-gate NMOS-type ESD device as claimed in claim 5, wherein: the floating second high concentration P-type dopant (22) and the low voltage P-well (70) and the second high concentration N-type dopant (26) together form a reverse P-i-N diode.

7. A grounded-gate NMOS-type ESD device as claimed in claim 6, wherein: adjusting the spacing S of the floating second high concentration P-type doping (22) and second high concentration N-type doping (26) of the reverse P-i-N diode to lower the breakdown voltage of the drain of the grounded-gate NMOS ESD device.

8. A method for realizing a grounded-gate NMOS ESD device is characterized in that: according to the method, a P-type anti-static implanted layer (28) below an existing grid grounded NMOS type ESD device is removed, floating second high-concentration P-type doping (22) is added on the outer side of the second high-concentration N-type doping (26), a source electrode, a grid electrode and the first high-concentration P-type doping (20) are connected together to form a cathode, and a metal silicide (30) leading-out electrode above the second high-concentration N-type doping (26) forms an anode, so that the grid grounded NMOS type ESD device is obtained.

9. The method of claim 8, wherein the method comprises:

step S1, providing a semiconductor substrate (80);

a step S2 of generating a low-voltage P well (70) on the semiconductor substrate (80);

step S3, sequentially generating a first high-concentration P-type doping (20), a first high-concentration N-type doping (24), a second high-concentration N-type doping (26) and a floating second high-concentration P-type doping (22) on the low-voltage P well (70), wherein a non-metal silicide (50) is arranged right above the second high-concentration N-type doping (26) and close to the first high-concentration N-type doping (24), a metal silicide (30) is arranged right above the second high-concentration N-type doping (26) and close to the floating second high-concentration P-type doping (22), and a gate oxide layer and an N-type gate (40) are generated above an active region between the first high-concentration N-type doping (24) and the second high-concentration N-type doping (26);

and step S4, connecting the first high-concentration N-type doping (24), the N-type grid electrode (40) and the first high-concentration P-type doping (20) together to form a cathode, and forming an anode by the metal silicide 30 extraction electrode above the second high-concentration N-type doping (26).

10. A method of implementing a grounded-gate NMOS-type ESD device as claimed in claim 9, wherein: the floating second high-concentration P-type doping (22), the low-voltage P well (70) and the second high-concentration N-type doping (26) form a reverse P-i-N diode together, and the breakdown voltage of the drain of the grid-grounded NMOS ESD device is adjusted and reduced by adjusting the distance S between the floating second high-concentration P-type doping (22) and the second high-concentration N-type doping (26) of the reverse P-i-N diode.

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a Grounded-Gate NMOS (GGNMOS) type ESD device and a method for implementing the same.

Background

In the field of integrated circuit anti-static protection design, an anti-static protection design window generally depends on working voltage and Gate Oxide (GOX) thickness of an internal protected circuit, and taking a 55LP advanced process platform of a certain company as an example, the working voltage of a core device (1.2V MOSFET) is 1.2V, and the gate oxide thickness is 26A (angstroms, 0.1nm), so the anti-static protection design window of the core device (1.2V MOSFET) of the 55LP advanced process platform of the company is generally between 1.32V and 5.2V. However, as shown in fig. 1, the hysteresis effect characteristic curve of the anti-static protection GGNMOS device of the 55LP advanced process platform core device (1.2V NMOS) of the company shows that the trigger voltage (Vt1, voltage corresponding to the inflection point at the lower position of the right curve) of the GGNMOS device is 6.85V, which exceeds the anti-static protection design window of the core device, and if the GGNMOS device is directly used for the anti-static protection design of the core device (1.2V NMOS), the reliability problem of the gate oxide layer of the core device (1.2VMOSFET) is easily caused.

As to how to adjust and lower the trigger voltage Vt1 of a GGNMOS (Grounded-Gate NMOS), the industry generally adds a P-type ESD IMP under the drain of the GGNMOS, and the specific device structure diagram is shown in fig. 2.

The prior art GGNMOS includes a Shallow Trench Isolation (STI) 10, a high-concentration P-type dopant (P +)20, a high-concentration N-type dopant (N +)24, a high-concentration N-type dopant (N +)26, a P-type anti-static implant (P-type ESD IMP)28, a low-voltage P-Well (LV-P-Well)70, a P-type substrate (P-Sub)80, an N-type gate (N-Poly)40, a non-metal Silicide 50, and a plurality of metal silicides (Silicide)30 connecting the doped regions and the electrodes.

The whole ESD device is arranged on a P-type substrate (P-Sub)80, a low-voltage P-Well (LV-P-Well)70 is generated on the P-type substrate (P-Sub)80, a high-concentration P-type doping (P +)20 and a high-concentration N-type doping (N +)24 are sequentially arranged on one side of the low-voltage P-Well (LV-P-Well)70 from outside to inside, a Shallow Trench Isolation (STI) 10 is arranged between the high-concentration P-type doping (P +)20 and the high-concentration N-type doping (N +)24, and the outer side of the high-concentration P-type doping (P +)20 is a part of the low-voltage P-Well (LV-P-Well) 70; arranging a high-concentration N-type doping (N +)26 on the other side of the low-voltage P Well (LV-P-Well)70, wherein the outer side of the high-concentration N-type doping (N +)26 is a part of the low-voltage P Well (LV-P-Well)70, and arranging a P-type anti-static implantation layer (P-type ESD IMP)28 on the outer side right below the high-concentration N-type doping (N +) 26; a part (active region) of the low-voltage P Well (LV-P-Well)70 is located between the high-concentration N-type doping (N +)24 and the high-concentration N-type doping (N +)26, and a gate oxide (usually, the gate oxide of the gate is present by default and is not shown in the figure) and an N-type gate (N-Poly)40 are disposed above the high-concentration N-type doping (N +)24 and the high-concentration N-type doping (N +) 26; the inner side right above the high concentration N-type doping (N +)26 is a non-metal Silicide 50, the outer side right above the high concentration N-type doping (N +)26 is a metal Silicide (Silicide)30, and the metal Silicide (Silicide)30 is respectively generated above the high concentration P-type doping (P +)20 and the high concentration N-type doping (N +) 24.

The high-concentration N-type doping (N +)24 is the Source (Source) of the GGNMOS device, the high-concentration N-type doping (N +)26 is the Drain (Drain) of the GGNMOS device, and the N-type grid (N-Poly)40 is the grid (Gate) of the GGNMOS device.

The metal silicide 30 extraction electrode above the high concentration P-type doping (P +)20, the high concentration N-type doping (N +)24, and the N-type gate (N-Poly)40 forms the Cathode of the GGNMOS device, and the metal silicide 30 extraction electrode outside above the high concentration N-type doping (N +)26 forms the Anode of the GGNMOS device.

However, in order to save a mask in the process, the P-type ESD IMP under the drain of the GGNMOS of the core device and the P-type ESD IMP under the drain of the GGNMOS of the IO device are often added at the same time and share one mask, and the ion implantation dose of the P-type ESD IMP is often determined by the trigger voltage Vt1 of the GGNMOS of the IO device, this tends to result in the P-type ESD IMP being added even under the drain of the core device GGNMOS, the drop of the trigger voltage is still very limited, fig. 3 is a hysteresis effect curve of the core device GGNMOS with the P-type ESD IMP added under the existing drain, and it can be derived from the hysteresis effect curve that the trigger voltage Vt1 is only reduced from 6.85V to 6.7V, still greater than 5.2V, and cannot be directly applied to the anti-static protection design of the 1.2V (core) device, there is therefore a need to find a better way to reduce the trigger voltage of a 1.2V (core) GGNMOS device.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention aims to provide a grounded-gate NMOS type ESD device and an implementation method thereof, and the grounded-gate NMOS type ESD device is implemented by removing a P-type anti-static implant layer 28 below an original high-concentration N-type doped (N +)26 and adding a floating P-type heavily doped region (i.e. high-concentration P-type doped) (P +)22 outside the high-concentration N-type doped (N +)26 on the basis of the existing grounded-gate NMOS type ESD device, so that the trigger voltage of the novel GGNMOS device is reduced, and the novel GGNMOS device can be directly applied to the anti-static protection design of a core device (1.2V).

To achieve the above and other objects, the present invention provides a grounded-gate NMOS-type ESD device, comprising:

a semiconductor substrate (80);

a low voltage P-well (70) created on the semiconductor substrate (80);

a first high-concentration P-type doping (20), a first high-concentration N-type doping (24), a second high-concentration N-type doping (26) and a floating second high-concentration P-type doping (22) are sequentially generated on the low-voltage P well (70), a non-metal silicide (50) is arranged on the part, close to the first high-concentration N-type doping (24), right above the second high-concentration N-type doping (26), and a metal silicide (30) is arranged on the part, close to the floating second high-concentration P-type doping (22), right above the second high-concentration N-type doping (26);

a gate oxide and an N-type gate (40) formed over the active region between the first high concentration N-type doping (24) and the second high concentration N-type doping (26);

the first high-concentration N-type doping (24), the N-type grid electrode (40) and the first high-concentration P-type doping (20) are connected together to form a cathode, and the metal silicide 30 leading-out electrode above the second high-concentration N-type doping (26) forms an anode.

Preferably, a shallow trench isolation (10) is disposed between the first high concentration P-type dopant (20) and the first high concentration N-type dopant (24).

Preferably, metal silicide (30) is respectively generated above the first high-concentration P-type doping (20), the floating second high-concentration P-type doping (22), the first high-concentration N-type doping (24) and the N-type grid electrode (40).

Preferably, a metal silicide (30) extraction electrode above the first high concentration P-type doping (20), first high concentration N-type doping (24) and N-type gate (40) constitutes the cathode.

Preferably, the first high concentration N-type dopant (24) is a source of the grounded-gate NMOS-type ESD device, the second high concentration N-type dopant (26) is a drain of the grounded-gate NMOS-type ESD device, and the N-type gate (40) is a gate of the grounded-gate NMOS-type ESD device.

Preferably, the floating second high concentration P-type doping (22) and the low voltage P-well (70) and the second high concentration N-type doping (26) together form an inverse P-i-N diode.

Preferably, the breakdown voltage of the drain of the grounded-gate NMOS ESD device is reduced by adjusting the spacing S of the floating second high concentration P-type doping (22) and second high concentration N-type doping (26) of the reverse P-i-N diode.

In order to achieve the purpose, the invention also provides a method for realizing the grid-grounded NMOS ESD device, which removes a P-type anti-static implanted layer (28) below the existing grid-grounded NMOS ESD device, adds a floating second high-concentration P-type doping (22) outside a second high-concentration N-type doping (26), connects a source electrode, a grid electrode and the first high-concentration P-type doping (20) together to form a cathode, and leads out an electrode from a metal silicide (30) above the second high-concentration N-type doping (26) to form an anode, thereby obtaining the grid-grounded NMOS ESD device.

Preferably, the method further comprises:

step S1, providing a semiconductor substrate (80);

a step S2 of generating a low-voltage P well (70) on the semiconductor substrate (80);

step S3, sequentially generating a first high-concentration P-type doping (20), a first high-concentration N-type doping (24), a second high-concentration N-type doping (26) and a floating second high-concentration P-type doping (22) on the low-voltage P well (70), wherein a non-metal silicide (50) is arranged right above the second high-concentration N-type doping (26) and close to the first high-concentration N-type doping (24), a metal silicide (30) is arranged right above the second high-concentration N-type doping (26) and close to the floating second high-concentration P-type doping (22), and a gate oxide layer and an N-type gate (40) are generated above an active region between the first high-concentration N-type doping (24) and the second high-concentration N-type doping (26);

and step S4, connecting the first high-concentration N-type doping (24), the N-type grid electrode (40) and the first high-concentration P-type doping (20) together to form a cathode, and forming an anode by the metal silicide 30 extraction electrode above the second high-concentration N-type doping (26).

Preferably, the floating second high concentration P-type doping (22) and the low voltage P-well (70) and the second high concentration N-type doping (26) together form a reverse P-i-N diode, and the breakdown voltage of the drain of the gate-grounded NMOS type ESD device is adjusted to be reduced by adjusting the spacing S of the floating second high concentration P-type doping (22) and the second high concentration N-type doping (26) of the reverse P-i-N diode.

Compared with the prior art, the grid grounding NMOS ESD device and the realization method thereof remove the Drain (Drain) of the prior GGNMOS ESD device, namely the P-type anti-static implantation layer 28 below the high-concentration N-type doping (N +)26, and add the floating P-type heavily doped region (high-concentration P-type doping) (P +)22 outside the Drain (Drain) thereof, so that the floating P-type heavily doped region (P +)22, the low-voltage P well 70 and the Drain form a reverse P-i-N diode together, and the breakdown voltage of the Drain (Drain) of the GGNMOS ESD device is adjusted and reduced by adjusting the distance S between the P end (P +)22 of the reverse P-i-N diode, namely the floating P-type heavily doped region (P +)22 and the N end, namely the high-concentration N-type doping (N +)26, thereby reducing the trigger voltage 1 of the novel GGNMOS ESD device, the novel GGNMOS ESD device can be directly suitable for the anti-static protection of a core device (1.2V), and meanwhile, as the novel GGNMOS ESD device does not need P-type ESD (impact resistance) IMP, a photomask can be saved, and the process cost is reduced.

Drawings

FIG. 1 is a 1.2V GGNMOS hysteresis effect characteristic curve of a company 55LP process platform;

fig. 2 is a structural diagram of a grounded-gate NMOS type ESD device of the prior art;

FIG. 3 is a hysteresis effect curve of a GGNMOS type ESD device in the prior art;

FIG. 4 is a diagram of a device structure of a grounded-gate NMOS ESD device according to a preferred embodiment of the present invention;

FIG. 5 is a plot of hysteresis effect of a GGNMOS type ESD device of the present invention;

FIG. 6 is a flowchart illustrating the steps of a method for implementing a grounded-gate NMOS ESD device according to the present invention;

fig. 7 is a schematic view of an application scenario of the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

Fig. 4 is a device structure diagram of a grounded-gate NMOS type ESD device according to a preferred embodiment of the present invention. As shown in fig. 4, a grounded-gate NMOS type ESD device of the present invention includes: shallow Trench Isolation (STI) 10, high-concentration P-type dopant (P +)20, floating high-concentration P-type dopant (P +)22, high-concentration N-type dopant (N +)24, high-concentration N-type dopant (N +)26, low-voltage P-Well (LV-P-Well)70, P-type substrate (P-Sub)80, gate oxide (usually, gate oxide of gate is present by default, none of which is shown) and N-type gate (N-Poly)40, non-metal Silicide 50, and metal Silicide (Silicide)30 connecting the doped region and the electrode.

The whole ESD device is arranged on a P-type substrate (P-Sub)80, a low-voltage P Well (LV-P-Well)70 is generated on the P-type substrate (P-Sub)80, a high concentration P-type doping (P +)20, a high concentration N-type doping (N +)24, a high concentration N-type doping (N +)26, and a floating high concentration P-type doping (P +)22 are sequentially disposed on a low voltage P-Well (LV-P-Well)70, and specifically, a high concentration P-type doping (P +)20 and a high concentration N-type doping (N +)24 are sequentially arranged from the outside to the inside on one side of a low voltage P-Well (LV-P-Well)70, a Shallow Trench Isolation (STI) 10 is disposed between the high-concentration P-type doping (P +)20 and the high-concentration N-type doping (N +)24, and the outside of the high-concentration P-type doping (P +)20 is a part of a low-voltage P-Well (LV-P-Well) 70; the high-concentration N-type doping (N +)26 and the floating high-concentration P-type doping (P +)22 are sequentially arranged on the other side of the low-voltage P Well (LV-P-Well)70 from inside to outside, the distance between the high-concentration N-type doping (N +)26 and the floating high-concentration P-type doping (P +)22 is S, and the outer side of the floating high-concentration P-type doping (P +)22 is a part of the low-voltage P Well (LV-P-Well) 70; a part (active region) of a low-voltage P Well (LV-P-Well)70 is arranged between the high-concentration N-type doping (N +)24 and the high-concentration N-type doping (N +)26, and a gate oxide layer and an N-type grid (N-Poly)40 are arranged above the low-voltage P Well (LV-P-Well); a non-metal Silicide 50 is arranged on the part, close to the high-concentration N-type doping (N +)24, right above the high-concentration N-type doping (N +)26, a metal Silicide 30 is arranged on the part, close to the floating high-concentration P-type doping (P +)22, right above the high-concentration N-type doping (N +)26, and the metal Silicide 30 is respectively generated on the parts, close to the floating high-concentration P-type doping (P +)22, the floating high-concentration N-type doping (N +)24 and the N-type grid (N-Poly)40, of the high-concentration P-type doping (P +) 20.

The high concentration N-type doping (N +)24 is the Source (Source) of the GGNMOS device of the present invention, the high concentration N-type doping (N +)26 is the Drain (Drain) of the GGNMOS device of the present invention, and the N-type Gate (N-Poly)40 is the Gate (Gate) of the GGNMOS device of the present invention.

The metal silicide 30 extraction electrode above the high concentration P-type doping (P +)20, the high concentration N-type doping (N +)24 and the N-type gate (N-Poly)40 constitutes the Cathode of the GGNMOS type ESD device of the present invention, and the metal silicide 30 extraction electrode above the high concentration N-type doping (N +)26 constitutes the Anode of the GGNMOS type ESD device of the present invention.

In the invention, on the basis of the GGNMOS ESD device added with the P-type ESD IMP shown in FIG. 2, the P-type anti-static implantation layer (P-type ESD IMP)28 below the original Drain (Drain), i.e. the high-concentration N-type doping (N +)26 is removed, and a floating P-type heavily doped region (i.e. high-concentration P-type doping) (P +) 22), a Source (Source), i.e. the high-concentration N-type doping (N +)24, a Gate (Gate), i.e. N-type Gate (N-Poly)40 and the high-concentration P-type doping (P +)20 are connected together to form a Cathode Cathode, and the floating P-type heavily doped region (P +)22, a low-voltage P-Well (LV-P-Well)70 and a Drain (Drain), i.e. the high-concentration N-type doping (N +)26 form a reverse P-i-N diode by adjusting the P-type P-i-N diode, i.e. the floating P-type heavily doped region (P +)22 and the Drain (Drain the reverse P-i-N-type heavily doped region (P +)22 and the high-N + doped region The N end, namely the distance S of the high-concentration N-type doping (N +)26 is adjusted to reduce the breakdown voltage of the Drain (Drain) of the core GGNMOS device, so that the trigger voltage Vt1 of the novel GGNMOS ESD device is reduced, the novel GGNMOS ESD device can be directly suitable for the anti-static protection of the core device (1.2V), as shown in FIG. 5, the trigger voltage Vt1 corresponding to the inflection point at the lower position of the right side curve is lower than 5V, and the novel GGNMOS ESD device is suitable for being applied in the background technology.

Fig. 6 is a flowchart illustrating a method for implementing a grounded-gate NMOS ESD device according to the present invention. As shown in fig. 6, the method for implementing a grounded-gate NMOS ESD device according to the present invention includes the following steps:

in step S1, a semiconductor substrate, in this embodiment of the invention, a P-type substrate (P-Sub)80 is provided.

In step S2, a low voltage P-Well (LV-P-Well)70 is created on a P-type substrate (P-Sub) 80.

Step S3, sequentially disposing a high-concentration P-type dopant (P +)20, a high-concentration N-type dopant (N +)24, a high-concentration N-type dopant (N +)26, and a floating high-concentration P-type dopant (P +)22 on a low-voltage P-Well (LV-P-Well)70, specifically, sequentially disposing a high-concentration P-type dopant (P +)20 and a high-concentration N-type dopant (N +)24 on one side of the low-voltage P-Well (LV-P-Well)70 from the outside to the inside, disposing a Shallow Trench Isolation (STI) 10 between the high-concentration P-type dopant (P +)20 and the high-concentration N-type dopant (N +)24, and forming a part of the low-voltage P-Well (LV-P-Well)70 outside the high-concentration P-type dopant (P +) 20; the high-concentration N-type doping (N +)26 and the floating high-concentration P-type doping (P +)22 are sequentially arranged on the other side of the low-voltage P Well (LV-P-Well)70 from inside to outside, the distance between the high-concentration N-type doping (N +)26 and the floating high-concentration P-type doping (P +)22 is S, and the outer side of the floating high-concentration P-type doping (P +)22 is a part of the low-voltage P Well (LV-P-Well) 70; a part (active region) of a low-voltage P Well (LV-P-Well)70 is arranged between the high-concentration N-type doping (N +)24 and the high-concentration N-type doping (N +)26, and a gate oxide layer and an N-type grid (N-Poly)40 are arranged above the low-voltage P Well (LV-P-Well); a non-metal Silicide 50 is arranged on the part, close to the high-concentration N-type doping (N +)24, right above the high-concentration N-type doping (N +)26, a metal Silicide 30 is arranged on the part, close to the floating high-concentration P-type doping (P +)22, right above the high-concentration N-type doping (N +)26, and the metal Silicide 30 is respectively generated on the parts, close to the floating high-concentration P-type doping (P +)22, the floating high-concentration N-type doping (N +)24 and the N-type grid (N-Poly)40, of the high-concentration P-type doping (P +)20, the floating high-concentration P-type doping (P +) 22), the high-concentration N-type doping (N +)24 and the N-Poly)40

Step S4, the high concentration P-type doped (P +)20, the high concentration N-type doped (N +)24, and the metal silicide 30 extraction electrode above the N-type gate (N-Poly)40 form the Cathode of the GGNMOS ESD device of the present invention, and the metal silicide 30 extraction electrode above the high concentration N-type doped (N +)26 forms the Anode electrode of the GGNMOS ESD device of the present invention.

In the present invention, the high concentration N-type dopant (N +)24 is the Source (Source) of the GGNMOS device of the present invention, the high concentration N-type dopant (N +)26 is the Drain (Drain) of the GGNMOS device of the present invention, and the N-type Gate (N-Poly)40 is the Gate (Gate) of the GGNMOS device of the present invention.

It can be seen that, in the invention, on the basis of the GGNMOS ESD device with the P-type ESD IMP added in fig. 2, the P-type anti-static implant layer (P-type ESD IMP)28 under the original Drain (Drain), i.e. the high-concentration N-type doped region (N +)26 is removed, and the floating P-type heavily doped region (i.e. the high-concentration P-type doped region) (P +) 22), the Source (Source), i.e. the high-concentration N-type doped region (N +)24, the Gate (Gate), i.e. the N-type Gate (N-Poly)40 and the high-concentration P-type doped region (P +)20 are connected together to form the Cathode, and the floating P-type heavily doped region (P +)22, the low-P Well (LV-P-Well)70 and the Drain (Drain), i.e. the high-concentration N-type doped region (N +)26 are connected together to form the reverse P-i-N diode by adjusting the P-i-N diode, i-N diode P terminal (P +)22 And the N end, namely the distance S of the high-concentration N-type doping (N +)26 is used for adjusting and reducing the breakdown voltage of the Drain (Drain) of the core GGNMOS device, so that the trigger voltage Vt1 of the novel GGNMOS ESD device is reduced, and the novel GGNMOS ESD device can be directly suitable for the anti-static protection of the core device (1.2V).

When the GGNMOS ESD protection circuit is applied, the GGNMOS ESD device can be connected between an IO end and the ground for IO protection, the Anode of the GGNMOS ESD protection circuit is connected with the IO end, and the Cathode of the GGNMOS ESD protection circuit is grounded (Vss). The invention can also be connected between a Power supply and the ground to form a Power supply Clamp (Power Clamp), the Anode of the invention is connected with the positive end (Vdd) of the Power supply, and the Cathode of the invention is grounded (Vss), as shown in FIG. 7.

In summary, the invention relates to a grounded-gate NMOS ESD device and a method for implementing the same, wherein a floating P-type heavily doped region (P +)22 is added outside a Drain (Drain) of an existing GGNMOS ESD device by removing a P-type anti-static implant layer 28 below the Drain (Drain), i.e. a high-concentration N-type doped region (N +)26, so that the floating P-type heavily doped region (P +)22, a low-voltage P well 70 and the Drain form a reverse P-i-N diode, and the breakdown voltage of the Drain (Drain) of the GGNMOS ESD device is reduced by adjusting the distance S between the P-end, i.e. the floating P-type heavily doped region (P +)22, and the N-end, i.e. the high-concentration N-type doped region (N +)26 of the reverse P-i-N diode, so as to reduce the trigger voltage 1 of the novel GGNMOS ESD device of the invention, so that the novel GGNMOS ESD device of the invention can be directly applied to the anti-static protection of a core device (1.2V), meanwhile, the invention does not need P-type ESD (electro-static discharge) IMP (impact plasma), so that a photomask can be saved, and the process cost is reduced.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.