阅读说明：本技术 针对存储器设备的芯片选择信号读取操作的训练 (Training for chip select signal read operations for memory devices ) 是由 邬正龙 托尼亚·G·莫里斯 克里斯蒂娜·爵 丹尼尔·贝塞拉·佩雷斯 大卫·G·埃利斯 于 2019-05-24 设计创作，主要内容包括：可基于存储器设备所接收的CS信号的采样样本来确定向存储器设备提供的参考电压值和芯片选择(CS)信号时间延迟。可以针对各种参考电压以不同的时间延迟向存储器设备提供CS信号。来自存储器设备的CS信号的各种采样样本可指示CS信号的上升沿和下降沿的不同时间。可由CS信号的最迟出现的上升沿和最早出现的下降沿来生成复合信号眼。可基于与参考眼宽最接近的复合信号眼宽来选择参考电压值和时间延迟。(The reference voltage value and Chip Select (CS) signal time delay provided to the memory device may be determined based on sampled samples of a CS signal received by the memory device. The CS signal may be provided to the memory device with different time delays for various reference voltages. Various sampled samples of the CS signal from the memory device may indicate different times of rising and falling edges of the CS signal. The composite signal eye may be generated from the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and the time delay may be selected based on a composite signal eye width that is closest to the reference eye width.)

1. A host system, comprising:

a processor, and

a memory controller coupled to the processor, the memory controller to:

requesting a first reference voltage applied by a memory device;

during use of the first reference voltage by the memory device:

transmitting a Chip Select (CS) signal to the memory device after various delay amounts, and

receiving, from the memory device, sampled samples of the CS signal transmitted after the various amounts of delay;

requesting a second reference voltage applied by the memory device;

during use of the second reference voltage by the memory device:

transmitting the CS signal to the memory device after various delay amounts, and

receiving, from the memory device, sampled samples of the CS signal transmitted after the various amounts of delay, wherein the processor is to determine a reference voltage for the memory device based on a reference voltage that provides a composite eye width closest to a reference eye width, and determine a delay for transmitting the CS signal based on the composite eye width.

2. The host system of claim 1, wherein the processor is to: a composite eye for an applied reference voltage is determined based on sampled CS signals from a plurality of memory devices that are delayed for a plurality of applied CS signal transmissions.

3. The host system of claim 1, wherein:

the processor is to determine a first composite eye based on rising and falling edges of sampled samples of the CS signal transmitted during use of the first reference voltage by the memory device and after the various amounts of delay;

the processor is configured to select a latest rising edge and an earliest falling edge of the first composite eye;

the processor is to determine a second composite eye based on rising and falling edges of sampled samples of the CS signal transmitted during use of the second reference voltage by the memory device and after the various amounts of delay;

the processor is configured to select a latest rising edge and an earliest falling edge of the second composite eye; and is

The processor is to select the reference voltage associated with the compound eye from the first reference voltage and the second reference voltage, the compound eye being one of the first compound eye and the second compound eye that is closest to a reference eye width.

4. The host system of claim 3, wherein:

the processor is to select a transmission delay to be a time exactly in the middle of the composite eye width associated with the selected reference voltage.

5. The host system of claim 1, wherein the reference eye width comprises a memory clock cycle.

6. The host system of claim 1, comprising the memory device, and wherein the memory device comprises a one-tile Dynamic Random Access Memory (DRAM) device.

7. The host system of claim 1, wherein the processor is to initiate a CS signal training scheme compatible with joint committee for electronics engineering double data rate 5.

8. The host system of claim 1, wherein the processor is to set the sampled sample of the CS signal to provide a falling edge in place of an earliest rising edge in the event that the sampled sample of the CS signal includes a rising edge that is greater than a threshold distance from the rising edge.

9. The host system of claim 1, wherein the memory controller is to apply the determined offset prior to transmission of the CS signal, and the memory controller is to cause the memory device to apply the determined reference voltage.

10. A method, comprising:

starting a Chip Select (CS) training mode for a memory device of a tile;

setting a first reference voltage value for use by the memory device;

transmitting a CS signal to the tile with various amounts of time delay during use of the first reference voltage;

receiving sample samples of the CS signal with the various amounts of time delay from the memory device;

determining a first composite eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples from use of the first reference voltage;

setting a second reference voltage value for use by the memory device;

transmitting a CS signal to the tile with various amounts of time delay during use of the second reference voltage;

receiving, from the memory device, sampled samples of the CS signal associated with use of the second reference voltage and various amounts of time delay;

determining a second composite eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples from the use of the second reference voltage;

selecting a composite eye closest to the reference eye width;

selecting a reference voltage associated with the selected compound eye; and

determining a delay for transmission of the CS signal based on a midpoint of the composite eye.

11. The method of claim 10, wherein the reference eye width comprises a memory clock period.

12. The method of claim 10, wherein the tile comprises a tile of a Dynamic Random Access Memory (DRAM) device.

13. The method of claim 10, wherein the CS signal training pattern is compatible with joint committee for electronics engineering double data rate 5.

14. The method of claim 10, comprising:

determining that the sampled sample of the CS signal includes a rising edge that is greater than a threshold distance from an earliest rising edge, an

Setting a sample of the CS signal to provide a falling edge in place of the rising edge.

15. The method of claim 10, comprising:

applying the selected reference voltage by the memory controller, an

Applying, by the memory controller, the determined offset prior to transmission of the CS signal.

16. The method of claim 10, comprising:

starting a Chip Select (CS) training mode for a memory device of a second tile;

setting a first reference voltage value for use by memory devices of the second tile;

transmitting a CS signal to the memory devices of the second tile with various amounts of time delay during use of the first reference voltage by the memory devices of the second tile;

receiving, from the memory device, sampled samples of the CS signal with the various amounts of time delay from use of the first reference voltage by the memory devices of the second tile;

determining a first compound eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples of usage of the first reference voltage by memory devices from the second tile;

setting a second reference voltage value for use by memory devices of the second tile;

transmitting a CS signal to the tile with various amounts of time delay during use of the second reference voltage by memory devices of the second tile;

receiving, from the memory device, sampled samples of the CS signal with the various amounts of time delay from use of the second reference voltage by the memory devices of the second tile;

determining a second compound eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples of usage of the second reference voltage from memory devices of the second tile;

selecting a second compound eye closest to the reference eye width;

selecting a second reference voltage associated with the selected compound eye; and

determining a delay for transmission of the CS signal based on a midpoint of the second composite eye.

17. A system, comprising:

a host system comprising a processor, a memory controller, and a memory device, wherein the memory device is coupled to the processor, wherein:

the processor to cause application of one or more reference voltages by the memory device and cause transmission of a Chip Select (CS) signal delayed by a plurality of delay times during use of one or more of the reference voltages;

the processor is to receive sampled samples of the CS signal from a memory device;

the processor is to determine a composite eye for at least one of the reference voltages based on the sampling samples;

the processor is to select a reference voltage associated with a compound eye closest to a reference eye width; and is

The processor is configured to select a delay time before transmission of the CS signal based on a temporal offset from a midpoint of the composite eye closest to a reference eye width.

18. The system of claim 17, wherein the host system comprises a personal computer, a smartphone, a blade, a rack, or a server.

19. The system of claim 17, wherein the reference eye width comprises 2 UIs (unit interval).

20. The system of claim 17, wherein the processor is configured to initiate a joint committee on electronics engineering (eee) double data rate 5 (ddr) CS training mode.

Technical Field

Various examples described herein relate to setting a signal capture time in a memory device.

Background

A computing platform or system, such as one configured as a server, personal computer, or other computing device, may access a dual in-line memory module (DIMM). DIMMs may include various types of memory, including volatile or non-volatile types of memory. As memory technology has advanced to include memory cells with higher and higher densities, the memory capacity of DIMMs has also increased significantly. Furthermore, advances in the data rate for accessing memory included in a DIMM to be written to or read from enables a large amount of data to flow between requestors that need to be accessed and the memory devices included in the DIMM. A large number of memory devices may be coupled to the bus, with all memory devices having the same command interface.

Drawings

FIG. 1A depicts a block diagram of an example of a system having a host and a memory module.

FIG. 1B shows an example of a dual in-line memory module (DIMM) portion.

Fig. 2A depicts an example of a Chip Select (CS) signal transmitted at different transmission delay values.

Fig. 2B depicts a composite eye determination from signal transformation of a plurality of sample samples.

Fig. 3 depicts an example of samples of a CS signal, wherein one CS signal is subsequently modified to form a composite signal.

Fig. 4 depicts a composite eye calculation after modification of the sampled signal.

Fig. 5A and 5B depict a process that may be used to determine a propagation delay for a chip select signal and a reference voltage for a memory device for one tile.

Fig. 6 depicts a system.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Currently, there are various types of DIMMs. For example, in a server, Registered DIMMs (RDIMMs) may be used to buffer command addresses, controls, and clocks and to prepare for these operations before providing signals to the memory devices. Low load dimms (lrdimms) use buffers for the data bus, but also handle the load of many ranks (rank) of memory devices. A register-less DIMM (udimm) is a bufferless DIMM that does not have a separate buffer in front of the command address or data, and communication can occur directly with the memory device.

DIMMs are coupled to various interconnects and buses to enable communication with other devices, such as host devices. The host device may issue commands to the DIMM as well as receive responses from the DIMM. For example, a data bus, a command address bus, and control signal lines (e.g., Chip Select (CS) and Clock (CLK)) may be used to provide communication between the host and the DIMM. The host may issue a Chip Select (CS) signal to validate the command and indicate when the DIMM should "listen for" or read the Command Address (CA) information from the C/A bus. The CA information may include a command or an address. Commands may include write, read, row activate, row precharge, refresh, and mode register write. As the signal rate increases, the time region available for reading the CS signal between transitions of the CS signal is smaller.

Within a DIMM, the characteristics of the various memory devices, such as Dynamic Random Access Memories (DRAMs), may be different. For multiple memory devices, a Chip Select (CS) is sent to all memory devices. Due to different propagation delays, differences within the devices for the start time of sampling after entering the CS training mode, and other reasons, each memory device may experience different times when the CS is received and different times when the memory device receives the clock signal. When the memory device is in the CS training mode, the memory device may sample the CS bus using the memory device's clock signal on each rising edge of the clock and take a logical combination of 4 sample samples and send the sample samples back to the host on the DQ bus. But the sampled CS signal may vary from memory device to memory device due to different times of receipt of the CS signal and the clock signal. When a DIMM includes multiple memory devices and the same CS signal is transmitted to those memory devices, the CS signals read by the memory devices may be different. For example, the signal propagation delays of the CS signal to the various memory devices may be different. In addition, the clock signal used by a memory device to sample the CS signal may differ in phase or potentially frequency from the clock signal used by another memory device to sample the CS signal. For example, the CS signal is kept at a high level for 1 clock cycle and kept at a low level for 1 clock cycle. Some memory devices have feedback indicating a high value, while other memory devices provide feedback indicating that the CS signal is low. Thus, different memory devices in the DIMM may misread the CS signal and fail to determine when the C/A information was read or otherwise failed.

In known schemes for attempting to achieve accurate reading of the CS signal by the memory device using a clock signal, matching signal wiring on the board attempts to reduce the difference in the times at which the CS signal is received by the memory device. Another known solution includes a receive enabling method for joint committee for electronic device engineering double data rate 4(JEDEC DDR4) compliant UDIMM. For example, the receive enable (RCVEN) method for CS training is as follows: (1) the host controller sends a read command, (2) the host controller I/O samples the strobe return time for that read, and (3) repeats for all time delays of the CS to reveal when there is a cycle skip or no strobe directly for the strobe return time, and create a pass/fail scenario. Another known scheme includes a CS loopback mode for DDR4 Register Clock Drivers (RCDs). RCD is also a training mode in RCD implemented for DDR 4.

These schemes do not utilize Dynamic Random Access Memory (DRAM) training mode capabilities and rely on functional operation during training. Functional training refers to using a sequence of regular functional commands to get feedback from the memory device, rather than a special training pattern. One example of functional training is the RCVEN training described above. The RCD has similar capabilities as the receive enable mode but does not support multiple DRAM components.

JEDEC committee JC42.3, entry number: 1848.99D, DDR5 full Specification draft Rev0.83 provides loopback functionality for training mode. Various embodiments provide for Chip Select (CS) training of DDR5 compliant DRAMs (or other standard or volatile or non-volatile memory devices) for one or more partitions. A tile may include one or more memory devices. For example, various embodiments may be used in connection with LPDDR5(LPDDR version 5), HBM2(HBM version 2), and/or other older or newer technologies that are derived or extended based on such specifications. Various embodiments allow for: providing a CS signal having various time offset values to a tile for one or various applied reference voltage (Vref) values; determining a transformation of a CS signal read by a memory device of the tile; and selecting an applied Vref for the memory device for the tile and a time delay for the CS signal to center the memory device clock within a CS signal assertion time (assertion time). By providing the CS signal at different time offsets, various embodiments can learn when memory devices in one tile read the active and inactive portions of the CS signal. Various embodiments provide one point in time as follows: this point in time is used by the host so that all memory devices in one tile accurately read the CS signal. Thus, the accuracy of the reading of the CS signal by the memory devices of one or more slices can potentially be improved. Various embodiments may be performed by firmware, a basic input/output system (BIOS) executed by a processor, and/or firmware on a microcontroller.

Various embodiments provide the following processes: this process acts as an outer loop applying different time delays to the CS signal for varying the reference voltage (Vref) value to find the duty cycle and eye width for the CS signal. The Vref value is used to compare the analog value read by the memory device to determine whether a 1 or 0 is being transmitted. If the memory device reads a CS signal value above Vref at the sample, then the value is determined to be one or asserted (asserted), otherwise the value is determined to be zero or not asserted (unasserted).

Various embodiments may potentially improve the CS training pattern and determine an eye (e.g., eye width) for sampling the CS signal during CS training that is likely to result in an accurate reading of the CS signal by the memory devices of one tile. Thus, the higher frequencies (e.g., CS and clock signals) in DDR5 and other specifications may be used while allowing the CS signals to be properly read and used by multiple memory devices in a tile.

FIG. 1A depicts a block diagram of an example of a system having a host and a memory module. Various embodiments may be used in the following systems: the system has a host and DIMMs (e.g., UDIMM, backside RCD with RDIMM, LRDIMM, or other DIMM or arrangement of memory devices) or other types of volatile or non-volatile memory devices (which may or may not be double data rate). Host 100 may access DIMM 150 via a wired or wireless medium or interconnect using signal lines.

Control logic 102 may determine a time delay to apply for a memory device transmitting or issuing a CS signal to one tile. Control logic 102 may determine Vref to be applied by the memory devices of a tile. The control logic 102 may be implemented as one or more of the following: firmware, a BIOS executed by a processor, and/or firmware on the microcontroller 104. The memory controller 104 may issue the CS command to the memory devices of one sector (e.g., sector 152-0 or 152-1). More or fewer tile memory devices may be used. An example sequence of operations is described next for host 100 to determine the CS signal propagation delay and Vref values. For example, the control logic 102 may cause the system to perform one or more of the actions 161-164. In other examples, DIMM 150 may be programmed to determine one or both of the CS signal transmission delay or the Vref value.

At 161, the memory controller 106 begins CS training for the memory devices of the target tile. For example, memory controller 106 may apply a target Vrefn in a DRAM mode register for use by memory devices of a tile, enable a CS training mode for the tile, transmit a CS signal for various transmission delay values, and receive training feedback via a DQ pin. In this example, the tile 152-1 has CS training applied. Vref can be varied by: a low frequency command is sent that does not require the CS to be trained and the command to change Vref is captured using the same command and CS interface but using multiple clock cycles.

At 162, the memory controller 106 causes the CS signals to be transmitted to the memory devices of one tile at various transmission time delay values (e.g., 0 to X, in increments of 1/128 tCK) for the same tile. Various transfer time delays may be imposed for the transfer of the CS signal to the memory device of one tile for the applied Vref value. The Vref value may be changed to a different value and various transfer time delays may be imposed on the transfer of the CS signal to the memory device of one tile.

At 163, for some or all of the applied Vref values, a composite eye is determined based on training feedback for the CS signals sent at various transmission delays and the applied Vref values. The composite eye may be determined from sampled samples of the CS signal fed back from multiple memory devices. The composite eye may take into account differences between different memory devices in the tile during the sampling period. The composite eye may be determined based on a rising edge (e.g., a left edge) occurring the latest (in time) and a falling edge (e.g., a right edge) occurring the earliest (in time) selected from the CS signal sample samples from the plurality of memory devices. The composite eye may represent a region where the CS signal transitions are not measured by any memory device in one tile, and may represent a region where the probability of misinterpreting the CS signal is low (because the CS signal is unlikely to change during the composite eye).

At 164, the propagation delay and Vref for the CS signal to be applied in one tile is selected based on the propagation delay and Vref whose composite eye is closest to the ideal or reference eye width. For example, act 164 may include calculating absolute differences between various composite eye widths (for different Vref values) and the CS Unit Interval (UI). The representation of the calculation may be as follows.

Eye width offset (CA Vrefn) ═ eye width (CS Vrefn) -CS UI |, where: the CS UI may be an ideal or reference eye width as specified in JEDEC DDR5, although other ideal or reference eye widths may also be used. Act 164 may also include summing the eye width shifts for a plurality (e.g., three or other number) of Vref positions. Summing several (e.g., 3 or another number) eye-width offset values can average the effects of noise for any single measurement as a way of filtering measurements for multiple Vref levels (which are expected to be similar). An example manner of how the eye width offset is determined is described later.

Fig. 1B shows an example of DIMM portion 200. In some examples, DIMM portion 200 may represent a first side of two sides of the DIMM configured as an LRDIMM supported by a single register (e.g., register 210). A complete DIMM may include an equal number of memory devices 222 and buffers 230-1 through 230-3 on a second or back side. Examples are not limited to DIMMs configured with LRDIMMs with buffers 230-1 through 230-3. In other examples, other types of DIMM configurations (such as, but not limited to RDIMM configurations) may be applicable.

According to some examples, buffers 230-1 to 230-3 may be data buffers controlled by logic and/or features of registers 210 to route data associated with requests to access or control memory device 222 via a BCOM 0 bus based on commands received from a host computing device in response to various signals received from the host computing device (not shown). For these examples, at least a portion of the signals from the host computing device may be received by the register 210 via a Chip Select (CS) CS 0251, CS 0252, Chip Identification (CID)253, or command/address (CA) 254. For these examples, each memory device included in memory device 222 may be a DRAM memory device and may be coupled with a respective buffer 230-1 to 230-3 via a 4-bit (b) data bus. Buffers 230-1 through 230-3 may transfer data to a host computing device via data bus 240, or may be such that buffers 230-1 through 230-3 have internal resistance termination (RTT) when the respective memory devices coupled to these buffers are not being accessed. Examples are not limited to DRAM memory devices or 4b data buses. Different memory devices with different size data buses (e.g., 8b) are contemplated. Further, the examples are not limited to ten memory devices per tile or five buffers total per side of the DIMM. The examples are also not limited to DIMMs with a total of 4 die regions. In some examples, 2, 3, or more than 4 tiles are contemplated.

According to some examples, memory device 222 may be disposed in multiple slices shown in FIG. 1B, such as slice 0, slice 1, slice 2, or slice 3. Slice 0, slice 1, slice 2, or slice 3 may be controlled or accessed based on the respective activated CS output from register 210 via CS 0211, CS 1212, CS 2213, and CS 3214, and the CA signal output from register 210 via CA 254. In some examples, registers 210 may include logic and/or features to determine which tiles to access or control based on signals received from a host computing device (e.g., a host controller) via CS 0251, CS 0252, CID 253, or CA 254. Further, this logic may include CKE encoding to allow certain commands received from the host computing device (e.g., power save commands) to be broadcast to all the tiles, or may include ODT encoding for the DIMM to determine whether to terminate or cause RTT on the device or host side of the data bus 240.

Fig. 2A depicts an example of CS signals transmitted at different transmission delay values. The actual sampling of the CS signal by the CLK may be due to a special training pattern enabled in the memory device. This feedback of sample samples to the host may be a logical combination of several sample samples and may be sent back to the host via the data bus. Multiple memory devices in a DIMM may receive the CS signal with different amounts of time delay, sample the CS signal, and provide the sampled samples to a host. The host may determine the CS signal measured by the memory device based on the sampled samples.

Fig. 2B depicts an example of a composite eye from CS signal sample samples that are based on a CS signal transmitted with different amounts of time delay. For example, DRAM 0 through DRAM N of one tile may receive a transmitted Chip Select (CS) signal. The host device may transmit the CS signal at an increased level of transmission delay (from zero to a maximum level). DRAM 0 through DRAM N may provide the host with sampled samples of the CS signal received at different levels of transmission delay. The waveforms shown in fig. 2 indicate the active and inactive regions of the CS signal that DRAM 0 through DRAM N sample and feed back to the host for a particular applied Vref value. For example, signal DRAM 0 may use a clock signal to represent sampled samples of the CS signal. Likewise, the sampled samples taken by DRAM 1 and DRAM N may use a clock signal to represent the sampled samples of the CS signal. The sampled samples show that the CS signals measured by DRAMs 0-N are offset from each other due to at least differences in signal propagation and applied clock signals.

For applied Vref, the composite eye may be determined as the last occurring rising (e.g., left) edge and the earliest occurring (e.g., right) falling edge of the CS signal sampled for all DRAMs in the tile. The compound eye may be used by the host to determine an offset relative to the center of the compound eye. The offset from the center of the composite eye may be used as a transfer delay at which the host transfers the CS signal to one or more memory devices (e.g., DRAMs) of a tile for a particular applied Vref value. A single location may be determined based on the transition of the sampled CS signals from DRAM 0 to DRAM N, which CS time will be used for all DRAMs in a tile. The center of the compound eye represents the point: at this point, the CS signal is likely to be correctly read by all DRAM devices in one tile. The time offset may be determined for each or some of the tiles. Multiple CS signals may be sent to the DRAMs of different tiles, each with a determined CS signal propagation delay offset of zero or greater than zero.

Fig. 3 depicts an example of samples of a CS signal, wherein one CS signal is to be modified to form a correct composite signal. As in the example of fig. 2B, the DRAM provides sampled samples of the CS signal with various applied transmission offsets. In the case of DRAM 2, the left edge (rising) of the sampled CS signal is offset relative to the left edges of the sampled CS signals of the other DRAM devices. For example, if the left edge of the temporally earliest rising edge of the CS signal is more than a threshold distance from the rising edge of another sampled CS signal, the other sampled CS signal may be modified such that the left (rising) edge is changed to a right (falling) edge, and a new left (rising) edge is calculated. The pseudo code for determining whether to modify the left and right edges may be as follows.

If (left edge-minimum left edge of DRAM N) > (minimum left edge- (right edge of DRAM N-2 CS UIs)))) front end

New left edge of DRAM N-2 CS UIs on the right edge of DRAM N

New right edge of DRAM N-left edge of DRAM N

}

The smallest (leftmost) left edge of the sampled CS signal from a DRAM device in a tile is determined. If the minimum left edge subtracted by the left eye edge of DRAM device N is greater than the minimum left edge minus the right eye edge of DRAM device N minus the value of 2 CS UIs, then for this device the right edge will be changed to its current left edge and the left edge will be its current right edge minus the value of 2 CS UIs. The 2 CS UIs may represent a reference eye width (e.g., a distance between signal transitions). To determine the composite eye for that tile for the applied Vref value, the largest (rightmost) left edge and the smallest (leftmost) right edge of all DRAM devices are used.

Fig. 4 depicts the composite eye calculation after modifying the left and right edges of the signal. In this example, the left and right edges of the sampled CS signal for DRAM 2 are determined and used to determine the composite signal. The composite left and right edges are selected as the latest (in time) left (rising) edge and the earliest (in time) right (falling) edge.

Fig. 5A and 5B depict a process that may be used to determine a propagation delay for a chip select signal and a reference voltage for one or more memory devices of a tile. This process may be used by the host to determine the delay to be imposed on the transmission of the CS signal to one or more DRAM devices of a tile. Other types of volatile or non-volatile memory may be included in a tile, including cache, Static Random Access Memory (SRAM), NAND, 3D NAND or the likeOptane orOne or more of Z-NAND or the like memory. The process may also be used to determine a reference voltage (Vref) for use by the memory devices of a tile. The determined delay for a tile may be determined by applying one or more Vref values and transmitting the CS signal to the tile at different offset values. The reference voltage and delay whose eye width offset sum is closest to the reference eye width may be selected for chip selection to the tileAnd (5) signal transmission. The delay may be chosen to be the midpoint of the eye time center.

At 502, a tile is selected for which a Chip Select (CS) signal is to be trained. For example, the tile with the lowest identifier or index may be selected first. For example, tile 0 may be selected first, and tile 0 may have a corresponding chip select signal of CS 0. A partition may be a group of one or more DRAM devices that are accessed simultaneously (e.g., read from or write to these devices).

At 504, a Vref value is set for the selected tile. The Vref value may be set by selecting from a set of Vref values. Vref may be a reference voltage used by the memory device to distinguish between a 0 value or a 1 value when sampling the received CS signal.

At 506, the DRAM devices of the selected tile are placed into a CS training mode. An example of a CS training mode is described in connection with the JEDEC DDR5 specification. To place one or more DRAM devices of a slice into a CS training mode, the host may send a multipurpose command (MPC) to the slice to place the slice into the CS training mode.

At 508, a delay offset is applied to the CS signal prior to transmission to the selected tile. For example, the first delay offset may be zero and the subsequent delay offset may be incremented by 1/128tCK, where tCK represents a clock period. For example, the frequency per tCK may be 1600MHz, and the tCK 625 ps; 2000MHz, tCK 500 ps; or 3200MHz, tCK 312.5 ps.

At 510, training feedback from the transmitted CS signal is read. According to JEDEC DDR5, the slice sends 4 samples of the CS signal to the host using the DQ lines. JEDEC DDR5 Full Spec Draft rev0.83, fig. 81, and table 97 describe ways to understand the way in which sample samples are read to determine the value of the CS signal. For example, a determined value of the CS signal transmitted using the applied delay offset may be used to construct a portion of the sampled CS signal, and a plurality of sampled samples determined across a plurality of applied delay offsets may be used to construct the sampled CS signal. An example of sampling the CS signal is shown in fig. 2B.

At 512, it is determined whether all CS signal delay offset values have been tested. For example, for a first iteration of 508 through 510, a first delay offset is applied to the CS signal, and if there is another delay offset that can be tested, then 508 may follow 512. For example, if all available delay offset values have been tested, then the process proceeds to 514.

At 514, the process calculates the CS signal composite eye for all DRAM devices in a tile and stores the training results. The CS signal composite eye may be determined across all available delay offset values applied to the CS signal for a particular reference voltage value (Vref). For example, for applying a value of Vref, a CS signal composite eye may be determined based on the last occurring rising (e.g., left) edge and the earliest occurring (e.g., right) falling edge of the CS signal sampled for all DRAM devices in the tile. An example manner for determining a compound eye is described with respect to fig. 2B.

At 516, the process exits the CS training mode for the current tile. For example, to exit the CS training mode for a parcel, the host may send an MPC command to the parcel to disable the CS training mode.

At 518, the process determines whether all reference voltage (Vref) values have been applied to the DRAM devices of the tile. If not all reference voltage values have been tested for the current tile, the process continues to 504, where a next reference voltage value is selected at 504 and applied for the next iteration of 506 and 516. If all reference voltage (Vref) values have been tested for the tile, the process continues to 520. In some examples, a single Vref value may be used and does not change for different CS delay offset values applied to memory devices in one tile.

At 520, the process determines whether all CS signals and corresponding tiles have been tested using all available reference voltage values and available delay offset values. If all CS signals and corresponding tiles have been tested using all available reference voltage values and available delay offset values, the process continues to 522. If the CS signal and corresponding tile have not been tested using all available reference voltage values or available delay offset values, the process returns to 502.

At 522, a reference voltage (Vref) and a delay offset value to be applied is determined for each CS signal provided to one tile. For example, Vref0 and delay 0 may be applied for patch 0, Vref1 and delay 1 may be applied for patch 1, and so on. In some examples, a suitable process determines a reference voltage (Vref) and a delay offset value to apply for each CS signal transmitted to one tile. Act 522 may include one or more of acts 550 and 554 described with respect to fig. 5B.

Fig. 5B depicts a process that may be used to determine the reference voltage (Vref) and delay offset value to apply for each CS signal transferred to one tile. The process of FIG. 5B may be repeated for available tiles in the DIMM. At 550, the process calculates the eye width offset sum for each applied reference voltage value for one patch. The eye width may be the distance between the composite right edge and the composite left edge of the composite eye determined for the patch for the applied reference voltage. The eye width offset may be determined as:

eye width offset is eye width- (2 UIs), where 2 UIs are 128 PIs.

In some examples, 2 UIs are ideal or reference eye width values according to the JEDEC DDR5 specification. In some examples, the ideal eye width is a single memory clock cycle of the DDR-enabled memory. The eye width offset may be determined in the following manner.

If Vrefn is not the first Vref to be tested in the training step (e.g., the first Vref is the lowest Vref value), nor is Vrefn the last Vref to be tested in the training step (e.g., the last Vref may be the highest Vref value), then

Eye width offset sum (Vrefn) ═ eye width offset (Vrefn-1) + eye width offset (Vrefn +1), where:

eye width offset (Vrefn-1) is the eye width offset of the previous Vref measured before using Vrefn, and

the eye width offset (Vrefn +1) is the eye width offset of the next measured Vref after using Vrefn.

However, if Vrefn is the Vref first tested (e.g., the lowest Vref value), then

Eye width offset sum (Vrefn) ═ eye width offset (Vrefn) + eye width offset (Vrefn + 1).

If Vrefn is the Vref last tested (e.g., the highest Vref value), then

Eye width offset sum (Vrefn) ═ eye width offset (Vrefn-1) + eye width offset (Vrefn).

Averaging across 3 Vref values may take into account the fact that: at the edges of the Vref range, the measurements on both sides of the boundary are assumed to be the same. Instead of dividing all these values by 3, integer values are used and the lowest offset or Vref that produces the closest 50% duty cycle for the switched 0-1-0-1 mode is found.

At 552, the process selects Vref for use with the tile, with its eye width offset sum being the lowest value or its composite eye width closest to 2 UI values (or other specified measurement values). The Vref value may be programmed for use by the DRAM devices of the tile.

At 554, the process selects a delay offset for the CS signal based on the center of the composite eye associated with the selected Vref. The center of the composite eye may be set to the time delay of the CS signal for that tile, where the composite eye is associated with the selected Vref. For example, the midpoint times of the left and right edges of the composite edge of Vref may be selected to be used as the time delay of the CS signal for that tile. The host may store the time offset for delaying the CS signal to be transferred to a tile when the CS signal is to be transferred to a memory device of the tile. In some cases, the time offset is zero.

Fig. 6 depicts a system. The system may use embodiments described herein to determine a reference voltage to be applied to a memory device of a tile and a time delay of a Chip Select (CS) signal sent to the memory device of the tile. The system 600 includes a processor 610, the processor 610 providing processing, operational management, and instruction execution for the system 600. Processor 610 may include any type of microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), processing core, or other processing hardware, or combination of processors, for providing processing for system 600. The processor 610 controls the overall operation of the system 600 and may be or include one or more programmable general purpose or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), and the like, or a combination of such devices.

In one example, the system 600 includes an interface 612 coupled to the processor 610, which interface 612 may represent a higher speed interface or a high throughput interface for system components requiring higher bandwidth connections, such as the memory subsystem 620 or the graphics interface component 640 or the accelerator 642. Interface 612 represents an interface circuit that may be a stand-alone component or integrated into a processor die. The graphical interface 640 interfaces with graphical components, if present, for providing a visual display to a user of the system 600. In one example, the graphical interface 640 may drive a High Definition (HD) display that provides output to a user. High definition may refer to a display having a pixel density of about 100PPI (pixels per inch) or greater, and may include, for example, the following formats: full HD (e.g., 1080p), retinal display, 4K (ultra high definition or UHD), or other formats. In one example, the display may comprise a touch screen display. In one example, graphics interface 640 generates a display based on data stored in memory 630 or based on operations performed by processor 610, or both. In one example, graphics interface 640 generates a display based on data stored in memory 630 or based on operations performed by processor 610, or both.

The accelerators 642 may be fixed function offload engines that are accessible or used by the processor 610. For example, an accelerator in accelerators 642 may provide compression (DC) capabilities, cryptographic services, e.g., Public Key Encryption (PKE), cryptography, hashing/authentication capabilities, decryption, or other capabilities or services. In some embodiments, additionally or alternatively, ones of accelerators 642 provide field selection controller capability, as described herein. In some cases, accelerator 642 may be integrated into a CPU socket (e.g., a connector connected to a motherboard or circuit board that includes the CPU and provides an electrical interface with the CPU). For example, accelerators 642 may include single or multi-core processors, graphics processing units, logic execution units, single or multi-level caches, functional units that may be used to independently execute programs or threads, Application Specific Integrated Circuits (ASICs), Neural Network Processors (NNPs), programmable control logic, and programmable processing elements, such as Field Programmable Gate Arrays (FPGAs). The accelerators 642 may provide a plurality of neural networks, processor cores, or graphics processing units that may be used by Artificial Intelligence (AI) or Machine Learning (ML) models. For example, the AI model may use or include any or a combination of: a reinforcement learning scheme, a Q learning scheme, deep Q learning, or an Asynchronous evaluator algorithm (A3C), a combinational neural network, a recursive combinational neural network, or other AI or ML models. Multiple neural networks, processor cores, or graphics processing units may be used for the AI or ML models.

Memory subsystem 620 represents the main memory of system 600 and provides storage for code executed by processor 610, or data values used to execute routines. The memory subsystem 620 may include one or more memory devices 630, such as read-only memory (ROM), flash memory, volatile memory, or a combination of such devices. Memory 630 stores, hosts, and other things Operating System (OS)632 to provide a software platform for instructions in system 600. Additionally, applications 634 may execute on the software platform of OS 632 of memory 630. Application 634 represents a program having its own computational logic to perform the execution of one or more functions. Program 636 represents an agent or routine that provides ancillary functionality to OS 632 or one or more application programs 634 or a combination. The OS 632, applications 634 and programs 636 provide software logic to provide functionality for the system 600. In one example, memory subsystem 620 includes memory controller 622, memory controller 622 being the memory controller used to generate and issue commands to memory 630. It should be appreciated that the memory controller 622 may be a physical part of the processor 610 or a physical part of the interface 612. For example, memory controller 622 may be an integrated memory controller integrated onto a circuit with processor 610. In some examples, a system on a chip (SOC or SOC) is incorporated into one SOC package as one or more of the following: a processor, graphics, memory, a memory controller, and input/output (I/O) control logic.

Volatile memory is memory that is indeterminate in the event of a power interruption to the device (and therefore the data stored therein). Dynamic volatile memories require refreshing of data stored in the device to maintain state. One example of Dynamic volatile Memory includes DRAM (Dynamic Random Access Memory), or some variant, such as synchronous DRAM (sdram). The memory subsystem as described herein may be compatible with many memory technologies, for example, DDR3 (double data rate version 3, JEDEC (Joint Electronic Device Engineering Council, original version published on 27 th 6 th 2007). DDR4(DDR version 4, initial specification of JEDEC published in 9 months 2012), DDR4E (DDR version 4), LPDDR3 (low power DDR version 3, JESD209-3B, JEDEC published in 8 months 2013), LPDDR4(LPDDR version 4, JESD209-4, JEDEC originally published in 8 months 2014), WIO2 (wide input/output version 2, JESD229-2, JEDEC originally published in 8 months 2014), HBM (high bandwidth memory, JESD325, JEDEC originally published in 10 months 2013), LPDDR5(JEDEC currently discussed), HBM2(HBM version 2), JEDEC currently discussed, or other memory technologies or combinations of memory technologies, as well as derived or extended technologies based on such specifications. JEDEC standards are available from www.jedec.org.

For example, various embodiments may use the CS delay and Vref logic 623 to determine the CS signal delay and Vref to be applied by one or more memory devices of a tile in memory 630.

Although not specifically illustrated, it should be understood that system 600 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or other bus. A bus or other signal line may communicatively or electrically couple the components together, or both. A bus may include physical communication lines, point-to-point connections, bridges, switches, controllers, or other circuits or combinations. A bus may include, for example, one or more of the following: a system bus, a Peripheral Component Interconnect (PCI) bus, an ultra-transmission or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus.

In one example, system 600 includes an interface 614, interface 614 can be coupled to interface 612. In one example, interface 614 represents interface circuitry that may include separate components and integrated circuits. In one example, a plurality of user interface components or peripheral components or both are coupled to the interface 614. Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 650 may include an ethernet adapter, a wireless interconnect, a cellular network interconnect, USB (universal serial bus), or an interface based on other wired or wireless standards or proprietary interfaces. Network interface 650 may transmit data to a remote device, which may include transmitting data stored in memory. Network interface 650 may receive data from a remote device, which may include storing the received data in memory. Various embodiments may be used in conjunction with network interface 650, processor 610, and memory subsystem 620.

In one example, system 600 includes one or more input/output (I/O) interfaces 660. The I/O interface 660 can include one or more interface components via which a user interacts with the system 600 (e.g., audio, alphanumeric, tactile/touch, or other interface connections). Peripheral interface 670 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that are not independently connected to system 600. A non-independent connection is one in which: in this connection system 600 provides a software platform or a hardware platform or both on which to perform operations or use these platforms to interact with a user.

In one example, system 600 includes storage subsystem 680, storage subsystem 680 to store data in a non-volatile manner. In one example, at least some components of storage 680 may overlap components of memory subsystem 620 in some system implementations. The storage subsystem 680 includes storage device(s) 684, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid state, or optical disks, or a combination. The storage 684 holds code or instructions and data 686 in a persistent state (i.e., values are maintained even if power to the system 600 is interrupted). In general, the storage 684 may be considered a "memory," although the memory 630 is typically the execution or operation memory used to provide instructions to the processor 610. However, storage 684 is non-volatile, and memory 630 can comprise volatile memory (i.e., the value or state of data is indeterminate in the event power to system 600 is interrupted). In one example, storage subsystem 680 includes a controller 682 that interfaces with a storage 684. In one example, controller 682 is interface 614 or a physical part of processor 610, or may comprise circuitry or logic in both processor 610 and interface 614.

A non-volatile memory (NVM) device is a memory whose state is determined even if power to the device is interrupted. In one example, the NVM device can include a block addressable memory device, such as NAND technology, or more specifically, a multi-threshold level NAND flash memory (e.g., single layer cell ("SLC"), multi-layer cell ("MLC"), four layer cell ("QLC"), three layer cell ("TLC"), or some other NAND). The NVM devices may also include byte-addressable write-in-place three-dimensional intersection Memory devices, or other byte-addressable write-in-place NVM devices (also referred to as persistent memories), such as single or multi-level Phase Change Memory (PCM) or Phase Change Memory with Switch (PCMs), NVM devices using chalcogenide Phase Change materials (e.g., chalcogenide glass), resistive Memory including metal oxide substrates, oxygen vacancy substrates, and Conductive Bridge Random Access Memory (CB-RAM), nanowire Memory, ferroelectric Random Access Memory (FeRAM, FRAM), Magnetoresistive Random Access Memory (MRAM) incorporating memristor technology, Spin Transfer Torque (STT) -MRAM, spintronic magnetic junction Memory-based devices, Magnetic Tunneling Junction (MTJ) based devices, DW (magnetic domain wall) and SOT (spin-orbit transfer) based devices, thyristor based memory devices, or a combination of any of the above, or other memory.

A power source (not depicted) provides power to the components of system 600. More specifically, the power source is typically interfaced to one or more power supplies in the system 600 to provide power to the components of the system 600. In one embodiment, the power supply includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, e.g., an external AC to DC converter. In one example, the power source or power supply includes wireless charging hardware to charge by being in close proximity to a charging field. In one example, the power source may include an internal battery, an alternating current supply, a motion-based power supply, a solar power supply, or a fuel cell source.

In an example, system 600 may be implemented using an interconnected computing group of processors, memory, storage, network interfaces, and other components. A high speed interconnect, such as PCIe, ethernet, or optical interconnect (or a combination thereof) may be used.

Embodiments herein may be implemented in various types of computing, smart phones, tablets, personal computers, and networking equipment such as switches, routers, racks, and blade servers (e.g., blade servers employed in a data center and/or server farm environment). Servers for data centers and server farms include a ranked server configuration, e.g., a rack-based server or a blade server. These servers are communicatively interconnected via various Network provisions, such as dividing a server group into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private intranet. For example, a cloud hosting facility may typically employ a large data center having multiple servers. The blade includes a separate computing platform configured to perform server-type functions, i.e., "server-on-card". Thus, each blade includes components that are common in conventional servers, including a main printed circuit board (motherboard) that provides internal wiring (i.e., a bus) for coupling the appropriate Integrated Circuits (ICs) and other components mounted on the board.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, a hardware element may include a device, component, processor, microprocessor, circuit element (e.g., transistor, resistor, capacitor, inductor, etc.), integrated circuit, ASIC, PLD, DSP, FPGA, memory unit, logic gate, register, semiconductor device, chip, microchip, chipset, and so forth. In some examples, a software element may include a software component, a program, an application, a computer program, an application program, a system program, a machine program, operating system software, middleware, firmware, a software module, a routine, a subroutine, a function, a method, a procedure, a software interface, an API, an instruction set, computing code, computer code, a code segment, a computer code segment, a word, a value, a symbol, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation. It should be noted that hardware, firmware, and/or software elements may be referred to herein, collectively or individually, as "modules," logic, "" circuitry, "or" circuitry.

Some examples may be implemented using or as an article of manufacture or at least one computer readable medium. The computer readable medium may include a non-transitory storage medium to store logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform a method and/or operations in accordance with the described embodiments. The instructions may include any suitable type of code, for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine readable medium which represents various logic within a processor, which when read by a machine, computing device, or system causes the machine, computing device, or system to fabricate logic to perform the techniques described herein. Such representations (known as "IP cores") may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities for loading into the manufacturing machines that actually make the logic or processor.

The appearances of the phrase "one example" or "an example" are not necessarily all referring to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspects described herein, whether or not that aspect is described with respect to the same figure or element. Division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

Some examples may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The terms "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The term "indefinite article (a/an)" herein does not denote a limitation of quantity, but rather denotes the presence of at least one of the referenced item. The term "assert" as used herein with reference to signals means the state of a signal in which the signal is active and which can be realized by applying any logic level (logic 0 or logic 1) to the signal. The term "next" or "after" may refer to immediately following or following some other event(s). Other sequences of steps may also be performed according to alternative embodiments. In addition, additional steps may be added or removed depending on the particular application. Any combination of variations may be used, and many variations, modifications, and alternative embodiments will occur to those skilled in the art having the benefit of this disclosure.

Unless specifically stated otherwise, extracted terms (such as, for example, the phrase "X, Y or at least one of Z") are additionally understood, generally in the context of the usage, to be displayed as either of X, Y or Z, or any combination thereof (X, Y and/or Z). Thus, such disjunctive terms are generally not intended to, and should not, imply that at least one of X, at least one of Y, or at least one of Z are each present. In addition, extracted phrases such as the phrase "X, Y and at least one of Z" should also be understood to mean X, Y, Z, or any combination thereof, including "X, Y and/or Z," unless specifically stated otherwise.

Illustrative examples of the devices, systems, and methods disclosed herein are provided below. Embodiments of the apparatus, systems, and methods may include any one or more and any combination of the examples described below.

Example 1 includes a host system comprising: a processor, and a memory controller coupled to the processor, the memory controller to: requesting a first reference voltage applied by a memory device; during use of the first reference voltage by the memory device: transmitting a Chip Select (CS) signal to the memory device after various amounts of delay and receiving from the memory device sampled samples of the CS signal transmitted after the various amounts of delay; requesting a second reference voltage applied by the memory device; during use of the second reference voltage by the memory device: transmitting the CS signal to the memory device after various amounts of delay, and receiving from the memory device sampled samples of the CS signal transmitted after the various amounts of delay, wherein the processor is to determine a reference voltage for the memory device based on a reference voltage that provides a composite eye width closest to a reference eye width, and to determine a delay for transmitting the CS signal based on the composite eye width.

Example 2 includes any example, wherein the processor is to: a composite eye for an applied reference voltage is determined based on sampled CS signals from a plurality of memory devices that are delayed for a plurality of applied CS signal transmissions.

Example 3 includes any example, wherein: the processor is to determine a first composite eye based on rising and falling edges of sampled samples of the CS signal transmitted during use of the first reference voltage by the memory device and after the various amounts of delay; the processor is configured to select a latest rising edge and an earliest falling edge of the first composite eye; the processor is to determine a second composite eye based on rising and falling edges of sampled samples of the CS signal transmitted during use of the second reference voltage by the memory device and after the various amounts of delay; the processor is configured to select a latest rising edge and an earliest falling edge of the second composite eye; and the processor is configured to select the reference voltage associated with the compound eye from the first reference voltage and the second reference voltage, the compound eye being one of the first and second compound eyes that is closest to a reference eye width.

Example 4 includes any example, wherein: the processor is to select a transmission delay to be a time exactly in the middle of the composite eye width associated with the selected reference voltage.

Example 5 includes any example, wherein the reference eye width comprises a memory clock cycle.

Example 6 includes any of the examples and includes the memory device, and wherein the memory device includes a one-tile Dynamic Random Access Memory (DRAM) device.

Example 7 includes any example, wherein the processor is to initiate a CS signal training scheme compatible with joint committee for electronics engineering double data rate 5.

Example 8 includes any example, wherein, in a case that the sampled sample of the CS signal includes a rising edge that is greater than a threshold distance from an earliest rising edge, the processor is to set the sampled sample of the CS signal to provide a falling edge in place of the rising edge.

Example 9 includes any example, wherein the memory controller is to apply the determined offset prior to transmission of the CS signal, and the memory controller is to cause the memory device to apply the determined reference voltage.

Example 10 includes a method comprising: starting a Chip Select (CS) training mode for a memory device of a tile; setting a first reference voltage value for use by the memory device; transmitting a CS signal to the tile with various amounts of time delay during use of the first reference voltage; receiving sample samples of the CS signal with the various amounts of time delay from the memory device; determining a first composite eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples from use of the first reference voltage; setting a second reference voltage value for use by the memory device; transmitting a CS signal to the tile with various amounts of time delay during use of the second reference voltage; receiving, from the memory device, sampled samples of the CS signal associated with use of the second reference voltage and various amounts of time delay; determining a second composite eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples from the use of the second reference voltage; selecting a composite eye closest to the reference eye width; selecting a reference voltage associated with the selected compound eye; and determining a delay for transmission of the CS signal based on a midpoint of the composite eye.

Example 11 includes any example, wherein the reference eye width comprises a memory clock cycle.

Example 12 includes any example, wherein the tile comprises a tile of a Dynamic Random Access Memory (DRAM) device.

Example 13 includes any one of the examples, wherein the CS signal training pattern is compatible with joint committee for electronics engineering double data rate 5.

Example 14 includes any one of the examples, and includes: determining that the sampled sample of the CS signal includes a rising edge that is greater than a threshold distance from an earliest rising edge, and setting the sampled sample of the CS signal to provide a falling edge in place of the rising edge.

Example 15 includes any of the examples, and includes: applying, by a memory controller, the selected reference voltage, and applying, by the memory controller, the determined offset prior to transmission of the CS signal.

Example 16 includes any one of the examples, and includes: starting a Chip Select (CS) training mode for a memory device of a second tile; setting a first reference voltage value for use by memory devices of the second tile; transmitting a CS signal to the memory devices of the second tile with various amounts of time delay during use of the first reference voltage by the memory devices of the second tile; receiving, from the memory device, sampled samples of the CS signal with the various amounts of time delay from use of the first reference voltage by the memory devices of the second tile; determining a first compound eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples of usage of the first reference voltage by memory devices from the second tile; setting a second reference voltage value for use by memory devices of the second tile; transmitting a CS signal to the tile with various amounts of time delay during use of the second reference voltage by memory devices of the second tile; receiving, from the memory device, sampled samples of the CS signal with the various amounts of time delay from use of the second reference voltage by the memory devices of the second tile; determining a second compound eye based on a latest occurring rising edge and an earliest occurring falling edge of sampled samples of usage of the second reference voltage from memory devices of the second tile; selecting a second compound eye closest to the reference eye width; selecting a second reference voltage associated with the selected compound eye; and determining a delay for transmission of the CS signal based on a midpoint of the second composite eye.

Example 17 includes a system comprising: a host system comprising a processor, a memory controller, and a memory device, wherein the memory device is coupled to the processor, wherein: the processor to cause application of one or more reference voltages by the memory device and cause transmission of a Chip Select (CS) signal delayed by a plurality of delay times during use of one or more of the reference voltages; the processor is to receive sampled samples of the CS signal from a memory device; the processor is to determine a composite eye for at least one of the reference voltages based on the sampling samples; the processor is to select a reference voltage associated with a compound eye closest to a reference eye width; and the processor is configured to select a delay time before transmission of the CS signal based on a temporal offset from a midpoint of the composite eye closest to the reference eye width.

Example 18 includes any example, wherein the host system comprises a personal computer, a smartphone, a blade, a rack, or a server.

Example 19 includes any one of the examples, wherein the reference eye width comprises 2 UIs (unit intervals).

Example 20 includes any one of the examples, wherein the processor is to initiate a CS training mode based on joint committee for electronics engineering double data rate 5.