Clock control device and related product

文档序号：1920897 发布日期：2021-12-03 浏览：15次中文

阅读说明：本技术 时钟控制装置及相关产品 (Clock control device and related product ) 是由不公告发明人于 2020-05-27 设计创作，主要内容包括：本公开涉及一种时钟控制装置及相关产品。所述产品包括控制模块,所述控制模块包括：指令缓存单元、指令处理单元和存储队列单元；所述指令缓存单元,用于存储所述人工神经网络运算关联的计算指令；所述指令处理单元,用于对所述计算指令解析得到多个运算指令；所述存储队列单元,用于存储指令队列,该指令队列包括：按该队列的前后顺序待执行的多个运算指令或计算指令。通过以上装置,本公开可以提高相关产品在进行神经网络模型的运算时的运算效率。(The present disclosure relates to a clock control apparatus and related products. The product includes a control module, the control module including: the device comprises an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing the calculation instruction associated with the artificial neural network operation; the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions; the storage queue unit is configured to store an instruction queue, where the instruction queue includes: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue. Through the device, the operation efficiency of related products in operation of the neural network model can be improved.)

1. A clock control apparatus, for use with a processor, the apparatus comprising:

the voltage detection module is used for detecting the power supply voltage of a target position in the processor; when the power supply voltage is smaller than or equal to a preset first threshold value, outputting a voltage alarm signal;

a clock stretching module connected to the voltage detection module and used for generating a second clock signal according to the first clock signal corresponding to the reference frequency when receiving the voltage alarm signal, so that the processor performs data processing by using the second clock signal,

wherein a frequency of the second clock signal is lower than the reference frequency.

2. The apparatus of claim 1, wherein the voltage detection module comprises a first detection unit, the first detection unit comprising:

a pulse generating circuit for inputting a fifth clock signal and outputting a pulse signal;

a delay circuit connected to the pulse generating circuit, inputting the pulse signal, and outputting a delayed pulse signal, wherein a delay between the delayed pulse signal and the pulse signal is inversely related to a supply voltage of the target position;

the voltage detection and processing circuit is connected to the delay circuit and used for determining the power supply voltage of the target position according to the delayed pulse signal and the fifth clock signal; outputting a first voltage alarm signal when the supply voltage is less than or equal to a first threshold.

3. The apparatus of claim 2, wherein the voltage detection and processing circuit is further configured to:

outputting a first voltage normal signal when the supply voltage is greater than or equal to a preset second threshold and the duration of the supply voltage being greater than or equal to the second threshold reaches a preset first duration during the outputting of the first voltage alarm signal,

wherein the second threshold is greater than the first threshold.

4. The apparatus of claim 1, wherein the voltage detection module comprises a second detection unit, the second detection unit comprising:

the ring oscillation circuit is used for outputting a fourth clock signal according to the power supply voltage of the target position;

the processing circuit is connected to the ring oscillation circuit and used for determining a count value within a preset second time length according to the fourth clock signal; and outputting a second voltage alarm signal when the counting value is less than or equal to a preset first counting threshold value.

5. The apparatus of claim 2 or 3, wherein the voltage detection module further comprises a second detection unit, the second detection unit comprising:

the ring oscillation circuit is used for outputting a fourth clock signal according to the power supply voltage of the target position;

6. The apparatus of claim 5, wherein the processing circuit is further configured to:

outputting a second voltage normal signal when the count value is greater than or equal to a preset second count threshold and the number of times that the count value is greater than or equal to the second count threshold reaches a preset number of times during the period of outputting the second voltage alarm signal;

wherein the second count threshold is greater than the first count threshold.

7. The apparatus of claim 5 or 6, wherein the voltage detection module further comprises a first selection unit connected to the first detection unit, the second detection unit, and the clock stretching module, the first selection unit configured to:

and outputting the output signal of the first detection unit or the output signal of the second detection unit to the clock stretching module.

8. The apparatus of claim 6, wherein the voltage detection module further comprises a second selection unit coupled to the first detection unit, the second detection unit, and the clock stretching module, the second selection unit configured to:

when the first detection unit outputs a first voltage alarm signal and/or the second detection unit outputs a second voltage alarm signal, outputting the voltage alarm signal to the clock stretching module;

and when the first detection unit outputs a first voltage normal signal and the second detection unit outputs a second voltage normal signal, outputting the voltage normal signal to the clock stretching module.

9. The apparatus of any of claims 1-8, the clock stretching module comprising:

a clock phase generating circuit for outputting a plurality of phase clock signals according to the first clock signal;

and the clock stretching circuit is connected to the clock phase generating circuit and used for generating the second clock signal through the clock gating circuit according to the plurality of phase clock signals when the voltage alarm signal is received.

10. The apparatus of claim 9, wherein the clock stretching module is further configured to:

and when a normal voltage signal is received, generating a third clock signal according to the first clock signal or the plurality of phase clock signals so that the processor performs data processing by using the third clock signal, wherein the frequency of the third clock signal is equal to the reference frequency.

11. An artificial intelligence chip, wherein the chip comprises a clock control device according to any one of claims 1 to 10.

12. An electronic device, characterized in that the electronic device comprises an artificial intelligence chip according to claim 11.

13. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface device and a control device and an artificial intelligence chip according to claim 11;

wherein, the artificial intelligence chip is respectively connected with the storage device, the control device and the interface device;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the artificial intelligence chip and external equipment;

and the control device is used for monitoring the state of the artificial intelligence chip.

Technical Field

The present disclosure relates to integrated circuit technologies, and in particular, to a clock control device and a related product.

Background

When the chip is powered on and the load power consumption is suddenly increased, the chip cannot respond to the change of the load current in time due to the limitation of the bandwidth of a power supply network, and the chip power supply voltage is greatly reduced in a short time (generally less than 20 ns). The voltage drop causes an increase in the delay of the logic circuits in the chip. If the load current is too large, the voltage drops below the safe voltage of the chip, the timing sequence of the logic circuit cannot meet the requirement of the setup time, so that a metastable state is generated and the operation result of the circuit is wrong. This problem is called power droop. The processing mode in the related art has poor control effect on the load-following decline of the power supply.

Disclosure of Invention

In view of the above, it is desirable to provide a clock control apparatus and related products.

According to an aspect of the present disclosure, there is provided a clock control apparatus applied to a processor, the apparatus including:

wherein a frequency of the second clock signal is lower than the reference frequency.

According to another aspect of the present disclosure, an artificial intelligence chip is provided, which includes the clock control device described above.

According to another aspect of the present disclosure, an electronic device is provided, which includes the artificial intelligence chip described above.

According to another aspect of the present disclosure, a board card is provided, which includes: the artificial intelligence chip comprises a storage device, an interface device, a control device and the artificial intelligence chip;

wherein, the artificial intelligence chip is respectively connected with the storage device, the control device and the interface device; the storage device is used for storing data; the interface device is used for realizing data transmission between the artificial intelligence chip and external equipment; and the control device is used for monitoring the state of the artificial intelligence chip.

According to the clock control device disclosed by the disclosure, when the power supply voltage of the critical path is lower than the threshold value, the clock signal can be subjected to frequency reduction, the logic circuit establishment time margin is increased, and the load of the processor is reduced, so that errors in data processing results are avoided, and the control of voltage drop along with the load is realized.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a schematic diagram of a processor of a clocked device according to an embodiment of the disclosure.

Fig. 2 shows a block diagram of a clock control apparatus according to an embodiment of the present disclosure.

Fig. 3 shows a circuit schematic of a first detection unit according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a pulse signal of a clock control apparatus according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a supply voltage adjustment process of a clocked device according to an embodiment of the disclosure.

FIG. 6 shows a schematic diagram of a ring oscillator circuit of a clocking device according to an embodiment of the present disclosure.

Fig. 7 shows a block diagram of a clock control apparatus according to an embodiment of the present disclosure.

Fig. 8 shows a circuit schematic of a clock stretching module according to an embodiment of the present disclosure.

Fig. 9a and 9b show schematic diagrams of a second clock signal according to an embodiment of the present disclosure.

Fig. 10 shows a block diagram of a board card according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first," "second," and "third," etc. in the claims, description, and drawings of the present disclosure are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The clock control apparatus according to the embodiment of the present disclosure may be applied to a processor, which may be a general-purpose processor, such as a Central Processing Unit (CPU), or an artificial Intelligence Processor (IPU) for performing artificial intelligence operations. The artificial intelligence operations may include machine learning operations, brain-like operations, and the like. The machine learning operation comprises neural network operation, k-means operation, support vector machine operation and the like. The artificial intelligence processor may include, for example, one or a combination of a GPU (Graphics Processing Unit), a NPU (Neural-Network Processing Unit), a DSP (Digital Signal Processing Unit), a Field-Programmable Gate Array (FPGA), and an ASIC (Application Specific Integrated Circuit) chip. The present disclosure is not limited to a particular type of processor.

In one possible implementation, the processor referred to in this disclosure may include multiple processing units, each of which may independently run various tasks assigned thereto, such as: a convolution operation task, a pooling task, a full connection task, or the like. The present disclosure is not limited to processing units and tasks executed by processing units.

FIG. 1 shows a schematic diagram of a processor of a clocked device according to an embodiment of the disclosure. As shown in fig. 1, processor 100 includes a plurality of processing units 101 and a storage unit 102, where the plurality of processing units 101 is configured to execute instruction sequences, and the storage unit 102 is configured to store data, and may include a Random Access Memory (RAM) and a register file.

Fig. 2 shows a block diagram of a clock control apparatus according to an embodiment of the present disclosure. As shown in fig. 2, the apparatus 20 includes:

a voltage detection module 21, configured to detect a supply voltage of a target location in the processor; when the power supply voltage is smaller than or equal to a preset first threshold value, outputting a voltage alarm signal;

a clock stretching module 22, connected to the voltage detection module 21, for generating a second clock signal according to the first clock signal corresponding to the reference frequency when receiving the voltage alarm signal, so that the processor performs data processing by using the second clock signal,

wherein a frequency of the second clock signal is lower than the reference frequency.

For example, the position of the critical path in the processor may be set as a target position, and the supply voltage of the target position is detected by the voltage detection module 21. If the supply voltage is less than or equal to a preset first threshold, that is, the supply voltage is lower than a preset low voltage threshold, the voltage detection module 21 may generate and output an alarm signal.

In a possible implementation manner, when the clock stretching module 22 receives the alarm signal output by the voltage detection module 21, the clock stretching module may down-convert the first clock signal corresponding to the reference frequency, and generate and output a second clock signal after down-conversion, so that the processor performs data processing by using the second clock signal.

By the method, when the power supply voltage of the critical path is lower than the threshold value, the clock signal can be subjected to frequency reduction, the logic circuit establishment time allowance is increased, and the load of the processor is reduced, so that errors of data processing results are avoided, and the voltage drop along with the load is controlled.

In one possible implementation, the voltage detection module 21 may include a first detection unit for implementing Critical path detection (CPM).

Fig. 3 shows a circuit schematic of a first detection unit according to an embodiment of the present disclosure. As shown in fig. 3, the first detection unit includes:

a pulse generating circuit 31 that inputs the fifth clock signal and outputs a pulse signal;

a delay circuit 32 connected to the pulse generating circuit, for inputting the pulse signal and outputting a delayed pulse signal, wherein a delay between the delayed pulse signal and the pulse signal is inversely related to a supply voltage of the target position;

a voltage detection and processing circuit 33, connected to the delay circuit, for determining a supply voltage of the target location according to the delayed pulse signal and the fifth clock signal; outputting a first voltage alarm signal when the supply voltage is less than or equal to a first threshold.

For example, the Pulse generation circuit (Pulse generation circuit)31 may include a plurality of stages of inverters and a nand gate connected in series, and the fifth clock signal (clk) is directly input to one input terminal of the nand gate, and is input to the other input terminal of the nand gate after passing through the plurality of stages of inverters. The pulse generating circuit 31 generates a pulse signal for measurement in the first cycle of the input fifth clock signal. The pulse width of the pulse signal can be adjusted according to practical situations, which is not limited by the present disclosure. The frequency of the fifth clock signal may be the same as or different from the first clock signal, which is not limited by this disclosure.

In one possible implementation, a delay circuit (TRC) 32 is connected to the pulse generating circuit 31, and may for example include a series connection of multiple stages of inverters. The input pulse signal passes through the delay circuit 32, and generates a corresponding propagation delay, and the delayed pulse signal is output. The delay between the delayed pulse signal and the pulse signal is inversely related to the supply voltage of the target position, that is, the magnitude of the delay becomes larger as the supply voltage decreases.

Fig. 4 shows a schematic diagram of a pulse signal of a clock control apparatus according to an embodiment of the present disclosure. As shown in fig. 4, in the first cycle of the clock signal (clk)41, the Pulse generating circuit generates a Pulse signal (Detect Pulse)42, and the Pulse width of the Pulse signal 42 may be, for example, equal to the clock cycle of the clock signal 41. The pulse signal 42 passes through the delay circuit, and a Delayed pulse in TRC 43 is output. As shown in fig. 4, the delay of the pulse signal 43 becomes larger as the supply voltage decreases. A Reference delay (Detect Reference)44 (e.g., one clock cycle) may be preset, and if the delay of the pulse signal 43 is less than or equal to the Reference delay 44, the supply voltage may be considered to be within a reasonable range; conversely, if the delay of the pulse signal 43 is greater than the reference delay 44, the supply voltage may be considered abnormal (i.e., below the low voltage threshold) and a down-conversion may be required.

In one possible implementation, the voltage detection and processing circuit 33 may perform Time-to-digital (TDC) conversion on the delayed pulse signal and process the converted signal. As shown in fig. 3, the voltage detection and processing circuit 33 includes a plurality of stages of delay devices (e.g., an even number of inverters), a plurality of stages of registers, and a comparison circuit, and inputs the delayed pulse signal and the fifth clock signal to generate digital signals corresponding to the delay, for example, 64-Bit signals Bit [0], Bit [1], …, Bit [63], and Bit [64] in fig. 3. From the digital signal, a voltage value corresponding to the delay can be determined, the voltage value corresponding to the supply voltage of the target position. The corresponding relationship among the digital signal, the delay and the power supply voltage can be predetermined according to modes such as experimental measurement, and the specific determination mode is not limited in the present disclosure.

In a possible implementation manner, when the voltage is decreased, the propagation delay of the pulse signal passing through the adjustable delay circuit is increased, and the bits with high level in the output value of the time-to-digital conversion circuit are decreased, that is, it is determined that the voltage value corresponding to the delay is decreased. If the voltage value corresponds to the supply voltage being less than or equal to a preset first threshold (i.e., a low voltage threshold vth _ low), a first voltage ALARM signal (ALARM1) may be output to trigger the clock stretching circuit to down-clock. The digital signal output by the multi-stage register can be directly compared with a preset threshold signal (namely a low-voltage threshold) through a comparison circuit, and a comparison result is output; the determination of whether to issue the first voltage alarm signal is made according to the comparison result, and the present disclosure does not limit the specific implementation manner of the comparison circuit.

By the mode, the detection of the power supply voltage can be realized, and the alarm signal is output in the current period when the voltage drop along with the load is detected, so that the voltage drop along with the load is controlled, and the response speed of the device is improved. Compared with the related art, the circuit structure is simplified, and the circuit area is reduced.

In one possible implementation, the voltage detection and processing circuit 33 is further configured to:

during the period of outputting the first voltage alarm signal, when the power supply voltage is greater than or equal to a preset second threshold value and the duration of the power supply voltage being greater than or equal to the second threshold value reaches a preset first duration, outputting a first voltage normal signal, wherein the second threshold value is greater than the first threshold value

For example, after the clock stretching circuit performs frequency reduction, the data processing performance of the processor is reduced, so that when the power supply voltage rises back to the set high voltage threshold and lasts for a certain time, the frequency of the output clock can be restored, and the frequency of the output clock is the reference frequency.

During the period that the voltage detection and processing circuit 33 outputs the first voltage alarm signal, the voltage value corresponding to the delay may be continuously obtained, and if the voltage value corresponds to the power supply voltage that is greater than or equal to the preset second threshold value, and the duration of the power supply voltage that is greater than or equal to the second threshold value reaches the preset first duration, the first voltage normal signal may be output, so that the clock stretching circuit recovers the frequency of the output clock, and the frequency of the output clock is the reference frequency. The second threshold is a set high-pressure threshold (vth _ high) which is larger than the first threshold (low-pressure threshold vth _ low); the first duration may be, for example, a plurality of preset clock cycles, and the specific values of the second threshold and the first duration are not limited in this disclosure.

In a possible implementation manner, the digital signal output by the multi-stage register may be directly compared with a preset threshold signal (i.e., a high voltage threshold) by the comparison circuit, and a comparison result is output; and determining whether to send out a first voltage normal signal according to the comparison result and the times of the comparison result meeting the condition.

Fig. 5 shows a schematic diagram of a supply voltage adjustment process of a clocked device according to an embodiment of the disclosure. As shown in fig. 5, the high voltage threshold (vth _ high) > the low voltage threshold (vth _ low) > the safe voltage (safe _ voltage). In the case of non-clocked operation, as shown by curve a1 in fig. 5, the supply voltage VDD decreases with increasing load, from the high voltage threshold (position 0 in fig. 5) to the low voltage threshold (position 1 in fig. 5), until it falls below the safe voltage, which may lead to errors in the data processing result.

In the case of the clock control, as shown by a curve a2 in fig. 5, when the supply voltage VDD reaches the low voltage threshold (time point 1 in fig. 5) from the high voltage threshold (time point 0 in fig. 5), the voltage detection and processing circuit outputs a voltage alarm signal, the clock stretching module performs frequency reduction after receiving the voltage alarm signal, and outputs a stretched clock signal (stretched _ clock), so that the supply voltage VDD is raised back before reaching the safe voltage, thereby avoiding the error of the data processing result.

In one possible implementation, after the supply voltage VDD rises back to exceed the high voltage threshold (time point 2 in fig. 5) and lasts for N clock cycles (i.e., a first duration), and reaches time point 3 in fig. 5, the voltage detection and processing circuit outputs a voltage normal signal to make the clock stretching circuit recover the frequency of the output clock, which is the reference frequency.

According to the voltage detection and processing circuit disclosed by the embodiment of the disclosure, a bistable line control mode is adopted, namely, at a time point 1, the power supply voltage is lower than a low threshold value to trigger an alarm, the power supply voltage rises back to be higher than the low threshold value and lower than a high threshold value, and the alarm is not cancelled; the alarm is deactivated only after the supply voltage has risen above the high threshold at time point 2 and has remained for N clock cycles to time point 3. The method can filter the influence of the tiny fluctuation on the power supply voltage on the alarm signal, and avoid the oscillation of the alarm signal, which causes the oscillation of the clock stretching circuit between the frequency reduction and the frequency raising, thereby causing larger power supply voltage fluctuation.

In a possible implementation manner, the voltage detection module 21 may include a second detection unit, and the second detection unit includes:

the ring oscillation circuit is used for outputting a fourth clock signal according to the power supply voltage of the target position;

For example, the voltage detection module 21 may employ a Ring oscillator (Ring oscillator) for voltage detection. FIG. 6 shows a schematic diagram of a ring oscillator circuit of a clocking device according to an embodiment of the present disclosure. As shown in fig. 6, the ring oscillator may be an odd number of inverters connected end to end, and as long as the processor is powered on, the ring oscillator will automatically oscillate to generate the fourth clock signal, and the oscillation frequency of the fourth clock signal is related to voltage, temperature, and process, so that the ring oscillator can be used as a detector for the operating state of the processor. If the chip technology of the processor determines that the working temperature is not changed greatly, the oscillation frequency of the ring oscillation circuit is increased along with the increase of the voltage and is decreased along with the decrease of the voltage.

In one possible implementation, the ring oscillator circuit may output a fourth clock signal according to a supply voltage of a target location (i.e., a critical path of the processor); the processing circuit may be coupled to the ring oscillator circuit and configured to determine a count value for a preset second duration based on the fourth clock signal. Wherein the processing circuit may comprise a counter (not shown), and the fourth clock signal is used as an input of the counter, and the count value of the counter may reflect the level of the power supply voltage during a preset second time period (e.g. 1000 ns).

In a possible implementation manner, the processing circuit may compare the count value with a preset first count threshold, and if the count value is smaller than or equal to the preset first count threshold, it may determine that the power supply voltage is abnormal (i.e., lower than the low voltage threshold), and the processing circuit may output a second voltage alarm signal to trigger the clock stretching circuit to reduce the frequency. The first counting threshold may be a preset counting value corresponding to the low-voltage threshold, and the specific value of the first counting threshold is not limited in the present disclosure.

In this way, the detection of the supply voltage can be achieved in order to achieve a control of the voltage drop with load.

In one possible implementation, the processing circuit is further configured to:

wherein the second count threshold is greater than the first count threshold.

For example, after the clock stretching circuit performs frequency reduction, the data processing performance of the processor is reduced, and therefore, when the power supply voltage rises back to the set high-voltage threshold, the frequency of the output clock can be restored to the reference frequency.

And continuously acquiring counting values of a plurality of second time lengths during the period that the processing circuit outputs the second voltage alarm signal, and outputting a second voltage normal signal if the counting value is greater than or equal to a preset second counting threshold value and the times that the counting value is greater than or equal to the second counting threshold value reach the preset times, so that the frequency of the clock stretching circuit recovering the output clock is taken as the reference frequency. The second counting threshold value is a preset counting value corresponding to the high-voltage threshold value and is larger than the first counting threshold value; the preset number of times may be, for example, 5 to 10 times, and the specific values of the second count threshold and the preset number of times are not limited by the present disclosure.

By adopting the bistable line control mode, the influence of small fluctuation on the power supply voltage on the alarm signal can be filtered, and the alarm signal is prevented from oscillating, so that the clock stretching circuit oscillates between frequency reduction and frequency increase, and larger power supply voltage fluctuation is caused.

Fig. 7 shows a block diagram of a clock control apparatus according to an embodiment of the present disclosure. As shown in fig. 7, the voltage detection module 21 of the apparatus 20 includes a first detection unit 211, a second detection unit 212, and a first selection unit 213, and the first selection unit 213 is connected to the first detection unit 211, the second detection unit 212, and the clock stretching module 22, respectively. Wherein the first selecting unit 213 is configured to:

and outputting the output signal of the first detection unit or the output signal of the second detection unit to the clock stretching module.

For example, the first selection unit 213 may include a selector for gating the output signal of the first detection unit 211 or the output signal of the second detection unit 212 according to an enable signal, so as to control the clock stretching module through the first detection unit or the second detection unit. The first detecting unit 211 and the second detecting unit 212 may work independently without affecting each other.

When the voltage drop along with the load is required to be quickly responded, the clock stretching module can be controlled through the first detection unit; otherwise, the clock stretching module can be controlled by the second detection unit. The detection unit selected by the person skilled in the art can be set according to the actual situation, and the disclosure does not limit this. In this way, flexibility of clock stretching control can be improved.

In one possible implementation, the voltage detection module may include a first detection unit, a second detection unit, and a second selection unit (not shown). The second selection unit is respectively connected to the first detection unit, the second detection unit and the clock stretching module, and is used for:

For example, the second selection unit may include an OR gate (OR), for example, having the first voltage alarm signal of the first detection unit and the second voltage alarm signal of the second detection unit as logic 1, and having the first voltage normal signal of the first detection unit and the second voltage normal signal of the second detection unit as logic 0.

When the first detection unit outputs a first voltage alarm signal (logic 1) and/or the second detection unit outputs a second voltage alarm signal (logic 1), the second selection unit outputs a voltage alarm signal (logic 1) to the clock stretching module so that the clock stretching module performs frequency reduction; when the first detection unit outputs a first voltage normal signal (logic 0) and the second detection unit outputs a second voltage normal signal (logic 0), the second selection unit outputs the voltage normal signal (logic 0) to the clock stretching module, so that the clock stretching module recovers the frequency of the output clock as the reference frequency.

That is, as long as one of the first voltage alarm signal and the second voltage alarm signal is pulled up, the clock stretching circuit is subjected to frequency reduction; both alarm signals are deactivated and the clock stretching circuit recovers the original frequency.

By the mode, the fast response of the first detection unit (CPM) to voltage drop with load and the insensitivity of the second detection unit (ring oscillation circuit) to voltage noise can be combined, so that the system can fast respond to a voltage drop event, frequency can not be recovered before the voltage drop event is finished due to voltage noise after frequency reduction, and the reliability of clock broadening control is further improved.

In one possible implementation, as shown in fig. 7, the clock stretching module 22 includes:

a clock phase generating circuit 221 for outputting a plurality of phase clock signals according to the first clock signal;

a clock stretching circuit 222, connected to the clock phase generating circuit, for generating the second clock signal through an Integrated Clock Gating (ICG) circuit according to the plurality of phase clock signals when receiving the voltage alarm signal.

For example, the clock Phase generation circuit 221 may be, for example, a DLL (Delay locked Loop) circuit, which inputs a first clock signal from a PLL (Phase locked Loop) and outputs a plurality of Phase clock signals, for example, 8 Phase clock signals having phases of 0, 45, 90, 135, 180, 225, 270, and 315 (a Phase difference between adjacent Phase clocks is 45 degrees).

Fig. 8 shows a circuit schematic of a clock stretching module according to an embodiment of the present disclosure. As shown in fig. 8, the clock phase generation circuit 221 can generate 8-phase clocks, which are input to 8 ICG circuits (ICG0, ICG1, …, ICG7), respectively.

The clock stretching circuit 222, upon receiving the voltage ALARM signal (ALARM) from the voltage detection module 21, the counter cnt may start counting, generate a digital code of an enable signal ICG _ en [7:0] and input to each of the ICG circuits (ICG0, ICG1, …, ICG7), respectively, so that each of the ICG circuits is enabled for a period of time, outputting one of a plurality of phase clock signals; after passing through an OR gate (OR), a second clock signal clk _ out is generated. The gated clock circuit may adopt any circuit structure in the related art, and the present disclosure does not limit this.

In one possible implementation, the different phase clocks may be combined at the output to obtain the down clocks of different ratios. In the case where the phase clock signals are 8, two kinds of down clocks (i.e., the second clock signal) of 8/9 or 4/5 of the reference frequency may be output, for example. The person skilled in the art can set the down ratio of the down clock according to practical situations, and the present disclosure does not limit this.

Fig. 9a and 9b show schematic diagrams of a second clock signal according to an embodiment of the present disclosure. FIG. 9a is a schematic diagram of generating a second clock signal having a reference frequency of 8/9; fig. 9b is a schematic diagram of generating a second clock signal having a reference frequency of 4/5.

As shown in fig. 9a and 9b, the various ICGs may be controlled to be active for different time periods (e.g., the bolded portions of the various phase clock signals) based on the encoding of enable signals ICG _ en [7:0] of the 8 ICG circuits (ICG0, ICG1, …, ICG7) to output one of the 8 phase clock signals (clk0, clk45, clk90, clk135, clk180, clk225, clk270, clk315) for the time periods. After passing through an OR gate (OR), the second clock signal clk _ out is output, thereby completing the clock down-conversion process. Wherein, for the 8/9 reference frequency of fig. 9a, 9 clock cycles of the first clock signal are required to generate a second clock signal of 8 cycles; for the 4/5 reference frequency of fig. 9b, 5 clock cycles of the first clock signal are required, generating a4 cycle second clock signal.

By the method, clock broadening can be realized, the clock frequency is reduced, so that the load of the processor is reduced, and the voltage drop along with the load is controlled; and the gated clock is adopted to form a synchronous circuit to realize clock broadening, so that the stability of the broadened clock signal can be improved, and burrs cannot be generated.

In one possible implementation, the clock stretching module 22 is further configured to: and when a normal voltage signal is received, generating a third clock signal according to the first clock signal or the plurality of phase clock signals so that the processor performs data processing by using the third clock signal, wherein the frequency of the third clock signal is equal to the reference frequency.

For example, if the clock stretching module 22 receives the voltage normality signal from the voltage detection module 21, the clock down-conversion may be stopped, and a third clock signal having a frequency equal to the reference frequency may be generated and output. The phase of the third clock signal may be the same as or different from the first clock signal, which is not limited by this disclosure.

In one possible implementation, the clock stretching circuit 222 may directly output the first clock signal as the third clock signal when receiving the voltage normality signal; the phase of the first clock signal can be adjusted and output as a third clock signal; any one of the plurality of phase clock signals may also be gated for output as a third clock signal. The present disclosure does not limit the specific generation manner of the third clock signal.

According to the clock control device disclosed by the embodiment of the disclosure, when the power supply voltage of the critical path is lower than the threshold value, the clock signal of the processor is subjected to frequency reduction, the time margin for establishing the logic circuit is increased, and the load of the processor is reduced, so that errors in the data processing result are avoided, and the control of voltage drop along with the load is realized.

According to the embodiment of the disclosure, when the CPM is detected by adopting the critical path to detect the load-dependent drop, the precision can be very high, and the minimum resolution is only limited by the minimum time delay of the production process used by the circuit. Therefore, voltage drop along with load can be finely detected; meanwhile, the CPM is used as an open-loop system, the detection value of the CPM is updated in each sampling period, the alarm signal can be output for dynamic frequency modulation when the current sampling period that the voltage is reduced along with the load is detected, and the response speed of the device is improved.

It should be understood that the above-described apparatus embodiments are merely illustrative and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In addition, unless otherwise specified, each functional unit/module in each embodiment of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. The artificial intelligence processor may be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, ASIC, etc., unless otherwise specified. Unless otherwise specified, the Memory unit may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

In a possible implementation manner, an artificial intelligence chip is further disclosed, which comprises the clock control device.

In a possible implementation manner, a board card is further disclosed, which comprises a storage device, an interface device, a control device and the artificial intelligence chip; wherein, the artificial intelligence chip is respectively connected with the storage device, the control device and the interface device; the storage device is used for storing data; the interface device is used for realizing data transmission between the artificial intelligence chip and external equipment; and the control device is used for monitoring the state of the artificial intelligence chip.

Fig. 10 shows a block diagram of a board according to an embodiment of the present disclosure, and referring to fig. 10, the board may include other kit components besides the chip 389, where the kit components include, but are not limited to: memory device 390, interface device 391 and control device 392;

the storage device 390 is connected to the artificial intelligence chip through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the artificial intelligence chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the artificial intelligence chip may include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600 MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with the artificial intelligence chip. The interface device is used for realizing data transmission between the artificial intelligence chip and external equipment (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device may also be another interface, and the disclosure does not limit the specific expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the artificial intelligence chip is still transmitted back to the external device (e.g. server) by the interface device.

The control device is electrically connected with the artificial intelligence chip. The control device is used for monitoring the state of the artificial intelligence chip. Specifically, the artificial intelligence chip and the control device can be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). As the artificial intelligence chip can comprise a plurality of processing chips, a plurality of processing cores or a plurality of processing circuits, a plurality of loads can be driven. Therefore, the artificial intelligence chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the artificial intelligence chip.

In one possible implementation, an electronic device is disclosed that includes the artificial intelligence chip described above. The electronic device comprises a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, an intelligent terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1. a clock control apparatus applied to a processor, the apparatus comprising:

wherein a frequency of the second clock signal is lower than the reference frequency.

The apparatus of clause a1, the voltage detection module including a first detection unit, the first detection unit including:

a pulse generating circuit for inputting a fifth clock signal and outputting a pulse signal;

Clause a3. the device of clause a2, the voltage detection and processing circuit further for:

wherein the second threshold is greater than the first threshold.

Clause a4. the apparatus according to clause a1, the voltage detection module comprising a second detection unit comprising:

the ring oscillation circuit is used for outputting a fourth clock signal according to the power supply voltage of the target position;

Clause a5. the apparatus according to clause a2 or A3, the voltage detection module further comprising a second detection unit comprising:

the ring oscillation circuit is used for outputting a fourth clock signal according to the power supply voltage of the target position;

Clause a6. the apparatus of clause a5, the processing circuit further configured to:

wherein the second count threshold is greater than the first count threshold.

Clause A7. the device of clause a5 or a6, the voltage detection module further comprising a first selection unit connected to the first detection unit, the second detection unit, and the clock stretching module, the first selection unit to:

and outputting the output signal of the first detection unit or the output signal of the second detection unit to the clock stretching module.

Clause A8. the apparatus of clause a6, the voltage detection module further comprising a second selection unit connected to the first detection unit, the second detection unit, and the clock stretching module, the second selection unit to:

Clause A9. the apparatus of any one of clauses a1-a8, the clock stretching module comprising:

a clock phase generating circuit for outputting a plurality of phase clock signals according to the first clock signal;

Clause a10. the apparatus of clause a9, the clock stretching module further to:

Clause a11, an artificial intelligence chip comprising a clock control device according to any one of clauses a1-a 10.

Clause a12, an electronic device comprising the artificial intelligence chip of clause a 11.

Clause a13, a card, comprising: a memory device, an interface device and a control device and an artificial intelligence chip as described in clause a 11;

wherein, the artificial intelligence chip is respectively connected with the storage device, the control device and the interface device;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the artificial intelligence chip and external equipment;

and the control device is used for monitoring the state of the artificial intelligence chip.

The embodiments of the present disclosure have been described in detail, and the principles and embodiments of the present disclosure are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present disclosure. Meanwhile, a person skilled in the art should, based on the idea of the present disclosure, change or modify the specific embodiments and application scope of the present disclosure. In view of the above, the description is not intended to limit the present disclosure.

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