阅读说明：本技术 数据组合方法、芯片及装置 (Data combination method, chip and device ) 是由 龚源泉 徐子轩 夏杰 于 2021-09-18 设计创作，主要内容包括：本申请提供了一种数据组合方法、芯片及装置,应用于具有N个数据传输接口的芯片,所述方法包括步骤：分组步骤：将所述N个数据传输接口分为M组；数据组合步骤：将所述M组数据传输接口中的数据于组内分别进行组合,将各组的有效数据分别放置于对应组的前侧,并记录各组的有效数据个数；以及分组合并步骤：将所述M组数据传输接口中的至少部分组数据传输接口基于所述至少部分组的有效数据个数合并为P组并进行数据组合,其中,M、N均为整数,N≥4,M≥2,M＞P＞0,基于该方法能够降低数据组合的逻辑复杂程度,芯片实现芯片的时序和面积的优化。(The application provides a data combination method, a chip and a device, which are applied to a chip with N data transmission interfaces, wherein the method comprises the following steps: grouping: dividing the N data transmission interfaces into M groups; a data combination step: respectively combining the data in the M groups of data transmission interfaces in groups, respectively placing the effective data of each group on the front side of the corresponding group, and recording the number of the effective data of each group; and a grouping and merging step: and merging at least part of the M groups of data transmission interfaces into P groups based on the number of the effective data of the at least part of groups and carrying out data combination, wherein M, N are integers, N is not less than 4, M is not less than 2, and M is more than P and is more than 0.)

1. A data combination method is applied to a chip with N data transmission interfaces, and is characterized by comprising the following steps:

grouping: dividing the N data transmission interfaces into M groups;

a data combination step: respectively combining the data in the M groups of data transmission interfaces in groups, respectively placing the effective data of each group on the front side of the corresponding group, and recording the number of the effective data of each group; and

grouping and merging step: and merging at least part of the group data transmission interfaces in the M group data transmission interfaces into P groups based on the number of the effective data of the at least part of the groups, and performing data combination, wherein M, N are integers, N is more than or equal to 4, M is more than or equal to 2, and M is more than P and more than 0.

2. The data combining method according to claim 1, wherein in the grouping step, the number of data transmission interfaces in at least the first M-1 group of the M group data transmission interfaces is the same.

3. The data combining method of claim 1 or 2, wherein P-1.

4. The data combining method according to claim 1 or 2, wherein P > 1, in the packet merging step, further comprising:

respectively placing the effective data in the P group data transmission interfaces at the front sides of the corresponding groups, and recording the number of the effective data of each group; and

and combining the P groups of data transmission interfaces into one group based on the number of the effective data of each group and performing data combination.

5. The data combination method according to claim 1 or 2, wherein M is 2, P is 1, the M groups of data transmission interfaces include a first group of data transmission interfaces and a second group of data transmission interfaces, and in the packet combination step, "combining at least part of the M groups of data transmission interfaces into P groups based on the number of valid data of the at least part of the groups and performing data combination" is implemented to arrange valid data in the second group of data transmission interfaces after the last valid data in the first group of data transmission interfaces.

6. The data combining method according to claim 1 or 2, wherein in the data combining step, the valid data in each group are combined in an enumerated manner.

7. A chip having N data transmission interfaces, characterized in that the data combination method of any one of claims 1 to 6 is applied.

8. An apparatus applying the data combination method of any one of claims 1 to 6 or the chip of claim 7.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a data combination method, a chip, and an apparatus.

Background

With the continuous expansion of chip scale, especially chips applied in the fields of artificial intelligence, network switching, etc., a large amount of data needs to be processed. In these chips, a problem of processing and storing data from a plurality of interfaces after the data are combined is often encountered. Assuming that m interfaces input data with the same width, each interface has an indication signal to indicate whether the current data of the interface is valid. Data of one interface can only participate in the combination when it is valid. A schematic diagram of a combination using an 8 interface as an example is shown in fig. 1. Therefore, at least 0 data is valid for the m interfaces, and at most m data is valid for the m interfaces. There are 2m total cases. When m is 8, there are 256 cases; when m is 24, the number of cases is as much as 16,777,216. As the number of interfaces increases, the number of instances in which data is valid grows exponentially. How to combine the valid data of the interfaces together according to such various situations is a problem that must be solved in chip design. Meanwhile, the complexity of the design method for combining these data directly affects the timing and area of the chip.

Therefore, there is a need for an improved data combining method and apparatus.

Disclosure of Invention

In view of the above technical problems in the prior art, the present application provides a data combining method applied to a chip having N data transmission interfaces, the method including the steps of:

grouping: dividing the N data transmission interfaces into M groups;

a data combination step: respectively combining the data in the M groups of data transmission interfaces in groups, respectively placing the effective data of each group on the front side of the corresponding group, and recording the number of the effective data of each group; and

grouping and merging step: and merging at least part of the group data transmission interfaces in the M group data transmission interfaces into P groups based on the number of the effective data of the at least part of the groups, and performing data combination, wherein M, N are integers, N is more than or equal to 4, M is more than or equal to 2, and M is more than P and more than 0.

Optionally, in the grouping step, the number of data transmission interfaces in at least the first M-1 group of the M group of data transmission interfaces is the same.

Optionally, P ═ 1.

Optionally, P > 1, and in the packet merging step, the method further includes:

respectively placing the effective data in the P groups of data transmission interfaces at the front side of the corresponding groups, recording the number of the effective data of each group,

and combining the P groups of data transmission interfaces into one group based on the number of the effective data of each group and performing data combination.

Optionally, M is 2, P is 1, the M group data transmission interfaces include a first group data transmission interface and a second group data transmission interface, and in the packet merging step, "merging at least some of the M group data transmission interfaces into P groups based on the number of valid data of the at least some groups and performing data combination" is implemented to arrange valid data in the second group data transmission interface after the last valid data in the first group data transmission interface.

Optionally, in the data combining step, the valid data in each group are combined in an enumerated manner.

In order to achieve the above object, the present application further provides a chip having N data transmission interfaces, and applying the data combination method described above.

In order to achieve the above object, the present application further provides a device, which applies the above data combination method or chip.

To sum up, this application is through the mode with a plurality of interfaces grouping for the data in every group is less, and then make the mode that adopts the enumeration can realize its quick convenient data combination, furthermore, this application is through hierarchical mode, set up multistage interface group based on quantity of interface and the complexity adaptability of data combination, arrange in the front side through the effective data with a plurality of interface groups (or multiunit interface), the mode of recording effective data quantity and progressively merging interface group finally reachs the data combination result, not only can reduce the logical complexity of data combination, the chip realizes the optimization of the chronogenesis and the area of chip.

Drawings

FIG. 1 is a diagram illustrating data combination in the prior art;

fig. 2 is a data combination diagram of a data combination method according to an embodiment of the present application.

Detailed Description

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the present application is not limited to the following embodiments, but includes various changes, substitutions, and alterations within the technical scope of the present disclosure. The terms "first," "second," and the like may be used to explain various elements, the number of elements is not limited by such terms. These terms are only used to distinguish one element from another. Thus, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment. The singular forms "a", "an" and "the" do not exclude the plural forms unless the context requires otherwise. The following description of the embodiments of the present application is provided for illustrative purposes, and other advantages and capabilities of the present application will become apparent to those skilled in the art from the present disclosure.

In the following description, reference is made to the accompanying drawings that describe several embodiments of the application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.

Although the terms first, second, etc. may be used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first preset threshold may be referred to as a second preset threshold, and similarly, the second preset threshold may be referred to as a first preset threshold, without departing from the scope of the various described embodiments. The first preset threshold and the preset threshold are both described as one threshold, but they are not the same preset threshold unless the context clearly indicates otherwise. Similar situations also include a first volume and a second volume.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

As shown in fig. 1, taking the data combination of 8 input interfaces as an example: at least 0 data of the m interfaces are effective, at most m data are effective, and the total number of the m interfaces is 2^mA situation. When m is 8, there are 256 cases; when m is 24, the number of cases is as much as 16,777,216. As the number of interfaces increases, the number of instances in which data is valid grows exponentially. How to combine the valid data of the interfaces together according to such various situations is a problem that must be solved in chip design. Meanwhile, the design method for combining these data directly affects the timing and area of the chip.

One of the existing implementations is to use enumeration to enumerate all cases, and determine valid data after combination for each case.

Take the number of interfaces as 8 as an example. Suppose that the valid signals of 8 interfaces form a vector: valid [7:0 ].

The input data of 8 interfaces are recorded as data0, data1, … … and data7, and the combined data are recorded as dataOut. The value enumeration and data combination method according to valid is as follows (wherein xxx represents invalid data):

valid＝＝8’b0000_0001：dataOut＝{data0,xxx}；

valid＝＝8’b0000_0010：dataOut＝{data1,xxx}；

valid＝＝8’b0000_0011：dataOut＝{data0,data1,xxx}；

……

and so on.

As described above, a total of 256 possible values of valid need to be enumerated. If the number of interfaces is 24, it is not possible to manually enumerate 16,777,216 values of valid. Even with the script tool, because the number is too large, it takes a long time to complete the enumeration of valid values, and the generated file is huge. The synthesis tool also takes a significant amount of time to convert the hardware description language to a gate level netlist.

In order to solve the above technical problem, this embodiment provides a data combination method, which is applied to a chip having N data transmission interfaces, and the method includes the steps of:

grouping: dividing N data transmission interfaces into M groups;

a data combination step: respectively combining data in M groups of data transmission interfaces, respectively placing effective data of each group at the front side of a corresponding group, and recording the number of the effective data of each group; and

grouping and merging step: at least part of group data transmission interfaces in the M group data transmission interfaces are combined into P groups based on the number of effective data of at least part of groups and are subjected to data combination, wherein M, N are integers, N is not less than 4, M is not less than 2, and M is more than P and is more than 0.

It should be noted that, the "data transmission interface" mentioned in this embodiment may be an interface between the chip and external data transmission or an internal transmission interface of the chip, and this embodiment is not limited thereto.

For convenience of explanation, the principle and steps of the method provided in the present embodiment are specifically described below by taking N-16, M-4, and P-2 as examples.

As shown in fig. 2, the method provided by this embodiment includes the steps of:

grouping: data transmission interfaces (hereinafter simply referred to as interfaces) are grouped in sequence, each group containing the same number of interfaces (if the number of interfaces cannot be divisionally divided by the number of groups, it is guaranteed that the other groups except the last group contain the same number of interfaces). The following description will be given by taking an example of dividing into 4 groups of 4 interfaces. The interfaces 0 to 3 are divided into a first group, the interfaces 4 to 7 are divided into a second group, the interfaces 8 to 11 are a third group, the interfaces 12 to 15 are a fourth group, and so on.

A data combination step: and simultaneously combining the inner parts of each group, and putting the effective data at the forefront to finish the first-stage operation. And simultaneously recording the number of the effective data of each group. The number of valid data in each group is respectively marked as validNum0S0, validNum1S0, validNum2S0 and validNum3S 0. It can be seen that the number of valid data in each group may take on a value of 0 to 4. Since each group has only 4 data, valid flags have only 16 possible values, and valid data can be easily combined by way of enumeration.

Grouping and merging step: in this embodiment, four sets of interfaces after the first stage operation may be combined into two sets, that is, each set has 8 data. Wherein, the 4 data after the first group of combination and the 4 data after the second group of combination together form a new first group of interface by 8 data; the 4 data after the third group of combinations plus the 4 data after the fourth group of combinations, for a total of 8 data, form a new second group of interfaces. Each group was divided into two halves, each half having 4 data. The 4 data after the first set of combinations make up the first half of the new first set of interfaces and the 4 data after the second set of combinations make up the second half of the new first set of interfaces. Similarly, the 4 data after the third group of combinations form the first half of the new second group of interfaces, and the 4 data after the fourth group of combinations form the second half of the new second group of interfaces.

And executing second-stage operation, and simultaneously combining the inner parts of each group according to the effective number of the first half of data. Namely, the first half 4 data of the new first group interface are combined with the second half 4 data according to the value of validNum0S 0; the first half 4 data of the new second set of interfaces are combined with the second half 4 data according to the value of validNum2S 0. And simultaneously recording the number of the effective data of each group. The number of valid data in each group is respectively marked as validNum0S1 and validNum1S 1. Obviously:

validNum0S1＝validNum0S0+validNum1S0；

validNum1S1＝validNum2S0+validNum3S0。

since the first-stage operation is performed, only the front part of each half of the data is valid (in particular, if the number of valid data is 0, all the data are invalid), and there are only 5 cases where each group is subjected to valid data combination in the second-stage operation. And the first data of the second half of the data of each group is directly arranged behind the last effective data of the first half of the data (particularly, if the number of the effective data of the first half of the data is 0, the second half of the data directly covers the previous data), the combination mode is very simple.

A third level of operation is performed. All 16 data are combined into one group of 8 data each. And combining the first half 8 data with the second half 8 data according to the value of validNum0S1 to obtain output data. The combination is similar to the second stage except that the valid combination case becomes 9. And obtaining the last valid data, which is marked as validNumOut. Then:

validNumOut＝validNum0S1+validNum1S1。

this method of grouping into hierarchical combinations is not very likely due to the fact that each set of valid data is available. After each operation, the effective data of the corresponding group is placed at the forefront, thereby simplifying the complexity of the combination at the next stage.

As can be seen from the above steps, the combination case is most the last stage, except that the case of each group of combinations of the first stage is a fixed value, and the combination case is N/2+ 1. For 24 interfaces, the most combined situation is only 13, and the logic complexity is greatly reduced. The invention has simple overall logic, and the time sequence and the area of the chip can be optimized.

It should be noted that, although an example of grouping hierarchical combination data is given in the present embodiment, this is not a limitation of the present application.

Optionally, after the first-stage valid data combination, the packet merging step may be selected to be performed: the four groups of interfaces are combined into one group, and the effective data of each group of the four groups of interfaces are already positioned on the front side, so when the interfaces are combined, compared with the method of directly enumerating the data combination of 16 interfaces in an enumeration mode or other modes, the logic is simplified, and the optimization of the time sequence and the area of a chip is further realized.

In addition, the grouping and ranking of interfaces may be adaptively matched based on the number of interfaces or the logical complexity of the data combinations, and in some embodiments, the interfaces may be divided into two, three or more groups, and/or may be divided into two, four, five or more stages, which are all within the scope of the present application.

Optionally, in some embodiments, for example, M is 2, P is 1, the M group data transmission interfaces include a first group data transmission interface and a second group data transmission interface, and in the packet merging step, "merging at least part of the M group data transmission interfaces into P groups based on the number of valid data of the at least part of the groups and performing data combining" is implemented to arrange valid data in the second group data transmission interface in the last valid data in the first group data transmission interface, based on which the data combining manner is simplified.

Optionally, the present embodiment further provides a chip (not shown) having N data transmission interfaces, and processing data by applying the data combination method described above.

Optionally, the present embodiment further provides an apparatus (not shown) applying the data combination method or the chip described above.

The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.