阅读说明：本技术 锁存电路和包括其的半导体存储器件 (Latch circuit and semiconductor memory device including the same ) 是由 李桢埈 于 2021-01-12 设计创作，主要内容包括：本公开提供一种锁存电路和包括其的半导体存储器件。一种锁存电路包括：多个锁存器组,每个锁存器组包括使能锁存器和多个地址锁存器；以及多个锁存宽度调整电路,其分别对应于多个锁存器组,其中,在多个锁存器组的每个中,对应的锁存宽度调整电路设置在对应的锁存器组的使能锁存器和与该使能锁存器相邻的地址锁存器之间,并且在启动操作结束时,根据对应的锁存器组是否被使用来将使能锁存器耦接到相邻的地址锁存器。(The present disclosure provides a latch circuit and a semiconductor memory device including the same. A latch circuit includes: a plurality of latch groups, each latch group including an enable latch and a plurality of address latches; and a plurality of latch width adjusting circuits respectively corresponding to the plurality of latch groups, wherein in each of the plurality of latch groups, the corresponding latch width adjusting circuit is disposed between the enable latch of the corresponding latch group and the address latch adjacent to the enable latch, and at the end of the start-up operation, couples the enable latch to the adjacent address latch according to whether the corresponding latch group is used.)

1. A latch circuit, comprising:

a plurality of latch groups, each latch group including an enable latch and a plurality of address latches; and

a plurality of latch width adjusting circuits respectively corresponding to the plurality of latch groups, wherein in each of the plurality of latch groups, the corresponding latch width adjusting circuit is disposed between the enable latch of the corresponding latch group and an address latch adjacent to the enable latch, and at the end of a start-up operation, couples the enable latch to the adjacent address latch according to whether the corresponding latch group is used.

2. The latch circuit according to claim 1, wherein the latch circuit,

wherein, for each of the plurality of latch sets, the corresponding enable latch stores information about whether the corresponding latch set stores valid fuse data, and the plurality of address latches store a repair address.

3. The latch circuit of claim 1, wherein, for each of the plurality of latch sets, each of the enable latch and the plurality of address latches comprises:

a first transmission circuit adapted to transmit fuse data to the first node according to the selection signal;

a second transmission circuit adapted to transmit inverted fuse data to a second node according to the selection signal;

an inverter latch coupled between the first node and the second node; and

an output circuit adapted to drive an output node in accordance with a signal at the first node.

4. The latch circuit according to claim 3, wherein each of the plurality of latch width adjustment circuits comprises, for each of the plurality of latch groups:

a first connection circuit adapted to couple the first node of the enable latch to the first node of the adjacent address latch according to an enable complete signal and a signal at the second node of the enable latch.

5. The latch circuit according to claim 4, wherein the first connection circuit comprises:

a first transistor adapted to couple the first node of the enable latch to a first intermediate node according to a signal at a second node of the enable latch; and

a second transistor adapted to couple the first intermediate node to the first node of the adjacent address latch according to the enable complete signal.

6. The latch circuit according to claim 3, wherein each of the plurality of latch width adjusting circuits comprises:

a second connection circuit adapted to couple the second node of the enable latch to the second node of the adjacent address latch according to an enable complete signal and a signal at the second node of the enable latch.

7. The latch circuit according to claim 6, wherein the second connection circuit comprises:

a third transistor adapted to couple the second node of the enable latch to a second intermediate node according to a signal at the second node of the enable latch; and

a fourth transistor adapted to couple the second intermediate node to the second node of the adjacent address latch according to the enable complete signal.

8. A semiconductor memory device comprising:

a memory cell array including normal memory cells and redundant memory cells for replacing repair target memory cells;

a nonvolatile memory including a plurality of fuse sets for programming a repair address of the repair target memory cell, the nonvolatile memory adapted to sequentially output fuse data programmed in the plurality of fuse sets in response to a start signal;

a latch circuit including a plurality of latch groups corresponding to the plurality of fuse groups, respectively, the latch circuit being adapted to store fuse data supplied from the corresponding fuse group into the plurality of latch groups, and to output the stored fuse data as repair information in a case where a width of an unused latch group among the plurality of latch groups is adjusted in response to a startup completion signal; and

a repair control circuit adapted to control a repair operation for replacing the repair target memory cell with the redundant memory cell based on the repair information.

9. The semiconductor memory device according to claim 8, wherein each of the plurality of latch groups comprises:

an enable latch adapted to store information about whether a corresponding latch set stores valid fuse data; and

a plurality of address latches adapted to store the repair address in the fuse data.

10. The semiconductor memory device according to claim 9, wherein the latch circuit comprises:

a plurality of latch width adjustment circuits corresponding to the plurality of latch groups, wherein in each of the plurality of latch groups, the corresponding latch width adjustment circuit is disposed between the enable latch of the corresponding latch group and an address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch according to the enable completion signal and information stored in the enable latch.

11. The semiconductor memory device of claim 10, wherein, for each of the plurality of latch groups, each of the enable latch and the plurality of address latches comprises:

a first transmission circuit adapted to transmit fuse data to the first node according to the selection signal;

a second transmission circuit adapted to transmit inverted fuse data to a second node according to the selection signal;

an inverter latch coupled between the first node and the second node; and

an output circuit adapted to drive an output node in accordance with a signal at the first node.

12. The semiconductor memory device according to claim 11, wherein each of the plurality of latch width adjustment circuits comprises, for each of the plurality of latch groups:

a first transistor adapted to couple the first node of the enable latch to a first intermediate node according to a signal at a second node of the enable latch;

a second transistor adapted to couple the first intermediate node to the first node of the adjacent address latch according to the enable complete signal;

a third transistor adapted to couple the second node of the enable latch to a second intermediate node according to a signal at the second node of the enable latch; and

a fourth transistor adapted to couple the second intermediate node to the second node of the adjacent address latch according to the enable complete signal.

13. The semiconductor memory device according to claim 8, wherein the nonvolatile memory includes any one of an array electric fuse (ARE) circuit, a laser fuse circuit, a NAND flash memory, a NOR flash memory, a Phase Change Random Access Memory (PCRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FeRAM), a Magnetic Random Access Memory (MRAM), and a spin transfer magnetic random access memory (STT-MRAM).

14. A latch circuit, comprising:

a first latch adapted to transmit first data to a first node and to transmit inverted first data to a second node in response to a select signal being enabled during a power-up operation, and to latch data at the first node and the second node;

a second latch adapted to transmit second data to a third node and to transmit inverted second data to a fourth node in response to the selection signal, and to latch data at the third node and the fourth node; and

a latch width adjustment circuit adapted to couple the first node to the third node and the second node to the fourth node in response to data at the second node and a start-up completion signal enabled after the power-up operation.

15. The latch circuit of claim 14, wherein the first latch comprises:

a first transmission circuit adapted to transmit the first data to the first node according to the selection signal;

a second transmission circuit adapted to transmit the inverted first data to the second node according to the selection signal; and

a first inverter latch coupled between the first node and the second node.

16. The latch circuit of claim 14, wherein the second latch comprises:

a third transmission circuit adapted to transmit the second data to the third node according to the selection signal;

a fourth transmission circuit adapted to transmit the inverted second data to the fourth node according to the selection signal; and

a second inverter latch coupled between the third node and the fourth node.

17. The latch circuit of claim 14, wherein the latch width adjustment circuit comprises:

a first transistor adapted to couple the first node to a first intermediate node according to data at the second node;

a second transistor adapted to couple the first intermediate node to the third node according to the enable complete signal;

a third transistor adapted to couple the second node to a second intermediate node according to data at the second node; and

a fourth transistor adapted to couple the second intermediate node to the fourth node according to the enable complete signal.

18. A semiconductor memory device comprising:

a plurality of fuse sets adapted to program a repair address of a repair target memory cell as fuse data and to output the fuse data in each fuse set in response to a start signal;

a plurality of latch groups, each latch group corresponding to each fuse group and adapted to receive and store fuse data from the corresponding fuse group and output the stored fuse data as repair information; and

a repair control circuit adapted to control a repair operation on the repair target memory cell based on the repair information,

wherein each latch set includes:

an enable latch adapted to store information indicating whether the set of latches stores valid fuse data;

a plurality of address latches including a first address latch adjacent to the enable latch and the remaining address latches in parallel, adapted to store the fuse data; and

a latch width adjustment circuit adapted to couple the enable latch and the first address latch when the set of latches is not in use and a start up complete signal is enabled.

Technical Field

Embodiments of the present invention relate generally to semiconductor design technology, and more particularly, to a semiconductor memory device for transferring data from a nonvolatile memory to a latch circuit.

Background

Generally, a semiconductor memory device is additionally equipped with spare memory cells (redundant cells) for replacing defective memory cells that cannot operate under normal conditions due to defects in a memory cell array of the device. The replacement of defective memory cells in this manner serves the purpose of increasing product yield.

To this end, the semiconductor memory device includes a fuse circuit for programming one or more repair addresses corresponding to the redundant cell and the defective cell, and stores the repair addresses programmed into the fuse circuit as repair information in a latch circuit during a start-up operation. During normal operation, the semiconductor memory device may compare an external address with repair information stored in the latch circuit. In addition, the semiconductor memory device may perform a repair operation for accessing the corresponding redundant cell instead of the defective cell assigned by the external address when the external address is the same as the repair information.

The latching circuit is susceptible to soft errors in which the stored value changes due to particles induced by the radioisotope (neutron). During or after the start-up operation, latch inversion occurs when the latch circuit is reset or when repair information stored in the latch circuit is changed due to a soft error. Due to this phenomenon, the latch circuit loses the stored repair information, which may cause malfunction when the semiconductor memory device performs a repair operation.

Disclosure of Invention

Embodiments of the present invention relate to a semiconductor memory device capable of adjusting a width of a latch circuit by coupling an enable fuse and an address fuse of an unused latch group in the latch circuit after a start-up operation or a power-up operation.

According to one embodiment of the present invention, a latch circuit includes: a plurality of latch groups, each latch group including an enable latch and a plurality of address latches; and a plurality of latch width adjusting circuits respectively corresponding to the plurality of latch groups, wherein in each of the plurality of latch groups, the corresponding latch width adjusting circuit is disposed between the enable latch of the corresponding latch group and the address latch adjacent to the enable latch, and at the end of the start-up operation, couples the enable latch to the adjacent address latch according to whether the corresponding latch group is used.

According to one embodiment of the present invention, a semiconductor memory device includes: a memory cell array including normal memory cells and redundant memory cells for replacing repair target memory cells; a nonvolatile memory including a plurality of fuse sets for programming a repair address of a repair target memory cell, the nonvolatile memory adapted to sequentially output fuse data programmed in the fuse sets in response to a start signal; a latch circuit including a plurality of latch groups corresponding to the plurality of fuse groups, respectively, the latch circuit being adapted to store fuse data supplied from the corresponding fuse group into the plurality of latch groups, and to output the stored fuse data as repair information while adjusting a width of an unused latch group among the plurality of latch groups in response to a startup completion signal; and a repair control circuit adapted to control a repair operation for replacing the repair target memory cell with the redundant memory cell based on the repair information.

According to one embodiment of the present invention, a latch circuit includes: a first latch adapted to transmit first data to the first node and inverse first data to the second node in response to a select signal being enabled during a power-up operation, and latch the data at the first node and the second node; a second latch adapted to transmit the second data to the third node and the inverted second data to the fourth node in response to the selection signal, and latch the data at the third node and the fourth node; and a latch width adjustment circuit adapted to couple the first node to the third node and the second node to the fourth node in response to the data at the second node and the enable completion signal enabled after the power-on operation.

According to one embodiment of the present invention, a semiconductor memory device includes: a plurality of fuse sets adapted to program a repair address of a repair target memory cell as fuse data, and to output the fuse data in each fuse set in response to a start signal; a plurality of latch groups, each latch group corresponding to each fuse group and adapted to receive and store fuse data from the corresponding fuse group and output the stored fuse data as repair information; and a repair control circuit adapted to control a repair operation on a repair target memory cell based on the repair information, wherein each latch group includes: an enable latch adapted to store information indicating whether the set of latches stores valid fuse data; a plurality of address latches including a first address latch adjacent to the enable latch and the remaining address latches in parallel, adapted to store fuse data; and a latch width adjustment circuit adapted to couple the enable latch and the first address latch when the set of latches is not used and the enable completion signal is enabled.

These and other features and advantages of the present invention will be better understood by those of ordinary skill in the art from the following detailed description of the various embodiments of the invention taken in conjunction with the accompanying drawings.

Drawings

Fig. 1 is a block diagram showing a configuration of a semiconductor memory device including a latch circuit according to an embodiment of the present invention.

Fig. 2 is a diagram illustrating a latch circuit such as in fig. 1.

Fig. 3 is a block diagram illustrating a first latch set according to an embodiment of the present invention.

Fig. 4 is a circuit diagram showing a first latch group such as fig. 3.

Fig. 5A and 5B are block diagrams illustrating a latch circuit according to another embodiment of the present invention.

Detailed Description

Embodiments of the present invention are described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. Note that references to "one embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term "embodiments" as used herein does not necessarily refer to all embodiments.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, if not to have the same or similar nomenclature. Thus, a first element in one instance may also be referred to as a second element or a third element in another instance without any alteration of the indicated element itself.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected to, or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Communication between two elements, whether connected/coupled directly or indirectly, may be wired or wireless unless otherwise indicated or the context dictates otherwise.

As used herein, the singular form may also include the plural form and vice versa unless the context clearly dictates otherwise.

It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Hereinafter, embodiments of the present invention are described with reference to the drawings.

Fig. 1 is a block diagram showing the configuration of a semiconductor memory device 100 including a latch circuit 160 according to an embodiment of the present invention. Fig. 2 is a diagram illustrating the latch circuit 160 of fig. 1.

Referring to fig. 1, a semiconductor memory device 100 may include a memory cell region 110, a row circuit 120, a column circuit 130, a data input/output (I/O) circuit 140, a nonvolatile memory 150, a latch circuit 160, and a repair control circuit 170.

The semiconductor memory device 100 may include a command decoder (not shown) and an activation signal generator (not shown). The command decoder may generate a refresh signal REF (not shown), a write signal WT, a read signal RD, an activation signal ACT (not shown), and a precharge signal PCG (not shown) by decoding external commands RST,/CS,/RAS,/CAS, and/WE (not shown) input from an external source. The activation signal generator may generate a row activation signal RACT in response to the activation signal ACT and the precharge signal PCG. Further, the semiconductor memory device 100 may include: an address buffer (not shown) for buffering an external input address and outputting a row address RADD and a column address CADD; and an address decoder (not shown) for generating a block (mat) activation signal XMAT # according to the row address RADD.

The memory cell region 110 may include a plurality of memory cells MC each for storing data. The memory cells MC may be coupled to the row circuit 120 through word lines WL and to the column circuit 130 through bit lines BL. Data may be stored in memory cells selected based on a word line activation signal output from the row circuit 120 and a column selection signal output from the column circuit 130. According to one embodiment, the memory cell region 110 may be formed of volatile memory cells. Preferably, the memory cell area 110 is formed of Dynamic Random Access Memory (DRAM) memory cells.

The memory cell region 110 may include a normal cell region 112 in which normal memory cells are disposed and a redundant cell region 114 in which redundant memory cells are disposed. When a defective memory cell (which may also be referred to as a repair target memory cell) is detected in the normal cell region 112, a normal word line (repair target word line) in which the defective memory cell is located may be replaced with a redundant word line of the redundant cell region 114.

The nonvolatile memory 150 may include a plurality of fuse sets FSET0 through FSETa for programming an address (repair address) of a repair target memory cell. Each of the fuse sets FSET0 through FSETa may include an enable fuse EF and a plurality of address fuses AF1 through AFb. The enable fuse EF may program information as to whether the corresponding fuse set stores a valid repair address. For example, when the enable fuse EF is programmed with a high bit, it is determined that the corresponding fuse set stores the valid repair address. The address fuses AF1 through AFb can program respective bits of the repair address and include a fuse cell for each bit of the repair address. For example, when the 5-bit row address RADD is configured, each of the fuse sets FSET0 through FSETa includes the first through fifth address fuses AF1 through AF 5. The enable fuse EF and the address fuses AF 1-AFb can be programmed with a low bit when the corresponding fuse set is not used.

The non-volatile memory 150 may include any of various types of memory, such as array electrical fuse (ARE) circuitry, laser fuse circuitry, NAND flash memory, NOR flash memory, Phase Change Random Access Memory (PCRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), Magnetic Random Access Memory (MRAM), and/or spin transfer magnetic random access memory (STT-MRAM). Hereinafter, an arrangement in which the nonvolatile memory 150 includes an ARE circuit is illustrated as an example.

The nonvolatile memory 150 may output a repair address in which fuse data FDATA <0: b > is programmed to the latch circuit 160 in response to the enable signal BOOTUP. At this time, the nonvolatile memory 150 may provide the selection signal FSEL <0: a > to the latch circuit 160 together with the fuse data FDATA <0: b >. As an example, in the following embodiments, the semiconductor memory device operates in response to a start signal BOOTUP associated with a start operation. In one embodiment, a semiconductor memory device may operate in response to a power-on signal related to an initialization operation such as a power-on operation.

The latch circuit 160 may include a plurality of latch groups (not shown) corresponding to the fuse groups FSET0 through FSETa, respectively. Latch circuit 160 may sequentially store fuse data FDATA <0: b > supplied from the corresponding fuse sets FSET0 through FSETa into the latch sets in response to selection signals FSEL <0: a >.

Referring to fig. 2, the latch circuit 160 may include latch groups LSET0 to LSETa corresponding to the fuse groups FSET0 to FSETa, respectively. For example, the latch circuit 160 may include (a +1) latch groups LSET0 to LSETa corresponding to (a +1) fuse groups FSET0 to FSETa, respectively, and the nonvolatile memory 150 may supply the latch circuit 160 with the selection signal FSEL <0: a > having (a +1) bits so as to store the fuse data FDATA <0: b > to the corresponding latch group of the (a +1) latch groups LSET0 to LSETa. The latch sets LSET 0-LSETa may store fuse data FDATA <0: b > in response to corresponding bits of select signals FSEL <0: a >. For example, first latch set LSET0 may store fuse data FDATA <0> in response to first bit FSEL <0> (first select signal FSEL <0>) of select signals FSEL <0: a >.

As shown in fig. 3, each of the latch groups LSET0 through LSETa may include an enable latch ENL and a plurality of address latches AL1 through ALb. The enable latch ENL may store fuse data corresponding to the enable fuse EF, that is, may store information on whether the corresponding latch set stores valid fuse data. For example, when the enable latch ENL stores a high bit, the corresponding latch group is determined to store valid fuse data. The address latches AL1 through ALb may store fuse data corresponding to the address fuses AF1 through AFb, and include latch cells whose numbers correspond to the bit numbers of the repair address. For example, when the 5-bit row address RADD is configured, the latch groups LSET0 through LSETa include first through fifth address latches AL1 through ALb, respectively.

The latch circuit 160 may output the stored fuse data as the repair information INF _ R to the repair control circuit 170 according to the block activation signal XMAT #. For reference, the memory cell area 110 may be divided into a plurality of cell matrices (cell blocks), and each cell block may be selected in response to a corresponding block activation signal XMAT #. A set number of redundancy word lines may be disposed in each cell block, and fuse sets FSET0 through FSETa and latch sets LSET0 through LSETa may be allocated to the redundancy word lines, so that each cell block includes a dedicated fuse and latch set. For example, assuming that one redundancy word line is assigned to each of the first to eighth cell blocks, the first fuse set FSET0 and the first latch set LSET0 may be allocated to the redundancy word line disposed in the first cell block, and the second fuse set FSET1 and the second latch set LSET1 may be allocated to the redundancy word line disposed in the second cell block. In this manner, the eighth fuse set FSET7 and the eighth latch set LSET7 may be allocated to the redundancy word line provided in the eighth cell block. Accordingly, when the block activation signal XMAT # for selecting a specific cell block (e.g., a first cell block) is enabled according to the row address RADD, the latch circuit 160 may provide the stored fuse data from the first fuse set FSET0 and the first latch set LSET0 as the repair information INF _ R to the repair control circuit 170.

Further, the latch circuit 160 may include a plurality of latch width adjustment circuits 200 corresponding to the latch groups LSET0 to LSETa. Each latch width adjustment circuit 200 may be disposed between an enable latch ENL of a corresponding latch group and an address latch adjacent to the enable latch ENL (i.e., a first address latch AL 1). When the enable complete signal BOOTUP _ END is enabled, each latch width adjustment circuit 200 may couple the enable latch ENL to an adjacent address latch AL1 depending on whether the corresponding latch set is used. The start up completion signal BOOTUP _ END is enabled when or after the start up operation ENDs. In some embodiments, each latch width adjustment circuit 200 may couple an enable latch ENL to an adjacent address latch AL1 when the corresponding set of latches is not used at the end of the start-up operation. As a result, it is possible to have an effect of increasing the width of the latch circuit 160. That is, the physical width of the latch circuit 160 may be adjusted depending on whether or not the latch set is used. The latch circuit 160 may adjust the width of an unused latch set among the latch sets LSET0 through LSETa in response to the enable completion signal BOOTUP _ END. According to one embodiment, neutron attacks are spread due to the increase in the width of the unused set of latches, thereby preventing latch inversion and reducing the Neutron Soft Error Rate (NSER). The detailed configuration and operation of the latch circuit 160 are explained with reference to fig. 3 and 4.

Referring back to fig. 1, the repair control circuit 170 may control the row circuit 120 to perform a repair operation according to repair information INF _ R supplied from the latch circuit 160. The repair control circuit 170 may compare the repair information INF _ R with an externally input row address RADD and output a repair control signal HITSUM based on the comparison result. The repair control circuit 170 may enable the repair control signal HITSUM if the row address RADD is the same as the repair information INF _ R.

The row circuit 120 may activate a word line selected based on a row address RADD in response to a row activation signal RACT. When the repair control signal HITSUM is enabled, the row circuit 120 may activate the redundant word line instead of the word line selected by the row address RADD. In this way, the repair target word line corresponding to the repair information INF _ R stored in the latch circuit 160 can be replaced with the redundant word line.

The column circuit 130 can access data of the bit line BL selected based on the column address CADD.

During a read operation, the data I/O circuit 140 may output data transferred from the bit line BL selected based on the column address CADD to the data pad DQ in response to a read signal RD. During a write operation, the data I/O circuit 140 may transfer data input via the data pad DQ to the bit line BL corresponding to the column address CADD in response to the write signal WT.

As described above, in the semiconductor memory device 100, the nonvolatile memory 150 may program the repair address in its fuse set and output the repair information INF _ R to the latch circuit 160 in response to the enable signal BOOTUP. Herein, the repair information INF _ R stored in the nonvolatile memory 150 is not directly used, but the repair information INF _ R is moved and stored in the latch circuit 160 and then used. The reason is as follows.

Since the nonvolatile memory 150 is formed in an array type, it takes a set amount of time to call out data stored therein. Since it is impossible to instantaneously read out data from the nonvolatile memory 150, it is impossible to perform a repair operation by directly using data stored in the nonvolatile memory 150. Accordingly, a boot operation in which the repair information INF _ R stored in the nonvolatile memory 150 is transferred to and stored in the latch circuit 160 is performed, and then after the boot operation, the repair operation can be performed using the data stored in the latch circuit 160.

Hereinafter, referring to fig. 3 and 4, the configuration and operation of the latch circuit 160 will be described in detail. Each of the latch sets LSET0 through LSETa may have substantially the same configuration and operation; thus, first latch set LSET0 is described as an example.

Fig. 3 is a block diagram illustrating a first latch set LSET0 according to one embodiment of the present invention.

Referring to fig. 3, first latch set LSET0 may include an enable latch ENL and address latches AL1 through Alb. The latch width adjustment circuit 200 may be disposed between the enable latch ENL and a first address latch AL1 adjacent to the enable latch ENL.

The enable latch ENL and the address latches AL1 to Alb may store fuse data FDATA <0: b > in response to the first selection signal FSEL <0> and output repair information INF _ R in response to the block activation signal XMAT #. For example, the enable latch ENL may store a first bit FDATA <0> of fuse data FDATA <0: b > according to the first selection signal FSEL <0>, and output the stored fuse data as enable information EN _ INF according to the block activation signal XMAT #. First address latch AL1 may store second bit FDATA <1> of fuse data FDATA <0: b > according to first selection signal FSEL <0>, and output the stored fuse data as address information A1_ INF according to block activation signal XMAT #. The enable information EN _ INF and the address information a1_ INF to Ab _ INF output from the enable latch ENL and the address latches AL1 to Alb may constitute repair information INF _ R. Further, the enable latch ENL may provide the UNUSED FLAG signal UNUSED _ FLAG based on the first bit FDATA <0> of the fuse data FDATA <0: b > during the start-up operation. The UNUSED FLAG signal UNUSED _ FLAG may indicate whether the corresponding latch set is used.

Latch width adjustment circuit 200 may selectively couple enable latch ENL to first address latch AL1 in response to enable complete signal BOOTUP _ END and UNUSED FLAG signal UNUSED _ FLAG.

Fig. 4 is a circuit diagram illustrating first latch set LSET0 of fig. 3.

Referring to fig. 4, an arrangement is shown in which a first latch set LSET0 is allocated to a first cell block so as to operate according to a first block activation signal XMAT 0.

Referring to fig. 4, the enable latch ENL may include a first transfer circuit TM1, a second transfer circuit TM2, an inverter latch INV _ L1, and an output circuit OC 1.

The first transfer circuit TM1 may transfer the corresponding fuse data FDATA <0> to the first node FLT0 according to the first selection signal FSEL <0 >. The first transfer circuit TM1 may be composed of a transistor coupled between the first input node to which fuse data FDATA <0> is input and the first node FLT0 and turned on/off in response to the first selection signal FSEL <0 >. The second transmission circuit TM2 may transmit the inverted fuse data FDATAB <0> to the second node FLB0 according to the first selection signal FSEL <0 >. The second transmission circuit TM2 may be composed of a transistor coupled between the second input node to which the inverted fuse data FDATAB <0> is input and the second node FLB0 and turned on/off in response to the first selection signal FSEL <0 >. For reference, the first latch set LSET0 may further include an inverter INV # for generating inverted fuse data FDATAB <0: b > by inverting fuse data FDATA <0: b >.

The inverter latch INV _ L1 may be coupled between the first node FLT0 and the second node FLB 0. The inverter latch INV _ L1 may invert a signal at the first node FLT0 to latch the inverted signal at the second node FLB0, and invert a signal at the second node FLB0 to latch the inverted signal at the first node FLT 0. An enable FLAG signal EN _ FLAG may be output from the first node FLT0, and an UNUSED FLAG signal UNUSED _ FLAG may be output from the second node FLB 0. The inverter latch INV _ L1 may be composed of cross-coupled inverters.

The output circuit OC1 may be coupled between a ground Voltage (VSS) terminal and an output node, and outputs enable information EN _ INF according to the first block activation signal XMAT0 and a signal at the first node FLT0 (i.e., an enable FLAG signal EN _ FLAG). When the first block activation signal XMAT0 and the enable FLAG signal EN _ FLAG are enabled, the output circuit OC1 may drive the output node to the ground Voltage (VSS). The output circuit OC1 may be composed of transistors coupled in series between a ground Voltage (VSS) terminal and an output node and turned on/off in response to the first block activation signal XMAT0 and the enable FLAG signal EN _ FLAG, respectively.

Since each of the address latches AL1 through ALb may have substantially the same configuration and operation as the enable latch ENL, a detailed description of the address latches is omitted. The address latches AL1 through Alb may transfer corresponding fuse data FDATA <1: b > to the first nodes FLT1 through FLTb and transfer inverted fuse data FDATAB <1: b > to the second nodes FLB1 through FLBb according to the first selection signal FSEL <0 >. The address latches AL1 to Alb may output address information a1_ INF to Ab _ INF according to the first block activation signal XMAT0 and corresponding signals (i.e., address FLAG signals a1_ FLAG to Ab _ FLAG) at the first nodes FLT1 to FLTb.

The latch width adjustment circuit 200 may include a first connection circuit 210 and a second connection circuit 220.

First connection circuit 210 may couple first node FLT0 of enable latch ENL to first node FLT1 of first address latch AL1 according to enable complete signal BOOTUP _ END and UNUSED _ FLAG signal UNUSED. The first connection circuit 210 may include a first transistor T1 and a second transistor T2 coupled in series. The first transistor T1 may couple the first node FLT0 of the enable latch ENL to the first intermediate node IND1 according to the UNUSED FLAG signal UNUSED _ FLAG. The second transistor T2 may couple the first intermediate node IND1 to the first node FLT1 of the first address latch AL1 according to the enable completion signal BOOTUP _ END.

Second connection circuit 220 may couple second node FLB0 of enable latch ENL to second node FLB1 of first address latch AL1 in accordance with enable complete signal BOOTUP _ END and UNUSED _ FLAG signal UNUSED. The second connection circuit 220 may include a third transistor T3 and a fourth transistor T4 coupled in series. The third transistor T3 may couple the second node FLB0 of the enable latch ENL to the second intermediate node IND2 according to the UNUSED FLAG signal UNUSED _ FLAG. The fourth transistor T4 may couple the second intermediate node IND2 to the second node FLB1 of the first address latch AL1 according to the enable completion signal BOOTUP _ END.

When the first and second connection circuits 210 and 220 are turned on, the first node FLT0 of the enable latch ENL is coupled to the first node FLT1 of the first address latch AL1, and the second node FLB0 of the enable latch ENL is coupled to the second node FLB1 of the first address latch AL 1. Accordingly, such an arrangement has the effect of increasing the latch width since the input/output nodes of the inverter latch INV _ L1 of the enable latch ENL are respectively coupled to the input/output nodes of the inverter latch of the first address latch AL1 adjacent to the enable latch ENL.

As an example, fig. 4 shows that the latch width adjustment circuit 200 includes both the first connection circuit 210 and the second connection circuit 220, but the present invention is not limited to this configuration. In another embodiment, the latch width adjustment circuit 200 may include only one of the first connection circuit 210 and the second connection circuit 220.

Hereinafter, referring to fig. 1 to 4, an operation of the semiconductor memory device 100 according to an embodiment is explained.

First, the nonvolatile memory 150 may output a programmed repair address as fuse data FDATA <0: b > to the latch circuit 160 in response to the boot signal BOOTUP during a boot operation. At this time, the nonvolatile memory 150 may provide the selection signal FSEL <0: a > to the latch circuit 160 together with the fuse data FDATA <0: b >. Latch circuit 160 may sequentially store fuse data FDATA <0: b > supplied from the corresponding fuse sets FSET0 through FSETa into latch sets LSET0 through LSETa according to selection signals FSEL <0: a >.

For example, when the first selection signal FSEL <0> is enabled, the first transmission circuit (i.e., TM1) and the second transmission circuit (i.e., TM2) of the enable latch ENL and the address latches AL1 through Alb included in the first latch set LSET0 are turned on. Accordingly, fuse data FDATA <0: b > is transferred to the first nodes FLT0 through FLTb, and inverted fuse data FDATAB <0: b > is transferred to the second nodes FLB0 through FLBb. When the enable fuse EF is programmed by the high bit, since the first fuse set FSET0 stores an effective repair address, the fuse data FDATA <0> becomes a signal of a logic high level, and thus the enable FLAG signal EN _ FLAG of a logic high level may be generated and the UNUSED FLAG signal UNUSED _ FLAG of a logic low level may be generated. In contrast, in the case where the enable fuse EF is programmed with a low bit, since the first fuse set FSET0 stores an invalid repair address, the fuse data FDATA <0> becomes a signal of a logic low level, and thus the enable FLAG signal EN _ FLAG of a logic low level may be generated and the UNUSED FLAG signal UNUSED _ FLAG of a logic high level may be generated. That is, when the first fuse set FSET0 is not used, the UNUSED FLAG signal UNUSED _ FLAG having a logic high level is generated.

Through the above start-up operation, the repair addresses programmed in the fuse sets FSET0 through FSETa of the nonvolatile memory 150 can be transferred and stored in the latch sets LSET0 through LSETa of the latch circuit 160, respectively.

During a normal operation after the start-up operation, when a word line provided in the first cell block is selected, the first block activation signal XMAT0 is enabled. The enable latch ENL of the first latch set LSET0 may output enable information EN _ INF according to an enable FLAG signal EN _ FLAG at the first node FLT 0. Likewise, the address latches AL1 through Alb of the first latch group LSET0 may output address information a1_ INF through Ab _ INF according to address FLAG signals a1_ FLAG through Ab _ FLAG at the first nodes FLT1 through FLTb. The repair control circuit 170 controls the row circuit 120 to perform a repair operation according to the repair information INF _ R supplied from the latch circuit 160.

When the enable completion signal BOOTUP _ END becomes enabled after the start-up operation, the latch width adjustment circuit 200 may couple the enable latch ENL to the adjacent address latch AL1 according to whether the corresponding latch group is used. That is, the first connection circuit 210 may couple the first node FLT0 of the enable latch ENL to the first node FLT1 of the first address latch AL1, and the second connection circuit 220 may couple the second node FLB0 of the enable latch ENL to the second node FLB1 of the first address latch AL1, according to the enable completion signal BOOTUP _ END and the UNUSED FLAG signal UNUSED _ FLAG. When the corresponding latch set is not used, latch width adjustment circuit 200 may couple enable latch ENL to its adjacent first address latch AL1, thereby increasing the physical width of latch circuit 160. That is, according to one embodiment, at the end of the start-up operation, neutron attacks are distributed due to the increase in width of the unused set of latches, thereby preventing latch inversion and reducing NSER.

In one embodiment, one latch width adjustment circuit 200 is disposed between the enable latch ENL and the adjacent address latch AL1 in each latch group, but the present invention is not limited to this configuration. In another embodiment, two or more latch width adjustment circuits may be provided in each latch group.

Fig. 5A and 5B are block diagrams illustrating a latch circuit according to another embodiment of the present invention. In fig. 5A and 5B, a first latch group LSET0 and a latch width adjustment circuit corresponding thereto are shown.

Referring to fig. 5A, the latch circuit may include a first latch width adjustment circuit 310 and a second latch width adjustment circuit 320 corresponding to the first latch group LSET 0. First latch width adjustment circuit 310 may be disposed between enable latch ENL and first address latch AL1 (i.e., the latch in first latch set LSET0 that is closest to enable latch ENL). Second latch width adjustment circuit 320 may be disposed between first address latch AL1 and second address latch AL2 (i.e., the latch in first latch set LSET0 that is next closest to enable latch ENL). That is, by providing two or more latch width adjustment circuits 310 and 320 in each latch group, it is possible to further increase the width of the latch circuit.

Referring to fig. 5B, the latch circuit may include a plurality of latch width adjustment circuits 410_1 to 410_ B corresponding to the first latch group LSET 0. The latch width adjustment circuit 410_1 may be disposed between the enable latch ENL in the first latch set LSET0 and the first address latch AL 1. As shown in fig. 5B, the remaining latch width adjustment circuits (i.e., 410_2 to 410_ B) are disposed between the respective adjacent pairs of address latches. By providing a plurality of latch width adjustment circuits 410_1 to 410_ b in this manner, the width of the latch circuit can be further increased although the area is partially increased.

As described above, according to an embodiment of the present invention, the width of a latch circuit can be increased by coupling an enable latch to at least one adjacent address latch when a corresponding latch group is not used. Thus, neutron attacks are distributed due to the increase in latch width, preventing latch inversion and reducing NSER.

It should be noted that while the invention has been described in connection with various embodiments thereof, this description is not intended to limit the invention. Those skilled in the art will recognize that various changes may be made to any of the disclosed embodiments without departing from the technical spirit of the present invention.

For example, the logic gates and transistors provided as examples in the above-described embodiments may be of different types and configured in different ways depending on the polarity of the input signal.

Although the present disclosure has been described with respect to particular embodiments, the present invention itself is intended to embrace all such modifications and variations of any such embodiments that fall within the scope of the appended claims.