阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 张海洋 陈建 柯星 于 2020-05-29 设计创作，主要内容包括：一种半导体结构及其形成方法,形成方法包括：形成多个分立的叠层结构,叠层结构包括第一掺杂层、位于第一掺杂层上的半导体柱以及位于半导体柱上的第二掺杂层；形成保形覆盖半导体柱以及第二掺杂层的栅极材料层；在半导体柱之间形成层间介质层,层间介质层的顶面低于第二掺杂层的底面；对层间介质层露出的栅极材料层进行一次或多次原子层刻蚀处理,形成栅极结构,原子层刻蚀处理包括：在露出层间介质层的栅极材料层的表面形成有机物层,去除有机物层。有机物层使得栅极材料层最表面的原子与内层原子的键能进一步的减小,在去除有机物层的过程中,能够剥离栅极材料层最表面的原子,经过多次原子层刻蚀处理后,能够形成栅极结构。(A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a plurality of discrete laminated structures, wherein each laminated structure comprises a first doping layer, a semiconductor column positioned on the first doping layer and a second doping layer positioned on the semiconductor column; forming a gate material layer conformally covering the semiconductor pillar and the second doped layer; forming an interlayer dielectric layer between the semiconductor columns, wherein the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; carrying out one or more times of atomic layer etching treatment on the grid material layer exposed out of the interlayer dielectric layer to form a grid structure, wherein the atomic layer etching treatment comprises the following steps: and forming an organic layer on the surface of the grid material layer exposed out of the interlayer dielectric layer, and removing the organic layer. The organic layer enables bond energy of atoms on the outermost surface of the grid material layer and atoms on the inner layer to be further reduced, the atoms on the outermost surface of the grid material layer can be stripped in the process of removing the organic layer, and a grid structure can be formed after multiple times of atomic layer etching treatment.)

1. A method of forming a semiconductor structure, comprising:

providing a base, wherein the base comprises an initial substrate, a first doping material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doping material layer and a second doping material layer positioned on the semiconductor material layer;

etching the second doping material layer, the semiconductor material layer and the first doping material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doping layer, a semiconductor column located on the first doping layer and a second doping layer located on the semiconductor column;

forming a gate material layer conformally covering the semiconductor pillar and the second doped layer;

after the grid material layer is formed, an interlayer dielectric layer is formed between the semiconductor columns, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer;

performing one or more times of atomic layer etching treatment on the gate material layer exposed out of the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatment comprises the following steps: and forming an organic layer on the surface of the grid material layer exposing the interlayer dielectric layer, and removing the organic layer.

2. The method of forming a semiconductor structure of claim 1, wherein a material of the organic layer comprises a halogen element.

3. The method according to claim 1 or 2, wherein a material of the organic layer includes one or more elements of chlorine, bromine, and fluorine.

4. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the organic layer, the organic layer on the surface of the gate material layer has a thickness of 0.5 nm to 5 nm.

5. The method of claim 1, wherein the organic layer is formed on the surface of the gate material layer using a plasma chemical vapor deposition process.

6. The method of forming a semiconductor structure of claim 1, wherein the organic layer is removed using an anisotropic physical etching process.

7. The method of forming a semiconductor structure of claim 6, wherein the anisotropic physical etching process comprises a plasma ribbon etching process.

8. The method of forming a semiconductor structure of claim 7, wherein the process parameters for performing the plasma ribbon etching process comprise: the included angle between the incident direction of the etching ions and the normal line of the surface of the substrate is more than 10 degrees and less than 45 degrees, the etching ions comprise one or more of He, Ar, Ne, Kr and Xe, the bias voltage is 50V to 1000V, and the pressure of the chamber is 5mTorr to 1000 mTorr.

9. The method of claim 1, wherein in the step of forming the gate material layer, the reactant used comprises a precursor of the gate material layer.

10. The method of forming a semiconductor structure of claim 9, wherein the precursor of the gate material layer comprises a precursor of tungsten.

11. The method of forming a semiconductor structure of claim 1, wherein the layer of gate material is formed using an atomic layer deposition process.

12. The method of forming a semiconductor structure of claim 1, wherein the step of forming the interlevel dielectric layer comprises:

forming an interlayer material film covering the gate material layer, wherein the top surface of the interlayer material film is higher than that of the gate material layer;

carrying out curing treatment on the interlayer material film to form an interlayer material layer;

and etching back the interlayer material layer with partial thickness, and taking the residual interlayer material layer as an interlayer dielectric layer.

13. The method of forming a semiconductor structure of claim 12, wherein a material of the interlayer material film comprises silsesquioxane.

14. The method of forming a semiconductor structure of claim 12, wherein said interlayer material film is subjected to a curing process using an electron beam curing process.

15. The method for forming a semiconductor structure according to claim 1, wherein after the stacked structure is formed, the initial substrate is etched by a certain thickness to form a substrate and a fin portion on the substrate;

the method for forming the semiconductor structure further comprises the following steps: after the fin part is formed and before the grid material layer is formed, forming an isolation layer on the substrate exposed out of the fin part and the first doping layer, wherein the top surface of the isolation layer is higher than the top surface of the fin part and is lower than or flush with the top surface of the first doping layer;

in the step of forming the gate material layer, the gate material layer is formed on the stacked structure where the isolation layer is exposed.

16. A semiconductor structure, comprising:

a substrate;

a stacked structure separated from the substrate; the laminated structure includes: the semiconductor device comprises a first doping layer, a semiconductor column and a second doping layer, wherein the semiconductor column is located on the first doping layer;

a gate material layer conformally covering the semiconductor pillar and the second doping layer;

the interlayer dielectric layer covers part of the side wall of the grid electrode material layer, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer;

and the organic layer is positioned on the surface of the grid material layer exposed out of the interlayer dielectric layer.

17. The semiconductor structure of claim 16, wherein a material of the organic layer comprises a halogen element.

18. The semiconductor structure of claim 16 or 17, wherein the organic layer comprises one or more elements of chlorine, bromine, and fluorine.

19. The semiconductor structure of claim 16, wherein the organic layer at the surface of the gate material layer has a thickness of 0.5 nm to 5 nm.

20. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: the fin part is positioned between the substrate and the first doping layer;

the semiconductor structure further includes: the isolation layer is positioned on the substrate between the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer;

the grid material layer is positioned on the isolation layer and on the top surface and the side wall of the laminated structure higher than the isolation layer.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be shortened in order to accommodate the reduction of process nodes.

The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, and the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (short-channel leakage) is more likely to occur, and the channel leakage current of the transistor is increased.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect.

The fully-wrapped Gate transistor includes a transverse Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor, in which a channel of the VGAA extends in a direction perpendicular to a surface of a substrate, which is advantageous for improving an area utilization efficiency of a semiconductor structure, and thus is advantageous for realizing a further reduction in feature size.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises an initial substrate, a first doping material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doping material layer and a second doping material layer positioned on the semiconductor material layer; etching the second doping material layer, the semiconductor material layer and the first doping material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doping layer, a semiconductor column located on the first doping layer and a second doping layer located on the semiconductor column; forming a gate material layer conformally covering the semiconductor pillar and the second doped layer; after the grid material layer is formed, an interlayer dielectric layer is formed between the semiconductor columns, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; performing one or more times of atomic layer etching treatment on the gate material layer exposed out of the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatment comprises the following steps: and forming an organic layer on the surface of the grid material layer exposing the interlayer dielectric layer, and removing the organic layer.

Optionally, the material of the organic layer includes a halogen element.

Optionally, the material of the organic layer includes one or more elements of chlorine, bromine, and fluorine.

Optionally, in the step of forming the organic layer, the thickness of the organic layer on the surface of the gate material layer is 0.5 nm to 5 nm.

Optionally, a plasma chemical vapor deposition process is used to form the organic layer on the surface of the gate material layer.

Optionally, the organic layer is removed by using an anisotropic physical etching process.

Optionally, the anisotropic physical etching process includes a plasma belt etching process.

Optionally, the process parameters for performing the plasma belt etching process on the organic layer include: the included angle between the incident direction of the etching ions and the normal line of the surface of the substrate is more than 10 degrees and less than 45 degrees, the etching ions comprise one or more of He, Ar, Ne, Kr and Xe, the bias voltage is 50V to 1000V, and the pressure of the chamber is 5mTorr to 1000 mTorr.

Optionally, in the step of forming the gate material layer, the reactant used includes a precursor of the gate material layer.

Optionally, the precursor of the gate material layer includes a precursor of tungsten.

Optionally, the gate material layer is formed by an atomic layer deposition process.

Optionally, the forming step of the interlayer dielectric layer includes: forming an interlayer material film covering the gate material layer, wherein the top surface of the interlayer material film is higher than that of the gate material layer; carrying out curing treatment on the interlayer material film to form an interlayer material layer; and etching back the interlayer material layer with partial thickness, and taking the residual interlayer material layer as an interlayer dielectric layer.

Optionally, the material of the interlayer material film includes silsesquioxane.

Optionally, the interlayer material film is cured by electron beam curing.

Optionally, after the laminated structure is formed, etching the initial substrate with a certain thickness to form a substrate and a fin portion located on the substrate; the method for forming the semiconductor structure further comprises the following steps: after the fin part is formed and before the grid material layer is formed, forming an isolation layer on the substrate exposed out of the fin part and the first doping layer, wherein the top surface of the isolation layer is higher than the top surface of the fin part and is lower than or flush with the top surface of the first doping layer; in the step of forming the gate material layer, the gate material layer is formed on the stacked structure where the isolation layer is exposed.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a stacked structure separated from the substrate; the laminated structure includes: the semiconductor device comprises a first doping layer, a semiconductor column and a second doping layer, wherein the semiconductor column is located on the first doping layer; a gate material layer conformally covering the semiconductor pillar and the second doping layer; the interlayer dielectric layer covers part of the side wall of the grid electrode material layer, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; and the organic layer is positioned on the surface of the grid material layer exposed out of the interlayer dielectric layer.

Optionally, the material of the organic layer includes a halogen element.

Optionally, the organic layer comprises one or more elements of chlorine, bromine, and fluorine.

Optionally, the thickness of the organic layer on the surface of the gate material layer is 0.5 nm to 5 nm.

Optionally, the semiconductor structure further includes: the fin part is positioned between the substrate and the first doping layer; the semiconductor structure further includes: the isolation layer is positioned on the substrate between the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer; the grid material layer is positioned on the isolation layer and on the top surface and the side wall of the laminated structure higher than the isolation layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure provided by the embodiment of the present invention, the gate material layer exposing the interlayer dielectric layer is subjected to one or more atomic layer etching processes to form a gate structure, and the atomic layer etching processes include: forming an organic layer on the surface of the gate material layer exposed from the interlayer dielectric layer, wherein the bond energy of atoms on the outermost surface and atoms in the inner layer in the gate material layer is smaller than that of atoms in the inner layer, the organic layer has free radicals (radial) therein, the free radicals have elements capable of reacting with the gate material layer, so that the bond energy of the atoms on the outermost surface of the gate material layer and the atoms in the inner layer is further reduced, atoms on the outermost surface of the gate material layer can be stripped during the process of removing the organic layer, and thus, in the process of the atomic layer etching treatment, the grid material layer covered by the interlayer dielectric layer is less damaged, and after the atomic layer etching treatment for a plurality of times, the grid material layer exposed out of the interlayer dielectric layer can be removed, and the grid structure has better formation quality, so that the electrical property of the semiconductor structure can be improved.

Drawings

Fig. 1 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, the channel of the vertical all-around gate transistor extends in a direction perpendicular to the normal of the substrate surface, and the source and the drain of the corresponding vertical all-around gate transistor are arranged in the longitudinal direction, so that the area utilization efficiency of the semiconductor structure can be improved, and the reduction of the semiconductor structure is facilitated to realize further feature size reduction. In general, in a fin field effect transistor (FinFET) and a laterally all-around gate array (LGAA), a dummy gate structure occupying a spatial position is formed first, then the dummy gate structure is removed, a gate opening is formed at the position of the original dummy gate structure, then a gate structure is formed in the gate opening, if the gate structure in the vertically all-around gate transistor also adopts the dummy gate structure to occupy the spatial position, in the process of removing the dummy gate structure to form the gate opening, the aspect ratio of the gate opening is high, the dummy gate structure is prone to remain, so that a subsequently formed gate structure is formed on the dummy gate structure, and when the semiconductor structure works, the gate structure cannot directly control a channel, so that the electrical performance of the semiconductor structure is poor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises an initial substrate, a first doping material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doping material layer and a second doping material layer positioned on the semiconductor material layer; etching the second doping material layer, the semiconductor material layer and the first doping material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doping layer, a semiconductor column located on the first doping layer and a second doping layer located on the semiconductor column; forming a gate material layer conformally covering the semiconductor pillar and the second doped layer; after the grid material layer is formed, an interlayer dielectric layer is formed between the semiconductor columns, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; performing one or more times of atomic layer etching treatment on the gate material layer exposed out of the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatment comprises the following steps: and forming an organic layer on the surface of the grid material layer exposing the interlayer dielectric layer, and removing the organic layer.

In the method for forming a semiconductor structure provided by the embodiment of the present invention, the gate material layer exposing the interlayer dielectric layer is subjected to one or more atomic layer etching processes to form a gate structure, and the atomic layer etching processes include: forming an organic layer on the surface of the gate material layer exposed from the interlayer dielectric layer, wherein the bond energy of atoms on the outermost surface and atoms in the inner layer in the gate material layer is smaller than that of atoms in the inner layer, the organic layer has free radicals (radial) therein, the free radicals have elements capable of reacting with the gate material layer, so that the bond energy of the atoms on the outermost surface of the gate material layer and the atoms in the inner layer is further reduced, atoms on the outermost surface of the gate material layer can be stripped during the process of removing the organic layer, and thus, in the process of the atomic layer etching treatment, the grid material layer covered by the interlayer dielectric layer is less damaged, and after the atomic layer etching treatment for a plurality of times, the grid material layer exposed out of the interlayer dielectric layer can be removed, and the grid structure has better formation quality, so that the electrical property of the semiconductor structure can be improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 1 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1, a base is provided, the base comprising an initial substrate 100, a first doped material layer 101 located on the initial substrate 100, a semiconductor material layer 102 located on the first doped material layer 101, and a second doped material layer 103 located on the semiconductor material layer 102.

The initial substrate 100 provides a process platform for the subsequent formation of semiconductor structures.

In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the material of the initial substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the initial substrate can also be silicon on insulator or germanium on insulator.

The first doped material layer 101 provides for the subsequent formation of a first doped layer.

In this embodiment, the semiconductor structure is used to form a PMOS (positive Channel Metal Oxide semiconductor) transistor, when the PMOS transistor works, a carrier in a Channel is a hole, and when a lattice structure of the Channel is subjected to a compressive stress, a migration speed of the hole becomes fast, which can improve an electrical property of the PMOS transistor, and the first doped material layer 101 is made of silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS (negative channel Metal Oxide semiconductor) transistor, when the NMOS transistor operates, a carrier in a channel is an electron, and when a lattice structure of the channel is subjected to a compressive stress, a migration speed of the electron becomes fast, so that an electrical property of the NMOS transistor can be improved, and the first doped material layer is made of silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, As or Sb.

The layer of semiconductor material 102 is used in preparation for the subsequent formation of semiconductor pillars.

In this embodiment, the material of the semiconductor material layer 102 is silicon. In other embodiments, the material of the semiconductor material layer may also be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.

The second layer of doping material 103 is used in preparation for the subsequent formation of a second doping layer.

In this embodiment, the semiconductor structure is used to form a PMOS transistor, when the PMOS transistor works, a carrier in a channel is a hole, and when a lattice structure of the channel is subjected to a compressive stress, a migration speed of the hole becomes fast, which can improve an electrical property of the PMOS transistor, and the second doped material layer 103 is made of silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS transistor, when the NMOS transistor works, the carriers in the channel are electrons, and when the lattice structure of the channel is subjected to a compressive stress, the migration speed of the electrons becomes faster, which can improve the electrical performance of the NMOS transistor, and the material of the second doped material layer 103 is correspondingly silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, As or Sb.

A mask layer 104 is further formed on the second doped material layer 103.

The mask layer 104 is used for subsequently etching the second doping material layer 103, the semiconductor material layer 102 and the first doping material layer 101 to form an etching mask of a laminated structure, wherein the laminated structure comprises a first doping layer, a semiconductor column located on the first doping layer and a second doping layer located on the semiconductor column.

Specifically, the material of the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the mask layer 104 is made of silicon nitride.

Referring to fig. 2, the second doping material layer 103, the semiconductor material layer 102 and the first doping material layer 101 are etched to form a plurality of discrete stacked structures, where each stacked structure includes a first doping layer 105, a semiconductor pillar 106 located on the first doping layer 105, and a second doping layer 107 located on the semiconductor pillar 106.

The stacked structure provides for a subsequently formed fully-wrapped-around gate structure.

Specifically, when the semiconductor structure works, the semiconductor pillar 106 is used as a channel, and the first doped layer 105 and the second doped layer 107 are used as source-drain doped layers of the semiconductor pillar 106, so that stress is provided for the channel, and the migration rate of carriers in the channel is improved.

In this embodiment, the mask layer 104 is used as a mask to etch the second doped material layer 103, the semiconductor material layer 102, and the first doped material layer 101 by using a dry etching process, so as to form a discrete stacked structure. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is beneficial to enabling the appearance of the laminated structure to meet the process requirements, and can etch the second doping material layer 103, the semiconductor material layer 102 and the first doping material layer 101 in the same etching device by replacing etching gas, so that the process steps are simplified.

The method for forming the semiconductor structure further includes: after the laminated structure is formed, the initial substrate 100 with a certain thickness is etched to form a substrate 108 and a fin 109 located on the substrate 108. The first doping layer 105, the second doping layer 107 and the semiconductor pillars 106 are located on the fin portion 109, and an isolation layer is formed on the substrate 108 between the fin portion 109 and the first doping layer 105 in a subsequent step. In other embodiments, in the step of forming the stacked structure, the top of the initial substrate may also be used as an etching stop position, and the initial substrate is not etched after the stacked structure is correspondingly formed.

Referring to fig. 3 and 4, a gate material layer 110 (shown in fig. 4) is formed conformally covering the semiconductor pillars 106 and the second doped layer 107.

The gate material layer 110 provides for the subsequent formation of a gate structure.

In this embodiment, the gate material layer 110 is made of a magnesium-tungsten alloy. In other embodiments, the material of the gate material layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

In this embodiment, the gate material Layer 110 is formed by an Atomic Layer Deposition (ALD) process. The ald process refers to a deposition process in which a vapor phase precursor is alternately pulsed into a reaction chamber to chemisorb and generate a surface reaction on the semiconductor pillar 106 and the second doped layer 107. Through an atomic layer deposition process, the gate material layer 110 is formed on the surfaces of the semiconductor pillar 106 and the second doping layer 107 in an atomic layer manner, so that the uniformity and the thickness uniformity of the deposition rate are improved, and the gate material layer 110 has good formation quality; in addition, the process temperature of the ald process is usually lower, so that the Thermal Budget (Thermal Budget) is also reduced, and the probability of Wafer deformation (Wafer deformation) and device performance deviation is reduced. In other embodiments, the gate material layer may be formed by a Chemical Vapor Deposition (CVD) process.

In this embodiment, in the step of forming the gate material layer 110 by using an atomic layer deposition process, the reactant includes a precursor of the gate material layer 110. In the step of forming the gate material layer 110 on the surfaces of the semiconductor pillars 106 and the second doped layer 107 by using the precursor of the gate material layer 110, the precursor of the atomic layer deposited gate material layer 110 is rapidly cured into the gate material layer 110 in the chamber.

Specifically, the precursor of the gate material layer 110 includes a precursor of tungsten, and the corresponding gate material layer 110 includes tungsten.

In this embodiment, the method for forming the semiconductor structure further includes: after the fin 109 is formed, before the gate material layer 110 is formed, an isolation layer 111 is formed on the substrate 108 exposed by the fin 109 and the first doping layer 105, and a top surface of the isolation layer 111 is higher than a top surface of the fin 109 and lower than or flush with a top surface of the first doping layer 105.

The top surface of the isolation layer 111 is higher than the top surface of the fin 109 and is lower than or flush with the top surface of the first doped layer 105, that is, the isolation layer 111 covers a part of the sidewall of the first doped layer 105 or covers the entire sidewall of the first doped layer 105, so that adjacent devices can be better electrically isolated. In addition, the isolation layer 111 also completely exposes the semiconductor pillar 106, so that a subsequently formed gate material layer can completely cover the sidewall of the semiconductor pillar 106, and a correspondingly subsequently formed gate structure can completely cover the sidewall of the semiconductor pillar 106, which can have a high control force on a channel.

In other embodiments, the spacer may further cover a sidewall of the first doped layer, and in the step of forming the gate material layer, the gate material layer does not cover the sidewall of the first doped layer.

In this embodiment, the material of the isolation layer 111 includes silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 111; in addition, the silicon oxide has a small dielectric constant, and is beneficial to improving the subsequent function of isolating adjacent devices.

In the step of forming the gate material layer 110, the gate material layer 110 is formed on the stacked structure where the isolation layer 111 is exposed.

Specifically, the gate material layer 110 covers the semiconductor pillar 106, the second doped layer 107, the mask layer 104, a portion of the sidewall of the first doped layer 105, and the surface of the isolation layer 111.

The method for forming the semiconductor structure further includes: after the isolation layer 111 is formed and before the gate material layer 110 is formed, a gate dielectric material layer (not shown in the figure) is formed on the stacked structure and the isolation layer 111 exposed by the stacked structure; and removing the surface of the isolation layer 111 and the gate dielectric material layer right above the stacked structure, and taking the gate dielectric material layer on the side wall of the stacked structure as a gate dielectric layer 112.

And subsequently, performing one or more atomic layer etching treatments on the gate material layer 110 to form a gate structure surrounding the sidewall of the semiconductor pillar, wherein the gate dielectric layer 112 is used for electrically isolating the semiconductor pillar 106 from the gate structure.

In this embodiment, the material of the gate dielectric layer 112 includes HfO₂、ZrO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO and Al₂O₃One or more of them.

In this embodiment, the gate dielectric material layer is formed by an atomic layer deposition process, and in other embodiments, the gate dielectric material layer may also be formed by a metal-organic chemical vapor deposition (MOCVD).

Specifically, in the step of forming the gate dielectric material layer, the gate dielectric material layer is further formed on the top wall and the side wall of the mask layer 104; in the step of removing the surface of the isolation layer 111 and the gate dielectric material layer right above the stacked structure, the gate dielectric material layer on the top of the mask layer 104 is removed.

Referring to fig. 5 to 7, after the gate material layer 110 is formed, an interlayer dielectric layer 113 (as shown in fig. 7) is formed between the semiconductor pillars 106, and a top surface of the interlayer dielectric layer 113 is lower than a bottom surface of the second doped layer 107.

The interlayer dielectric layer 113 exposes the gate material layer 110 to be removed, and in the subsequent step of removing the gate material layer 110 exposing the interlayer dielectric layer 113, the gate material layer 110 covered by the interlayer dielectric layer 113 serves as a gate structure. In addition, the interlayer dielectric layer 113 is also used to electrically isolate adjacent devices.

In this embodiment, the material of the interlayer dielectric layer 113 includes silicon oxide. Silicon oxide is a dielectric material with common process, low cost and high process compatibility. In other embodiments, the interlayer dielectric layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.

Specifically, the forming step of the interlayer dielectric layer 113 includes:

as shown in fig. 5, an interlayer material film 114 is formed to cover the gate material layer 110, and the top surface of the interlayer material film 114 is higher than the top surface of the gate material layer 110.

In the present embodiment, the material of the interlayer material film 114 includes Hydrogen Silsesquioxane (HSQ), which is an inorganic spin-on glass (inorganic spin-on glass) material, and has the characteristic of achieving better flatness without etching back, therefore, the flatness of the top surface of the formed interlayer material film 114 is high, and the silsesquioxane hydride can be converted into silicon dioxide after Electron Beam Curing (Electron Beam Curing), so that the flatness of the subsequently formed interlayer material layer is improved, the interlayer material layer with partial thickness is correspondingly etched back, the flatness of the top surface of the formed interlayer medium layer is high, the dimension of the gate structures formed on the side walls of the laminated structures in the normal direction of the surface of the substrate 108 is identical, and the uniformity of the performance of the semiconductor structure is improved.

In the present embodiment, the interlayer material film 114 is formed by a spin coating (spin coating) process. The spin coating process has the advantages of mild process conditions, simplicity in operation and the like, and has remarkable convenient effects of reducing pollution, saving energy, improving cost performance and the like.

As shown in fig. 6, the interlayer material film 114 is subjected to a curing process to form an interlayer material layer 115.

The interlayer material layer 115 provides for the subsequent formation of an interlayer dielectric layer.

In this embodiment, the interlayer material film 114 is subjected to Curing treatment using Electron Beam Curing (EBC). In the process of electron beam curing treatment, high-energy electron beam flow is emitted to the silsesquioxane to initiate polymerization and crosslinking reaction of the silsesquioxane to form silicon oxide.

As shown in fig. 7, a portion of the thickness of the interlayer material layer 115 is etched back, and the remaining interlayer material layer 115 serves as an interlayer dielectric layer 113.

And etching back the interlayer material layer 115 with a part of thickness to form an interlayer dielectric layer 113, wherein the interlayer dielectric layer 113 exposes a part of the gate material layer 110, in the subsequent process, the gate material layer 110 exposing the interlayer dielectric layer 113 is removed, and the rest gate material layer 110 is used as a gate structure.

In this embodiment, the interlayer material layer 115 with a certain thickness is etched back by using a dry etching process to form the interlayer dielectric layer 113. The dry etching process is favorable for accurately controlling the removal thickness of the interlayer material layer 115 and controlling the height of the gate material layer 110 covered by the interlayer dielectric layer 113.

In this embodiment, the interlayer dielectric layer 113 is made of silicon oxide, and the etching gas used in the corresponding dry etching process is HF gas.

Referring to fig. 8 to 10, performing one or more atomic layer etching processes on the gate material layer 110 exposed from the interlayer dielectric layer 113 to form a gate structure 116, where the atomic layer etching processes include: and forming an organic layer 117 on the surface of the gate material layer 110 exposing the interlayer dielectric layer 115, and removing the organic layer 117.

Performing one or more atomic layer etching treatments on the gate material layer 110 exposing the interlayer dielectric layer 113 to form a gate structure 116, wherein the atomic layer etching treatments include: an organic layer 117 is formed on the surface of the gate material layer 110 exposing the interlayer dielectric layer 113, generally, in the gate material layer 110, the bond energy between atoms on the outermost surface and atoms on the inner layer is less than the bond energy between atoms on the inner layer, a radical (radial) is provided in the organic layer 117, and the radical has an element capable of reacting with the sidewall of the gate material layer 110, so that the bond energy between atoms on the outermost surface of the gate material layer 110 and atoms on the inner layer is further reduced, and in the process of removing the organic layer 117, the atoms on the outermost surface of the gate material layer 110 can be stripped, so that in the process of atomic layer etching treatment, the gate material layer 110 covered by the interlayer dielectric layer 113 is less damaged, after multiple atomic layer etching treatments, the gate material layer 110 exposing the interlayer dielectric layer 113 can be removed, and the gate structure 116 has better formation quality, thereby improving the electrical performance of the semiconductor structure.

Specifically, the atomic layer etching treatment comprises the following steps:

as shown in fig. 8, an organic layer 117 is formed on the surface of the gate material layer 110 where the interlayer dielectric layer 115 is exposed.

The organic layer 117 has radicals (radics) with elements capable of reacting with the gate material layer 110, and the organic layer 117 is capable of reacting with the atoms on the outermost surface of the gate material layer 110 exposing the interlayer dielectric layer 115, so that the bond energy of the atoms on the outermost surface of the gate material layer 110 and the atoms in the inner layer is further reduced, thereby facilitating the peeling of the atoms on the outermost surface of the gate material layer 110 during the subsequent removal of the organic layer 117.

In this embodiment, the material of the organic layer 117 includes a halogen element. Specifically, the material of the organic layer 117 includes one or more elements of chlorine, bromine, and fluorine.

In this embodiment, a Plasma Chemical Vapor Deposition (PCVD) process is used to form an organic layer 117 on the surface of the gate material layer 110 exposed from the interlayer dielectric layer 115. The plasma chemical vapor deposition process has good step coverage, can control the deposition thickness of the organic layer 117, and can make the film purity of the silicide blocking material layer 106 higher. In other embodiments, the organic layer may also be formed using an atomic layer deposition process.

In this embodiment, in the process of forming the organic layer 117 by using the plasma cvd process, the reaction gas is one or two of fluorocarbon gas and fluorocarbon gas, and HBr, Cl₂And HCl.

Specifically, the fluorocarbon gas includes: CF (compact flash)₄、C₄F₆、C₄F₈And C₅F₈One or more of; the hydrocarbon fluorine gas includes: CH (CH)₂F₂And CHF₃One or two of them.

It should be noted that the organic layer 117 on the surface of the gate material layer 110 is not too thick nor too thin. If the organic layer 117 on the surface of the gate material layer 110 is too thick, too much process time is required to form the organic layer 117, and accordingly, in the subsequent process of removing the organic layer 117, the process time is too long, which is not favorable for improving the formation efficiency of the gate structure. If the organic layer 117 on the surface of the gate material layer 110 is too thin, a weak region (week point) which does not cover the organic layer 117 is easy to exist on the surface of the gate material layer 110, atoms on the outermost surface of the gate material layer 110 are not easy to fully contact with the organic layer 117, accordingly, bond energy between atoms on the outermost surface of the gate material layer 110 in the weak region and inner layer atoms is not easy to be reduced, and after multiple atomic layer etching processes, the gate material layer 110 in the weak region is not removed, resulting in poor forming quality of a gate structure. In the present embodiment, the thickness of the organic layer 117 on the surface of the gate material layer 110 is 0.5 nm to 5 nm. Such as 1 nanometer, 2 nanometers, or 3 nanometers.

In the step of forming the organic layer 117 on the surface of the gate material layer 110 exposing the interlayer dielectric layer 115, the organic layer 117 is also formed on the top surface of the interlayer dielectric layer 113.

As shown in fig. 9, the organic layer 117 is removed.

In this embodiment, the organic layer 117 is removed by an anisotropic physical etching process. The physical etching process can provide high-speed ions, and the ions can physically remove the organic layer 117 at high speed and take away atoms on the outermost surface of the gate material layer 110 exposing the interlayer dielectric layer 113, so that the purpose of removing the gate material layer 110 exposing the interlayer dielectric layer 113 and forming a gate structure is achieved.

In this embodiment, a Plasma Ribbon Beam etching process (Plasma Ribbon Beam) is used to perform the anisotropic etching process. Etching ions in the plasma belt etching process have no selectivity to the etched material and have good etching directionality.

In the process of removing the organic layer 117 using an anisotropic physical etching process, etching ions include one or more of He, Ar, Ne, Kr, and Xe. He. Ar, Ne, Kr and Xe are inert ions, and in the process of etching the organic material layer 117, the etching ions are not easy to react with the material of the interlayer dielectric layer 113 and the material of the gate material layer 110, so that an impurity polymer is not easy to exist in the chamber, and the organic material layer 117 on the surface of the gate material layer 110 is not interfered.

It should be noted that, in the process of removing the organic layer 117 by using the anisotropic physical etching process, the bias voltage should not be too large, and should not be too small. If the bias voltage is too large, the etching rate of the organic material layer 117 is too fast, the process controllability and the reaction rate uniformity in the etching process are small, the interlayer dielectric layer 113 is easily damaged after multiple atomic layer etching processes, the corresponding gate material layer 110 covered by the interlayer dielectric layer 113 is easily etched by mistake, and when the semiconductor structure works, the control capability of the gate structure 116 on a channel is not strong, so that the electrical performance of the semiconductor structure is poor. If the bias voltage is too low, the etching rate of the organic layer 117 is too slow, and the formation efficiency of the gate structure 116 is not easily improved. In this embodiment, in the process of removing the organic layer 117 by using an anisotropic physical etching process, the bias voltage is 50V to 1000V. Such as 100V, 200V, or 500V.

It should be noted that, during the process of removing the organic layer 117 by using the anisotropic physical etching process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the etching speed of the ions is low, and the organic layer 117 is not anisotropic, and the atoms on the outermost surface of the gate material layer 110 are not removed easily, so that the organic layer 117 exposed out of the interlayer dielectric layer 113 is not removed easily. If the chamber pressure is too low, the etching rate of the organic material layer 117 is too fast, the process controllability and the reaction rate uniformity in the etching process are small, after multiple atomic layer etching processes, the interlayer dielectric layer 113 is easily damaged, the corresponding gate material layer 110 covered by the interlayer dielectric layer 113 is easily etched by mistake, and when the semiconductor structure works, the control capability of the gate structure 116 on a channel is not strong, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the chamber pressure is 5mTorr to 1000mTorr, such as 100mTorr, 200mTorr, or 300mTorr, during the anisotropic physical etching process to remove the organic layer 117.

It should be noted that, in the process of removing the organic material layer 117 by using the anisotropic physical etching process, an included angle between the incident direction of the etching ions and the normal line of the substrate surface should not be too large or too small, and specifically, an included angle between the incident direction of the etching ions and the normal line of the substrate 100 should not be too large or too small. If the included angle is too small, correspondingly, in the process of etching the organic material layer 117, the removal rate of the gate material layer 110 on the top of the stacked structure is too much greater than the etching rate of the gate material layer 110 on the sidewall of the stacked structure, after the gate material layer 110 on the top of the stacked structure is removed, the second doping layer 107 is easily damaged by mistake, and when the semiconductor structure works, the second doping layer 107 is not easy to provide sufficient stress for the semiconductor column 106, so that the migration rate of carriers in a channel is not high. In the process of removing the organic material layer 117 by using the anisotropic physical etching process, if an included angle between an incident direction of etching ions and a normal line of the surface of the substrate 100 is too large, a shadowing effect (shadow effect) is likely to occur, and a portion, close to the interlayer dielectric layer 113, of the gate material layer 110 on the side wall of the stacked structure cannot be smoothly removed, the gate structure 116 exposing the interlayer dielectric layer 113 needs to be removed by adding an additional step, which is not favorable for improving the formation rate of the gate structure 116. In this embodiment, in the process of removing the organic layer 117 by using an anisotropic physical etching process, an included angle between the incident direction of the etching ions and the normal of the surface of the substrate 100 is greater than 10 ° and less than 45 °, for example, 20 °, 30 °, or 40 °.

It should be noted that, during the process of removing the organic layer 117, the mask layer 104 is used to protect the top of the second doped layer 107, so that the second doped layer 107 has good formation quality, and when the semiconductor structure operates, the second doped layer 107 can provide sufficient stress to the channel, thereby increasing the mobility rate of carriers in the channel.

As shown in fig. 10, after performing one or more atomic layer etching processes on the gate material layer 110 exposed from the interlayer dielectric layer 113, a gate structure 116 is formed.

In this embodiment, the mask layer 104 is removed in the step of removing the gate material layer 110 exposing the interlayer dielectric layer 113, and the removal of the mask layer 104 is prepared for the subsequent formation of a contact plug connected to the second doping layer 107. In other embodiments, after the gate material layer exposing the interlayer dielectric layer is removed, a mask layer with a partial thickness may remain, and needs to be removed by an additional process.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 8, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 108; a stacked structure, discrete on the substrate 108; the laminated structure includes: a first doped layer 105, a semiconductor pillar 106 located on the first doped layer 105, and a second doped layer 107 located on the semiconductor pillar 106; a gate material layer 110 conformally covering the semiconductor pillar 106 and the second doped layer 107; an interlayer dielectric layer 113 covering a part of the sidewall of the gate material layer 110, wherein the top surface of the interlayer dielectric layer 113 is lower than the bottom surface of the second doped layer 107; and the organic layer 117 is positioned on the surface of the gate material layer 110 exposing the interlayer dielectric layer 113.

In the semiconductor structure provided by the embodiment of the present invention, the organic layer 117 is located on the surface of the gate material layer 110 exposed out of the interlayer dielectric layer 113, generally, in the gate material layer 110, the bond energy of atoms on the outermost surface and atoms in the inner layer is smaller than the bond energy between atoms in the inner layer, and the organic layer 117 has a radical (radial) with an element capable of reacting with the gate material layer 110, so that the bond energy of atoms on the outermost surface and atoms in the inner layer of the gate material layer 110 is further reduced, and in the subsequent process of removing the organic layer 117, the atoms on the outermost surface of the gate material layer 110 can be peeled off, and the gate material layer 110 covered by the interlayer dielectric layer 113 is less damaged, so that the gate structure has better formation quality, and further, the electrical performance of the semiconductor structure can be improved.

In this embodiment, the substrate 108 is made of silicon. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be silicon on insulator or germanium on insulator.

The semiconductor structure further includes: a fin 109 located between the substrate 108 and the first doped layer 105.

In this embodiment, the material of the fin 109 is the same as the material of the substrate 108.

The semiconductor structure further includes: and the isolation layer 111 is positioned on the substrate 108 between the fin 109 and the first doping layer 105, and the top surface of the isolation layer 111 is higher than the top surface of the fin 109 and lower than or flush with the top surface of the first doping layer 105.

The top surface of the isolation layer 111 is higher than the top surface of the fin 109 and is lower than or flush with the top surface of the first doped layer 105, that is, the isolation layer 111 covers a part of the sidewall of the first doped layer 105 or covers the entire sidewall of the first doped layer 105, so that adjacent devices can be better electrically isolated. In addition, the isolation layer 111 completely exposes the semiconductor pillar 106, the gate material layer 110 can completely cover the sidewall of the semiconductor pillar 106, and a corresponding gate structure formed by subsequently removing the gate material layer 110 higher than the interlayer dielectric layer 113 can completely cover the sidewall of the semiconductor pillar 106, so that a higher control force can be exerted on a channel.

In this embodiment, the material of the isolation layer 111 includes silicon oxide. The silicon oxide is a dielectric material which is common in process and low in cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 111; in addition, the silicon oxide has a small dielectric constant, and is beneficial to improving the subsequent function of isolating adjacent devices.

The semiconductor pillar 106 serves as a channel region when the semiconductor structure is in operation.

In this embodiment, the material of the semiconductor pillar 106 is silicon. In other embodiments, the material of the semiconductor pillar may also be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.

The first doping layer 105 and the second doping layer 107 serve as source drain doping layers of the semiconductor pillars 106.

In this embodiment, the semiconductor structure is used to form a PMOS (positive Channel Metal Oxide semiconductor) transistor, when the PMOS transistor works, a carrier in a Channel is a hole, and when a lattice structure of the Channel is subjected to a compressive stress, a migration speed of the hole becomes fast, so that an electrical property of the PMOS transistor can be improved, that is, the material of the first doping layer 105 is silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In. In other embodiments, the semiconductor structure is used to form an NMOS (negative channel Metal Oxide semiconductor) transistor, when the NMOS transistor operates, a carrier in a channel is an electron, and when a lattice structure of the channel is subjected to a compressive stress, a migration speed of the electron becomes fast, so that an electrical property of the NMOS transistor can be improved, and the material of the first doping layer is correspondingly silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, As or Sb.

In this embodiment, the semiconductor structure is used to form a PMOS transistor, that is, the material of the second doping layer 107 is silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In. In other embodiments, the semiconductor structure is used to form an NMOS transistor, and the material of the second doped layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. Specifically, the N-type ions include P, As or Sb.

In addition, the semiconductor structure further includes: and a mask layer 104 on the second doped layer 107. The mask layer 104 is an etching mask for forming a stacked structure by etching.

Specifically, the material of the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the mask layer 104 is made of silicon nitride.

The gate material layer 110 provides for the subsequent formation of a gate structure.

Specifically, the gate material layer 110 is located on the isolation layer 111, and on the top surface and the sidewall of the stacked structure higher than the isolation layer 111. In this embodiment, the semiconductor pillar 106, the second doped layer 107 and a part of the first doped layer 105 are higher than the isolation layer 111, and the corresponding gate material layer 110 is located on the semiconductor pillar 106, the second doped layer 107 and the first doped layer 105 with a part of the height.

In this embodiment, the gate material layer 110 is made of tungsten. In other embodiments, the material of the gate material layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

It should be noted that the gate material layer 110 is located on the isolation layer 111, and on the top surface and the sidewall of the stacked structure higher than the isolation layer 111.

Specifically, the gate material layer 110 is formed on the sidewalls of the stacked structure, the top wall and the sidewalls of the mask layer 104, and the surface of the isolation layer 111.

The semiconductor structure further includes: and a gate dielectric layer 112 located between the gate material layer 110 and the stacked structure.

Gate dielectric layer 112 is used to electrically isolate semiconductor pillar 106 from subsequently formed gate structures.

In this embodiment, the material of the gate dielectric layer 112 includes HfO₂、ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al₂O₃One or more of them.

Specifically, the gate dielectric layer 112 is located on the sidewall of the bottom of the mask layer 104, the sidewall of the second doped layer 107, the sidewall of the semiconductor pillar 106, and the sidewall of the first doped layer 105 higher than the isolation layer 111.

The interlayer dielectric layer 113 exposes the gate material layer 110 to be removed, so that preparation is made for forming a gate structure subsequently, and the probability that the gate material layer 110 covered by the interlayer dielectric layer 113 is damaged is reduced. In addition, the interlayer dielectric layer 113 is also used for electrically isolating devices formed later.

In this embodiment, the material of the interlayer dielectric layer 113 includes silicon oxide. Silicon oxide is a dielectric material with common process, low cost and high process compatibility. In other embodiments, the interlayer dielectric layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.

The organic layer 117 has radicals (radics) with elements capable of reacting with the gate material layer 110, and the organic layer 117 is capable of reacting with the atoms on the outermost surface of the gate material layer 110 exposing the interlayer dielectric layer 115, so that the bond energy of the atoms on the outermost surface of the gate material layer 110 and the atoms in the inner layer is further reduced, thereby facilitating the peeling of the atoms on the outermost surface of the gate material layer 110 during the subsequent removal of the organic layer 117.

In this embodiment, the material of the organic layer 117 includes a halogen element. Specifically, the material of the organic layer 117 includes one or more elements of chlorine, bromine, and fluorine.

It should be noted that the organic layer 117 on the surface of the gate material layer 110 is not too thick nor too thin. If the organic layer 117 on the surface of the gate material layer 110 is too thick, the process time spent in the subsequent process of removing the organic layer 117 is too long, which is not favorable for improving the formation efficiency of the gate structure. If the organic layer 117 on the surface of the gate material layer 110 is too thin, a weak region (week point) that does not cover the organic layer 117 is prone to exist on the surface of the gate material layer 110, atoms on the outermost surface of the gate material layer 110 are not prone to fully contact with the organic layer 117, accordingly, bond energy between the atoms on the outermost surface of the gate material layer 110 and inner layer atoms in the weak region is not prone to be reduced, and during the subsequent process of removing the organic layer 117, the atoms on the outermost surface of the gate material layer 110 are not prone to be removed. In the present embodiment, the thickness of the organic layer 117 on the surface of the gate material layer 110 is 0.5 nm to 5 nm.

The organic layer 117 is also located on the top surface of the interlayer dielectric layer 113.

The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.