阅读说明：本技术 自动数据传输方法、装置及存储介质 (Automatic data transmission method, device and storage medium ) 是由 宋大成 于 2020-06-01 设计创作，主要内容包括：一种自动数据传输方法、装置及存储介质,所述方法包括具有多个存储模块的存储器接收由处理器传送的数据并获取数据的标识信息；数据对应存储器的一个存储模块；存储器根据标识信息查询起始地址；将数据对应的存储模块设定为目标存储模块,并根据数据对应的预定操作设定目标控制模块；目标控制模块的指针从起始地址开始将数据对应的多段数据段进行传送；在接收到中断指令且当前指针对应的地址为末位地址时,关闭存储器的输出功能,存储器自动获取起始地址并检测中断指令可提高数据传输的响应速度。(An automatic data transmission method, device and storage medium, the said method includes the memorizer with multiple memory modules receives the data transmitted by the processor and obtains the identification information of the data; a storage module of the data corresponding memory; the memory inquires the initial address according to the identification information; setting a storage module corresponding to the data as a target storage module, and setting a target control module according to a preset operation corresponding to the data; the pointer of the target control module transmits a plurality of data segments corresponding to the data from the starting address; when the interrupt instruction is received and the address corresponding to the current pointer is the last address, the output function of the memory is closed, the memory automatically acquires the initial address and detects the interrupt instruction, and the response speed of data transmission can be improved.)

1. An automatic data transmission method is applied to a memory which is communicated with a processor; the memory comprises a first memory module and a second memory module; the automatic data transmission method is characterized by comprising the following steps:

when a receiving instruction is detected, the memory receives the data transmitted by the processor and acquires the identification information of the data; wherein the data takes one of the first storage module and the second storage module as a preset storage module; the identification information is used for identifying whether the data has a specified starting address in the target memory;

when a query instruction is detected, the memory queries an initial address corresponding to the data according to the identification information;

when a setting instruction is detected, setting a preset storage module corresponding to the data as a target storage module, and setting a target control module according to a preset operation corresponding to the data;

when a transmission instruction is detected, controlling a pointer of the target control module to transmit a plurality of data segments corresponding to the data from the starting address;

when a detection instruction is detected, judging whether an interrupt instruction is received or not;

when an interrupt instruction is received, judging whether the address corresponding to the current pointer is a last address or not;

and when the address corresponding to the current pointer is the last address, closing the output function of the memory.

2. The automatic data transmission method according to claim 1, wherein the identification information includes a default identification ID and a specified identification ID; the step of querying the start address and the target memory corresponding to the data according to the identification information comprises:

judging whether the identification information is the default identification ID or not;

when the identification information is not the default identification ID, acquiring a designated address corresponding to the designated identification ID as an initial address;

and when the identification information is the default identification ID, acquiring a default address corresponding to the default identification ID as a starting address.

3. The automatic data transmission method of claim 2, wherein the default identification ID corresponds to a default address of 468 and the specified identification ID corresponds to a specified address of 476.

4. The method according to claim 1, wherein the step of setting the preset storage module corresponding to the data as a target storage module and setting the target control module according to the predetermined operation corresponding to the data comprises:

setting the preset storage module corresponding to the data as a target storage module;

judging whether the preset operation information is a reading operation or not;

when the preset operation information is read operation, setting a read control module in the memory as a target control module;

and when the preset operation information is write operation, setting a write control module in the memory as a target control module.

5. The automatic data transmission method according to claim 1, wherein the automatic data transmission method further comprises:

and after the interrupt instruction is not received and the target control module finishes the transmission from the starting address to the ending address, the target control module returns to the first address of the target storage module to continue the transmission of the corresponding multiple data segments.

6. An automatic data transmission apparatus, characterized in that the automatic data transmission apparatus comprises:

a processor;

a memory receiving data output by the processor; the memory includes:

the receiving module is used for receiving the data transmitted by the processor and acquiring the identification information of the data when a receiving instruction is detected; the data takes one of the first storage module and the second storage module as a preset storage module; the identification information is used for identifying whether the data has a specified starting address in the target memory;

the identification detection module is used for inquiring the initial address corresponding to the data by the memory according to the identification information when the inquiry instruction is detected;

the receiving module is further used for setting the preset storage module corresponding to the data as a target storage module when a setting instruction is detected, and setting a target control module according to a preset operation corresponding to the data;

the receiving module further controls a pointer of the target control module to transmit a plurality of data segments corresponding to the data from the starting address when a transmission instruction is detected;

the receiving module further judges whether an interrupt instruction is received or not when the detection instruction is detected;

the last address detection module is used for judging whether the address corresponding to the current pointer is the last address or not when an interrupt instruction is received; and when the address corresponding to the current pointer is the last address, the last address detection module closes the output function of the memory.

7. The automatic data transmission apparatus according to claim 6, wherein the identification information includes a default identification ID and a specified identification ID; the identification detection module further judges whether the identification information is the default identification ID; when the identification information is not the default identification ID, the identification detection module further acquires a designated address corresponding to the designated identification ID as a starting address; when the identification information is the default identification ID, the identification detection module further acquires a default address corresponding to the default identification ID as a start address.

8. The automated data transmission apparatus of claim 7, wherein the default identification ID corresponds to a default address of 468 and the specified identification ID corresponds to a specified address of 476.

9. The automatic data transmission device according to claim 6, wherein the receiving module further sets the preset storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is a read operation; when the preset operation information is read operation, the receiving module further sets a read control module as a target control module; when the predetermined operation information is a write operation, the receiving module further sets a write control module as a target control module.

10. A storage medium, characterized in that the storage medium is a computer-readable storage medium, storing at least one instruction which, when executed by a processor, implements the automatic data transmission method according to any one of claims 1 to 5.

Technical Field

The invention relates to a method and a device for automatic data transmission and a storage medium.

Background

With the development of communication technology, the amount of data generated in terminal equipment becomes increasingly large. The terminal device generally includes a Central Processing Unit (CPU), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and other functional modules. Data generated in the terminal device usually needs to be temporarily stored in the memory and then sent to the corresponding functional module after some processing, so that the corresponding functional module receives the required data. In the prior art, a CPU needs to read target data from a DRAM and analyze the data to determine a transmission sequence, the process is time-consuming, time for the CPU to process other instructions is occupied, and quick response of the data in the transmission process cannot be realized.

Disclosure of Invention

The invention mainly aims to provide an automatic data transmission method, an automatic data transmission device and a storage medium, and aims to solve the problem that quick response in the transmission process cannot be realized in the prior art.

An automatic data transmission method is applied to a memory which is communicated with a processor; the memory comprises a first memory module and a second memory module; the automatic data transmission method comprises the following steps:

when a receiving instruction is detected, the memory receives data transmitted by the processor and acquires identification information of the data; wherein the data takes one of the first storage module and the second storage module as a preset storage module; the identification information is used for identifying whether the data has a specified starting address in the target memory;

when a query instruction is detected, the memory queries an initial address corresponding to the data according to the identification information;

when a setting instruction is detected, setting a preset storage module corresponding to the data as a target storage module, and setting a target control module according to a preset operation corresponding to the data;

when a transmission instruction is detected, controlling a pointer of the target control module to transmit a plurality of data segments corresponding to the data from the starting address;

when a detection instruction is detected, judging whether an interrupt instruction is received or not;

when an interrupt instruction is received, judging whether the address corresponding to the current pointer is a last address or not;

and when the address corresponding to the current pointer is the last address, closing the output function of the memory.

Preferably, the identification information includes a default identification ID and a specified identification ID; the step of querying the start address and the target memory corresponding to the data according to the identification information comprises:

judging whether the identification information is the default identification ID or not;

when the identification information is not the default identification ID, acquiring a designated address corresponding to the designated identification ID as an initial address;

and when the identification information is the default identification ID, acquiring a default address corresponding to the default identification ID as a starting address.

Preferably, the default address corresponding to the default ID is 468, and the designated address corresponding to the designated ID is 476.

Preferably, the step of setting the preset storage module corresponding to the data as a target storage module and setting the target control module according to the predetermined operation corresponding to the data includes:

setting the preset storage module corresponding to the data as a target storage module;

judging whether the preset operation information is a reading operation or not;

when the preset operation information is read operation, setting a read control module in the memory as a target control module;

and when the preset operation information is write operation, setting a write control module in the memory as a target control module.

Preferably, after an interrupt instruction is not received and the target control module completes the transmission from the starting point to the last address, the target control module returns to the starting address of the target storage module to continue the transmission of the corresponding multiple data segments.

In addition, in order to achieve the above object, the present invention also provides an automatic data transmission apparatus, including:

a processor;

the memory receives the data output by the processor and comprises a first memory module and a second memory module; the memory includes:

the receiving module is used for receiving the data transmitted by the processor and acquiring the identification information of the data when a receiving instruction is detected; wherein the data takes one of the first storage module and the second storage module as a preset storage module; the identification information is used for identifying whether the data has a specified starting address in the target memory;

the identification detection module is used for inquiring the initial address corresponding to the data by the memory according to the identification information when the inquiry instruction is detected;

the receiving module is further used for setting the preset storage module corresponding to the data as a target storage module when a setting instruction is detected, and setting a target control module according to a preset operation corresponding to the data;

the receiving module further controls a pointer of the target control module to transmit a plurality of data segments corresponding to the data from the starting address when a transmission instruction is detected;

the receiving module further judges whether an interrupt instruction is received or not when the detection instruction is detected;

the last address detection module is used for judging whether the address corresponding to the current pointer is the last address or not when an interrupt instruction is received; and when the address corresponding to the current pointer is the last address, the last address detection module closes the output function of the memory.

Preferably, the identifier detecting module further determines whether the identifier information is the default identifier ID; when the identification information is not the default identification ID, the identification detection module further acquires a designated address corresponding to the designated identification ID as a starting address; when the identification information is the default identification ID, the identification detection module further acquires a default address corresponding to the default identification ID as a start address.

Preferably, the default address corresponding to the default ID is 468, and the designated address corresponding to the designated ID is 476.

Preferably, the receiving module further sets the preset storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is a read operation; when the preset operation information is read operation, the receiving module further sets a read control module as a target control module; when the predetermined operation information is a write operation, the receiving module further sets a write control module as a target control module.

In addition, in order to achieve the above object, the present invention further provides a storage medium, which is a computer-readable storage medium and stores at least one instruction, and when the at least one instruction is executed by a processor, the at least one instruction implements the following steps:

when a receiving instruction is detected, the memory receives data transmitted by the processor and acquires identification information of the data; the data takes one of the first storage module and the second storage module as a preset storage module; the identification information is used for identifying whether the data has a specified starting address in the target memory;

when a query instruction is detected, the memory queries an initial address corresponding to the data according to the identification information;

when a setting instruction is detected, setting a preset storage module corresponding to the data as a target storage module, and setting a target control module according to a preset operation corresponding to the data;

when a transmission instruction is detected, controlling a pointer of the target control module to transmit a plurality of data segments corresponding to the data from the starting point;

when a detection instruction is detected, judging whether an interrupt instruction is received or not;

when an interrupt instruction is received, judging whether the address corresponding to the current pointer is a last address or not;

and when the address corresponding to the current pointer is the last address, closing the output function of the memory.

According to the automatic data transmission method, the device and the storage medium, the memory can automatically determine the data starting address and transmit the data according to the input data or the input instruction, so that the occupation of the data transmission on the processor is reduced, and the response speed of the memory in the data transmission process is further improved; and further detecting the last address when detecting the interrupt instruction so as to ensure the integrity of data in the data transmission process.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of an automatic data transmission method according to the present invention.

Fig. 2 is a detailed flowchart of step S11 in fig. 1.

Fig. 3 is a detailed flowchart of step S12 in fig. 1.

Fig. 4 is a functional block diagram of the data transmission device of the present invention.

Description of the main elements

Data transmission device 100

Processor 10

Memory 20

Communication bus 30

Receiving module 201

Identity detection module 202

Write control Module 203

Read control module 204

First storage module 205

Second memory module 206

First cache module 208

Second cache module 209

Last address detection module 207

Output control module 210

Output module 211

Steps S10-S16

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first", "second", and "third", etc. in the description of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to the listed steps or modules but may alternatively include other steps or modules not listed or inherent to such process, method, article, or apparatus.

The following describes a specific embodiment of the automatic data transmission method according to the present invention with reference to the drawings.

In at least one embodiment of the invention, the automatic data transmission method is applied to a data transmission system. The data transmission system comprises a processor 10 (see fig. 4) and at least one memory 20 (see fig. 4). The data transmission system provides a visual interface. The visual interface is used for providing a man-machine interaction interface for a user, and the user can be connected to the data transmission system through electronic equipment such as a mobile phone or a computer. The automatic data transmission method is used for the memory 20 to automatically transmit and detect the interrupt according to the data of the processor 10.

The processor 10 may comprise one or more microprocessors, digital processors. The processor 10 may call the program code stored in the memory 20 to perform the associated function. For example, the various modules illustrated in fig. 4 are program code stored in the memory 20 and executed by the processor 10 to implement an automatic data transfer method. The processor 10 is also called a Central Processing Unit (CPU), and is an ultra-large scale integrated circuit, which is an operation Core (Core) and a Control Core (Control Unit).

The memory 20 is used for storing data as well as program code. The memory 20 may be a circuit without a physical form having a storage function in an integrated circuit, or the memory 20 may also be a physical form of memory, such as a memory bank, a TF Card (Trans-flash Card), a smart media Card (smart media Card), a secure digital Card (secure digital Card), a flash memory Card (flash Card), or other storage devices. The memory 20 may be in data communication with the processor 10 via a communication bus 30. The memory 20 may include therein an operating system, a network communication module, and a data transmission program. The operating system is a program that manages and controls the hardware and software resources of the data transfer device 100, supporting the operation of the data transfer program as well as other software and/or programs. The network communication module is used for realizing communication among the components in the memory 20 and with other hardware and software in the electronic device 100.

Please refer to fig. 1, which is a flowchart illustrating an automatic data transmission method.

S10, when the receiving instruction is detected, the memory receives the data transmitted by the processor and acquires the identification information of the data.

In at least one embodiment of the present invention, the data includes a plurality of pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. The preset storage module information and the operation instruction information can be designated by symbols designated by user-defined settings. In at least one embodiment of the present invention, the attribute information is a combination of numbers and symbols. For example, the attribute information may be 0 × 2, where "0" denotes that the first storage module 205 is a predetermined storage module, and "2" denotes that the read operation is a predetermined operation instruction. The identification information is used for identifying whether the data has a specified starting address in the target storage module. The identification information is a positive integer. The identification information includes a default identification ID and a specified identification ID. The default identification ID is used for indicating that the data corresponds to a default starting address; the specified identification ID is used for indicating that the data corresponds to a specified starting address. In at least one embodiment of the present invention, the default ID is 0, and the specific ID may be 1, 2, or 3. A list of correspondence relationships between default identification IDs, designated identification IDs, default starting addresses, and designated starting addresses may be stored in the first storage module 205 and the second storage module 206.

And S11, when a query instruction is detected, the memory queries the initial address corresponding to the data according to the identification information.

Referring to fig. 2, in at least one embodiment of the present invention, the step of querying, by the memory according to the identification information, a start address corresponding to the data includes:

s110, judging whether the identification information is the default identification ID;

s111, when the identification information is not the default identification ID, acquiring a designated address corresponding to the designated identification ID as an initial address;

and S112, when the identification information is the default identification ID, acquiring a default address corresponding to the default identification ID as a starting address.

In at least one embodiment of the invention, the default address corresponding to the default ID is 468, and the specific address corresponding to the specific ID is 476.

And S12, when a setting instruction is detected, setting the preset storage module corresponding to the data as a target storage module, and setting a target control module according to the preset operation corresponding to the data.

Referring to fig. 3, in at least one embodiment of the present invention, the step of setting the preset storage module corresponding to the data as a target storage module and setting a target control module according to a predetermined operation corresponding to the data includes:

s121, setting the preset storage module corresponding to the data as a target storage module;

s122, judging whether the preset operation information is a reading operation;

s123, when the preset operation information is read operation, setting a read control module in the memory as a target control module;

and S124, setting the write control module in the memory as a target control module when the preset operation information is write operation.

And S13, when a transmission instruction is detected, controlling the pointer of the target control module to transmit the plurality of data segments corresponding to the data from the starting address.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module corresponding to the first storage module 205 and a second cache module corresponding to the second storage module 206. When the operation information is a read operation, the transfer operation is that the read control module starts to transfer the data corresponding to the target storage module to the first cache module from the starting point. When the operation information is a write operation, the transfer operation is that the write control module stores the data from the processor 10 starting from the start address within the target storage module.

S14, when detecting the detection command, determining whether an interrupt command is received.

And S15, when the interrupt instruction is received, judging whether the address corresponding to the current pointer is the last address.

And S16, when the address corresponding to the pointer is the last address, closing the output function of the memory 20.

When the interrupt instruction is not received, the process returns to step S13.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transfer from the start address to the end address, the target control module returns to the start address of the target storage module to continue the transfer of the corresponding multiple data segments.

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 (see fig. 4) of the memory 20 to be turned off.

When the address corresponding to the pointer is not the last address, the process returns to step S14.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transfer from the starting point to the last address, the target control module returns to the first address of the target storage module to continue the transfer of the corresponding multiple data segments.

In at least one embodiment of the present invention, all of the above instructions may be data request instructions received by the electronic device. The electronic device may include a keyboard, a touch screen, and the like, but the user input manner in the example embodiment of the present disclosure is not limited thereto, and may be generated by a specific operation on the visual interface for the user. Specifically, the user's operations include, but are not limited to: sliding operation, clicking operation (such as single clicking operation, double clicking operation, etc.). Specifically, the preset key may be an entity key on the electronic device, or may be a virtual key on the electronic device (for example, the virtual key may be a virtual icon on a display of the electronic device, etc.), and the present invention is not limited herein.

In the automatic data transmission method, the memory 20 can automatically determine the initial address of the data and transmit the data according to the input data or instructions, so that the occupation of the data transmission on the processor 10 is reduced, and the response speed of the memory 20 in the data transmission process is further improved; and further detecting the last address when detecting the interrupt instruction so as to ensure the integrity of data in the data transmission process.

Referring to fig. 4, the present invention provides an automatic data transmission apparatus 100 including a processor 10, a memory 20 and a communication bus 30.

The processor 10 may comprise one or more microprocessors, digital processors. The processor 10 may call the program code stored in the memory 20 to perform the associated function. For example, the various modules illustrated in fig. 4 are program code stored in the memory 20 and executed by the processor 10 to implement an automatic data transfer method. The processor 10 is also called a Central Processing Unit (CPU), and is an ultra-large scale integrated circuit, which is an operation Core (Core) and a Control Core (Control Unit).

The memory 20 is used for storing data as well as program code. The memory 20 may be a circuit without a physical form having a storage function in an integrated circuit, or the memory 20 may also be a physical form of memory, such as a memory bank, a TF Card (Trans-flash Card), a smart media Card (smart media Card), a secure digital Card (secure digital Card), a flash memory Card (flash Card), or other storage devices. The memory 20 may be in data communication with the processor 10 via a communication bus 30. The memory 20 may include therein an operating system, a network communication module, and a data transmission program. The operating system is a program that manages and controls the hardware and software resources of the data transfer device 100, supporting the operation of the data transfer program as well as other software and/or programs. The network communication module is used for realizing communication among the components in the memory 20 and with other hardware and software in the data transmission device 100. In at least one embodiment of the present invention, the memory 20 includes a first storage module 205 and a second storage module 206.

In one embodiment of the present invention, the memory 20 includes:

the receiving module 201 is configured to receive data transmitted by the processor 10 and obtain identification information of the data when a receiving instruction is detected.

In at least one embodiment of the present invention, the data includes a plurality of pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. The preset storage module information and the operation instruction information can be designated by symbols designated by user-defined settings. In at least one embodiment of the present invention, the attribute information is a combination of numbers and symbols. For example, the attribute information may be 0 × 2, where "0" denotes that the first storage module 205 is a predetermined storage module, and "2" denotes that the read operation is a predetermined operation instruction. The identification information is used for identifying whether the data has a specified starting address in the target storage module. The identification information is a positive integer. The identification information includes a default identification ID and a specified identification ID. The default identification ID is used for indicating that the data corresponds to a default starting address; the specified identification ID is used for indicating that the data corresponds to a specified starting address. In at least one embodiment of the present invention, the default ID is 0, and the specific ID may be 1, 2, or 3. A list of correspondence relationships between default identification IDs, designated identification IDs, default starting addresses, and designated starting addresses may be stored in the first storage module 205 and the second storage module 206.

And the identifier detection module 202 is configured to, when a query instruction is detected, query, by the memory, an initial address corresponding to the data according to the identifier information.

Referring to fig. 2, in at least one embodiment of the present invention, the identifier detecting module 202 further determines whether the identifier information is the default identifier ID. When the identification information is not the default identification ID, the identification detection module 202 further acquires a designated address corresponding to the designated identification ID as a start address. When the identification information is the default identification ID, the identification detection module 202 further acquires a default address corresponding to the default identification ID as a start address.

In at least one embodiment of the invention, the default address corresponding to the default ID is 468, and the specific address corresponding to the specific ID is 476.

The receiving module 201 is further configured to set the preset storage module corresponding to the data as a target storage module when a setting instruction is detected, and set a target control module according to a predetermined operation corresponding to the data. The receiving module 201 further sets the preset storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is a read operation. When the predetermined operation information is a read operation, the receiving module 201 further sets the read control module 204 as a target control module. When the predetermined operation information is a write operation, the receiving module 201 further sets the write control module 203 as a target control module.

The receiving module 201 further controls the pointer of the target control module to transmit the plurality of data segments corresponding to the data from the start address when detecting the transmission instruction.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module 208 corresponding to the first storage module 205 and a second cache module 209 corresponding to the second storage module 206. When the predetermined operation information is a read operation, the transfer operation is that the read control module 204 starts to transfer the data corresponding to the start address to the first cache module 208 from the start point. When the predetermined operation information is a write operation, the transfer operation is that the write control module 203 stores the data from the processor 10 from the start address. The first buffer module 208 and the second buffer module 209 may be provided to the output module 211 through the output control module 210 for output.

The receiving module 201 further determines whether an interrupt command is received when detecting the detection command.

And the last address detection module 207 is configured to determine whether an address corresponding to the current pointer is a last address when the interrupt instruction is received. When the address corresponding to the current pointer is the last address, the last address detecting module 207 turns off the output function of the memory 20.

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 of the memory 20 to be turned off.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transfer from the starting point to the last address, the target control module returns to the first address of the target storage module to continue the transfer of the corresponding multiple data segments.

In the automatic data transmission device, the memory 20 can automatically determine the initial address of the data and transmit the data according to the input data or instructions, so that the occupation of the data transmission on the processor 10 is reduced, and the response speed of the memory 20 in the data transmission process is further improved; and further detecting the last address when detecting the interrupt instruction so as to ensure the integrity of data in the data transmission process.

The invention also provides a storage medium. The storage medium is a computer-readable storage medium. The computer readable storage medium has stored thereon computer instructions. The computer instructions may be stored on the memory 20 and when executed by the one or more processors 10 thereby to carry out the steps of:

s10, when the receiving instruction is detected, the memory receives the data transmitted by the processor and acquires the identification information of the data.

In at least one embodiment of the present invention, the data includes a plurality of pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. The preset storage module information and the operation instruction information can be designated by symbols designated by user-defined settings. In at least one embodiment of the present invention, the attribute information is a combination of numbers and symbols. For example, the attribute information may be 0 × 2, where "0" denotes that the first storage module 205 is a predetermined storage module, and "2" denotes that the read operation is a predetermined operation instruction. The identification information is used for identifying whether the data has a specified starting address in the target storage module. The identification information is a positive integer. The identification information includes a default identification ID and a specified identification ID. The default identification ID is used for indicating that the data corresponds to a default starting address; the specified identification ID is used for indicating that the data corresponds to a specified starting address. In at least one embodiment of the present invention, the default ID is 0, and the specific ID may be 1, 2, or 3. A list of correspondence relationships between default identification IDs, designated identification IDs, default starting addresses, and designated starting addresses may be stored in the first storage module 205 and the second storage module 206.

And S11, when a query instruction is detected, the memory queries the initial address corresponding to the data according to the identification information.

Referring to fig. 2, in at least one embodiment of the present invention, the step of the memory querying the start address and the target storage module corresponding to the data according to the identification information includes:

s110, judging whether the identification information is the default identification ID;

s111, when the identification information is not the default identification ID, acquiring a designated address corresponding to the designated identification ID as an initial address;

and S112, when the identification information is the default identification ID, acquiring a default address corresponding to the default identification ID as a starting address.

In at least one embodiment of the invention, the default address corresponding to the default ID is 468, and the specific address corresponding to the specific ID is 476.

And S12, when a setting instruction is detected, setting the preset storage module corresponding to the data as a target storage module, and setting a target control module according to the preset operation corresponding to the data.

Referring to fig. 3, in at least one embodiment of the present invention, the step of setting the preset storage module corresponding to the data as a target storage module and setting a target control module according to a predetermined operation corresponding to the data includes:

s121, setting the preset storage module corresponding to the data as a target storage module;

s122, judging whether the preset operation information is a reading operation;

s123, when the preset operation information is read operation, setting a read control module in the memory as a target control module;

and S124, setting the write control module in the memory as a target control module when the preset operation information is write operation.

And S13, when a transmission instruction is detected, controlling the pointer of the target control module to transmit the plurality of data segments corresponding to the data from the starting address.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module corresponding to the first storage module 205 and a second cache module corresponding to the second storage module 206. When the operation information is a read operation, the transfer operation is that the read control module starts to transfer the data corresponding to the target storage module to the first cache module from the starting point. When the operation information is a write operation, the transfer operation is that the write control module stores the data from the processor 10 starting from the start address within the target storage module.

S14, when detecting the detection command, determining whether an interrupt command is received.

And S15, when the interrupt instruction is received, judging whether the address corresponding to the current pointer is the last address.

And S16, when the address corresponding to the pointer is the last address, closing the output function of the memory 20.

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 (see fig. 4) of the memory 20 to be turned off.

When the address corresponding to the pointer is not the last address, the process returns to step S14.

When the interrupt instruction is not received, the process returns to step S13.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transfer from the starting point to the last address, the target control module returns to the first address of the target storage module to continue the transfer of the corresponding multiple data segments.

According to the automatic data transmission method, the memory can automatically determine the initial address of the data and transmit the data according to the input data or the input instruction, so that the occupation of the data transmission on a CPU is reduced, and the response speed of the memory in the data transmission process is improved; and further detecting the last address when detecting the interrupt instruction so as to ensure the integrity of data in the data transmission process.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some interfaces, and may be in an electrical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processor, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

It should also be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.