阅读说明：本技术 一种基于hbm缓存的ssd固态盘 (SSD solid state dish based on HBM cache ) 是由 李瑞东 郭鹏 于 2021-09-01 设计创作，主要内容包括：本发明涉及一种基于HBM缓存的SSD固态盘,包括基于HBM和DRAM混合缓存的SSD固态盘和基于HBM缓存的SSD固态盘两种方式,基于HBM和DRAM混合缓存的SSD固态盘混合使用HBM和DRAM作为缓存,DRAM存储FTL映射表,HBM提供缓存功能。基于HBM缓存的SSD固态盘使用HBM替代DRAM,HBM具有缓存数据和存储FTL映射表的功能。本发明在处理写放大、垃圾回收过程中保障了读写带宽恒定、降低了读写时延,较大程度的保证高并发、多路视频数据存取的效率。(The invention relates to an SSD solid state disk based on HBM cache, which comprises two modes of an SSD solid state disk based on HBM and DRAM mixed cache and an SSD solid state disk based on HBM cache. The SSD solid-state disk based on the HBM cache uses the HBM to replace a DRAM, and the HBM has functions of caching data and storing an FTL mapping table. The invention ensures the constant read-write bandwidth, reduces the read-write time delay and ensures the efficiency of high concurrent and multi-channel video data access to a greater extent in the processes of processing write amplification and garbage recovery.)

1. An SSD solid state disk based on HBM cache, characterized in that: the system comprises an SSD controller, a DRAM cache controller, an HBM cache controller, an NAND controller, a DRAM cache medium, an HBM cache medium and an NAND Flash, wherein the SSD controller comprises a PCIe host interface, an NVME protocol controller and an FTL mapping manager which are sequentially connected;

the PCIe host interface is used for data transmission between the SSD solid-state disk and the application of the computing node;

the NVME protocol controller is used for processing an NVME storage protocol between the computing node and the SSD solid-state disk;

the FTL mapping manager is responsible for maintaining the mapping relation from the logical block address to the physical block address of the flash memory medium;

the DRAM controller is responsible for storing an FTL address mapping table and a data read-write control instruction in a running state and finishing data interaction with the HBM controller and the NAND controller;

the HBM controller is responsible for completing data access with the HBM cache medium, interacts with the DRAM controller according to the reading and writing positions of data, and receives a data reading instruction and a data writing instruction sent by the DRAM controller; interacting with the NAND controller, and writing the cache data in the HBM into a NAND flash memory medium or reading application data from the NAND flash memory medium;

the NAND controller is responsible for completing data access with NAND Flash in the Flash memory storage medium layer;

when the HBM cache is enabled, the FTL address mapping manager places data in an HBM cache medium through the HBM controller; when the NAND Flash memory medium is used, the FTL address mapping manager places the data cache and the Log data in the NAND Flash through the NAND controller; when the SSD solid state disk executes garbage collection operation, the HBM controller receives data from the NAND controller, completes related operations and then sends the data to the NAND controller, so that access to the DRAM controller is reduced, and interruption times of the DRAM controller in FTL processing are reduced.

2. The HBM cache-based SSD solid state disk of claim 1, wherein: when the NAND controller is in a busy state or executes garbage collection, adopting a write-back mode and a read-back mode; in a write-back mode, the SSD controller sends a write instruction to the DRAM controller, the DRAM controller sends the received write instruction to the HBM controller to complete address conversion, then the write instruction is transmitted back to the DRAM controller to update the write instruction, and write-in data are written into an HBM cache medium from the SSD controller through the HBM controller, and the write is successful;

in the read-back mode, the NAND controller reads the large block data into the HBM cache medium through the HBM controller in a sequential reading mode, and the SSD controller reads the data from the HBM cache medium through the HBM controller, so that the reading is successful.

3. The HBM cache-based SSD solid state disk of claim 1, wherein: when the NAND controller is in an idle state or the computing node requires the SSD solid-state disk to keep strong consistency of data, starting a write-through mode and a read-through mode; in a write-through mode, write-in data enter a DRAM cache medium from the SSD controller to the DRAM controller, and then enter an NAND flash memory medium from the DRAM controller to the NAND controller; in the read-through mode, a read address enters a DRAM cache medium from a NAND controller to a DRAM controller, then the read address is sent to an FTL mapping manager by the DRAM controller, and read data is directly sent to an SSD controller by the NAND controller.

4. The HBM cache-based SSD solid state disk of claim 1, wherein: the data flow for data redundancy error correction and consistency protection is: the data reading direction is from the NAND controller to the HBM controller, so that the data enters the HBM cache medium, then the data is read out from the HBM cache medium to the FTL mapping manager, and data alignment, consistency check and redundancy error correction are performed in the HBM cache medium; the data writing direction allocates a new address and an old address for the new data to the FTL mapping manager, and then the new address falls into the NAND flash memory medium of the new address from the HBM controller to the NAND controller.

5. The HBM cache-based SSD solid state disk of claim 1, wherein: the data flow direction of the address mapping table is as follows: the address write direction is from the NAND controller to the DRAM controller, and the address read direction is from the DRAM controller to the NAND controller.

6. An SSD solid state disk based on HBM cache, characterized in that: the system comprises an SSD controller, an HBM cache controller, an NAND controller, an HBM cache medium and an NAND Flash, wherein the SSD controller comprises a PCIe host interface, an NVME protocol controller and an FTL mapping manager which are sequentially connected;

the PCIe host interface is used for data transmission between the SSD solid-state disk and the application of the computing node;

the NVME protocol controller is used for processing an NVME storage protocol between the computing node and the SSD solid-state disk;

the FTL mapping manager is responsible for maintaining the mapping relation from the logical block address to the physical block address of the flash memory medium;

the HBM controller and the HBM cache medium are used for caching data and storing an FTL mapping table, and interact with the NAND controller according to the reading and writing positions of the data to write the cache data in the HBM into the NAND flash memory medium or read application data from the NAND flash memory medium;

the NAND controller is responsible for completing data access with the NAND Flash in the Flash memory storage medium layer.

7. The HBM-cache-based SSD solid state disk of claim 6, wherein: when the NAND controller is in a busy state, adopting a write-back mode and a read-back mode; under a write-back mode, the SSD controller writes the received data into an HBM cache medium;

in the read-back mode, the NAND controller reads the large block data into the HBM cache medium in a sequential reading mode, and the SSD controller reads the data from the HBM cache medium through the HBM controller.

8. The HBM-cache-based SSD solid state disk of claim 6, wherein: when the NAND controller is in an idle state, starting a write transparent mode and a read transparent mode; in a write-through mode, the SSD controller writes the received data into the NAND flash memory medium through the HBM controller and the NAND controller; in the read-through mode, the SSD controller reads actual data in the NAND flash memory medium through the HBM controller and the NAND controller according to a received data read instruction, and returns success after executing redundancy check.

9. The HBM-cache-based SSD solid state disk of claim 6, wherein: the data flow for data redundancy error correction and consistency protection is: the data reading direction enters an HBM cache medium from a NAND controller and the HBM controller, then the data is read out to an FTL mapping manager from the HBM cache medium, and data alignment, consistency check and redundancy error correction are performed in the HBM cache medium; the data writing direction allocates a new address and an old address for the new data to the FTL mapping manager, and then the new address falls into the NAND flash memory medium of the new address from the HBM controller to the NAND controller.

10. The HBM-cache-based SSD solid state disk of claim 6, wherein: the data flow direction of the address mapping table is as follows: the address write direction is from the NAND controller to the HBM controller and the address read direction is from the DRAM controller to the NAND controller.

Technical Field

The invention relates to the field of solid-state storage, in particular to an SSD solid-state disk based on HBM cache.

Background

The SSD solid state disk mainly comprises a main control chip, flash memory particles, a cache chip, a PCB and the like. The main control chip controls and manages the space of all the flash memory particles and determines the specific distribution position of data on the flash memory particles. And the flash memory grain provides actual storage space for storing actual application data. The PCB is the base of the SSD solid state disk on which all chips and related electronic components are soldered, and is the basis of the solid state disk. The cache chip is specially present in the SSD solid state disk, and is mainly used for storing an FTL address mapping table, representing the corresponding (mapping) relationship between the physical address of the unit space in the flash memory granule and the logical address of the file system, and mapping the logical address of the storage space which can be identified by the host to the physical address of the actual flash memory granule one by one.

The cache chip is a necessary component of the high-configuration SSD, and the low-configuration SSD eliminates the cache chip for saving cost. In an SSD solid state disk adopting a cache chip, an FTL mapping table is completely placed in a DRAM cache, the DRAM cache capacity is configured according to the proportion of a flash memory particle storage space to the DRAM cache capacity of 1GB:1MB, the solid state disk has the help of the DRAM cache, and the accessibility of the solid state disk can be kept at a constant level in the continuous data reading and writing process. Only in the application that constant read-write performance is insensitive in the continuous data access process, the SSD solid-state disk can directly write the FTL mapping table into the flash memory particles, so that a DRAM cache chip can be removed, the performance of the whole disk is reduced, and meanwhile, the cost is saved. The SSD solid-state disk with and without the DRAM meets most of the current novel applications and traditional applications.

Along with the rise of AI and large-scale video data, the demand of video data processing and storage also shows explosive growth, and in novel data center, pending video data has reached thousands ~ hundreds of thousands way, and this has just promoted the appearance of the novel processing mode of video data, requires single computational node to break through traditional tens of ways video processing ability, reaches hundreds of ways of processing level. In hundreds of video processing applications, the conventional HDD cannot meet the storage bandwidth requirement; the novel NVMe SSD has the storage bandwidth meeting the requirement, but the time delay in the continuous high-frequency concurrent access process is also the challenge of performance; meanwhile, the video data is continuously written and read, so that the SSD solid-state disk is continuously in a working state, and the problems of write amplification and garbage recovery of the SSD solid-state disk are solved without enough idle time, and finally, the storage performance is reduced, and the video data is lost.

Aiming at the problem of the reduction of the read-write performance of the SSD, a common countermeasure in the industry is to optimize at the level of an algorithm and firmware, and mechanisms such as 4K alignment, Trim command, wear leveling and the like reduce write amplification. However, the method also belongs to a scheme for reducing write amplification and garbage recovery, and only can reduce the reduction range of the performance of the SSD, but cannot greatly improve the data access capability of the SSD, and particularly cannot reduce the read-write delay.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides the SSD solid-state disk based on the HBM cache, which ensures the constant read-write bandwidth, reduces the read-write time delay and ensures the efficiency of high-concurrency and multi-channel video data access to a greater extent in the processes of processing write amplification and garbage recovery.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: an SSD solid state disk based on HBM cache comprises an SSD controller, a DRAM cache controller, an HBM cache controller, an NAND controller, a DRAM cache medium, an HBM cache medium and an NAND Flash, wherein the SSD controller comprises a PCIe host interface, an NVME protocol controller and an FTL mapping manager which are sequentially connected;

the PCIe host interface is used for data transmission between the SSD solid-state disk and the application of the computing node;

the NVME protocol controller is used for processing an NVME storage protocol between the computing node and the SSD solid-state disk;

the FTL mapping manager is responsible for maintaining the mapping relation from the logical block address to the physical block address of the flash memory medium;

the DRAM controller is responsible for storing an FTL address mapping table and a data read-write control instruction in a running state and finishing data interaction with the HBM controller and the NAND controller;

the HBM controller is responsible for completing data access with the HBM cache medium, interacts with the DRAM controller according to the reading and writing positions of data, and receives a data reading instruction and a data writing instruction sent by the DRAM controller; interacting with the NAND controller, and writing the cache data in the HBM into a NAND flash memory medium or reading application data from the NAND flash memory medium;

the NAND controller is responsible for completing data access with NAND Flash in the Flash memory storage medium layer;

when the HBM cache is enabled, the FTL address mapping manager places data in an HBM cache medium through the HBM controller; when the NAND Flash memory medium is used, the FTL address mapping manager places the data cache and the Log data in the NAND Flash through the NAND controller; when the SSD solid state disk executes garbage collection operation, the HBM controller receives data from the NAND controller, completes related operations and then sends the data to the NAND controller, so that access to the DRAM controller is reduced, and interruption times of the DRAM controller in FTL processing are reduced.

Further, when the NAND controller is in a busy state or executes garbage collection, a write-back mode and a read-back mode are adopted; in a write-back mode, the SSD controller sends a write instruction to the DRAM controller, the DRAM controller sends the received write instruction to the HBM controller to complete address conversion, then the write instruction is transmitted back to the DRAM controller to update the write instruction, and write-in data are written into an HBM cache medium from the SSD controller through the HBM controller, and the write is successful;

in the read-back mode, the NAND controller reads the large block data into the HBM cache medium through the HBM controller in a sequential reading mode, and the SSD controller reads the data from the HBM cache medium through the HBM controller, so that the reading is successful.

Further, when the NAND controller is in an idle state or the computing node requires the SSD solid state disk to keep strong consistency of data, a write-through mode and a read-through mode are started; in a write-through mode, write-in data enter a DRAM cache medium from the SSD controller to the DRAM controller, and then enter an NAND flash memory medium from the DRAM controller to the NAND controller; in the read-through mode, a read address enters a DRAM cache medium from a NAND controller to a DRAM controller, then the read address is sent to an FTL mapping manager by the DRAM controller, and read data is directly sent to an SSD controller by the NAND controller.

Further, the data flow of data redundancy error correction and consistency protection is as follows: the data reading direction is from the NAND controller to the HBM controller, so that the data enters the HBM cache medium, then the data is read out from the HBM cache medium to the FTL mapping manager, and data alignment, consistency check and redundancy error correction are performed in the HBM cache medium; the data writing direction allocates a new address and an old address for the new data to the FTL mapping manager, and then the new address falls into the NAND flash memory medium of the new address from the HBM controller to the NAND controller.

Further, the data flow of the address mapping table is as follows: the address write direction is from the NAND controller to the DRAM controller, and the address read direction is from the DRAM controller to the NAND controller.

The SSD solid state disk based on HBM cache of the present invention has another implementation manner, which specifically is: the system comprises an SSD controller, an HBM cache controller, an NAND controller, an HBM cache medium and an NAND Flash, wherein the SSD controller comprises a PCIe host interface, an NVME protocol controller and an FTL mapping manager which are sequentially connected;

the PCIe host interface is used for data transmission between the SSD solid-state disk and the application of the computing node;

the NVME protocol controller is used for processing an NVME storage protocol between the computing node and the SSD solid-state disk;

the FTL mapping manager is responsible for maintaining the mapping relation from the logical block address to the physical block address of the flash memory medium;

the HBM controller and the HBM cache medium are used for caching data and storing an FTL mapping table, and interact with the NAND controller according to the reading and writing positions of the data to write the cache data in the HBM into the NAND flash memory medium or read application data from the NAND flash memory medium;

the NAND controller is responsible for completing data access with the NAND Flash in the Flash memory storage medium layer.

Further, when the NAND controller is in a busy state, a write-back mode and a read-back mode are adopted; under a write-back mode, the SSD controller writes the received data into an HBM cache medium;

in the read-back mode, the NAND controller reads the large block data into the HBM cache medium in a sequential reading mode, and the SSD controller reads the data from the HBM cache medium through the HBM controller.

Further, when the NAND controller is in an idle state, a write through mode and a read through mode are started; in a write-through mode, the SSD controller writes the received data into the NAND flash memory medium through the HBM controller and the NAND controller; in the read-through mode, the SSD controller reads actual data in the NAND flash memory medium through the HBM controller and the NAND controller according to a received data read instruction, and returns success after executing redundancy check.

Further, the data flow of data redundancy error correction and consistency protection is as follows: the data reading direction enters an HBM cache medium from a NAND controller and the HBM controller, then the data is read out to an FTL mapping manager from the HBM cache medium, and data alignment, consistency check and redundancy error correction are performed in the HBM cache medium; the data writing direction allocates a new address and an old address for the new data to the FTL mapping manager, and then the new address falls into the NAND flash memory medium of the new address from the HBM controller to the NAND controller.

Further, the data flow of the address mapping table is as follows: the address write direction is from the NAND controller to the HBM controller and the address read direction is from the DRAM controller to the NAND controller.

Drawings

FIG. 1 is a schematic block diagram of embodiment 1;

fig. 2 is a schematic block diagram of embodiment 2.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

In the application environment of AI and large-scale short video, a single compute node carries continuous writing of hundreds of ways of high-speed video data, which requires both large bandwidth, high concurrency, and low latency. Compared with SATA SSD and HDD, the current NVMe SSD product greatly improves the read-write bandwidth and IOPS performance, but the IO time delay is reduced by a small amount. Further analyzing the SSD structure, finding out that the IO delay factor is determined to be the type of the host interface, such as an SATA interface and a PCIe interface; the update speed of the FTL, such as in a cache, NAND flash memory; data is written into NAND types such as SLC, MLC, TLC, QLC. The host interface type and the NAND flash memory type determine the cost of the solid-state disk, and there is basically no optimization range in terms of performance and time delay. The FTL is placed behind the DRAM cache, and the optimization performance and the time delay amplitude at the algorithm layer are small; in the continuous multi-concurrent writing and reading AI video service, a large number of reading and writing requests start to be accumulated and wait for NAND Flash to process the reading and writing operation, and the video reading and writing requests which cannot be processed in time have frame loss. In the multi-path video processing, once a large number of frame losses occur, the application layer considers that more computing nodes (servers) are added; write operations are found frequently in the SSD layer, but the upper performance limit of the solid state disk is not reached, and more SSD solid state disks are typically configured. Both of these approaches are solutions to ensure that the written data is reliable.

In view of the excellent performance of DRAM caches in data access operations, the compute node (server) dimension is typically configured with a large capacity cache, ensuring that large amounts of video data on the network can be received locally and then written to the local HDD mechanical disks or SSD solid state disks. In order to ensure that the SSD solid state disk can receive data streams continuously written and read at a constant rate, manufacturers also increase the capacity of the DRAM cache in the SSD solid state disk, and cache a part of application data written by the host in addition to bearing FTL data, which improves the efficiency of the SSD solid state disk for receiving data. However, the size of the SSD solid state disk is limited, the number of DRAM chips is increased, the space of the NAND flash memory in the SSD solid state disk is occupied, the capacity of the entire disk is reduced, and a capacitor device with a larger capacity needs to be configured, which increases the risk of instability.

The HBM cache has the characteristics of high speed and large capacity, and is a novel packaging form for stacking the DRAMs by using the TSV technology. The HBM cache formed by stacking a plurality of DRAM chips has good performance in the aspects of processing and caching video data, the physical size of the plane of the HBM cache is not remarkably increased, the performance, capacity and size requirements of the high-capacity cache of the SSD solid-state disk can be met, and the outstanding capacity advantage can be used as the cache of application data in the SSD solid-state disk.

Based on this, the invention provides an SSD solid state disk based on HBM cache, which has two implementation manners, that is, the SSD solid state disk based on HBM and DRAM mixed cache described in embodiment 1 and the SSD solid state disk based on HBM cache described in embodiment 2.

In the SSD solid state disk based on the HBM and DRAM hybrid cache of embodiment 1, the FTL address mapping table information is processed by using the DRAM, the application data is processed by using the high-capacity and high-speed HBM cache, and the data garbage collection operation is performed in the continuous write-in process, so that the read-write pressure of the DRAM can be reduced, the update efficiency of the FTL address data is ensured, the processing efficiency of the application data is improved, the data relocation speed in the garbage collection process is increased, the influence of write amplification on the performance of the entire disk is reduced, and the SSD solid state disk has a stronger data receiving capability compared with the conventional SSD solid state disk. Taking 8TB SSD as an example, the capacity of the cache required by the FTL is 8GB, and a DDR cache chip is adopted as the storage space of the address mapping table of the FTL; and meanwhile, a large-capacity HBM2E cache (the capacity is 16 GB-64 GB) is configured, 1 HBM2E chip can meet the capacity and performance requirements, when 4 chips are added, the total capacity of the cache reaches 64GB, and the redundant cache capacity can bear the data writing or reading margin of more than 9s (64 GB/7 GB/s = 9.14s), so that the data receiving capacity of the SSD solid disk is greatly improved, and the problem of read-write time delay of the NAND flash memory is completely shielded.

The SSD solid state disk based on HBM cache according to embodiment 2 has a stronger capability of receiving data than a general SSD solid state disk. Taking 8TB SSD as an example, the capacity of the cache required by the FTL is 8GB, and taking DDR4.0 cache chips, 4 DRAM chips need to be pasted; if a single chip HBM2E with the maximum capacity of 16GB is adopted, 1 HBM2E chip can meet the capacity and performance requirements, when the number of the chips is increased to 4, the total cache capacity reaches 64GB, and the redundant cache capacity can bear data writing or reading margin of more than 8s ((64 GB-8 GB)/7 GB/s = 8s), so that the data receiving capacity of the SSD solid disk is greatly improved, and the read-write delay problem of the NAND flash memory can be shielded.

Example 1

The embodiment discloses an SSD solid state disk based on HBM and DRAM hybrid cache, as shown in fig. 1, comprising an SSD controller, a DRAM cache controller, an HBM cache controller and a NAND controller, a DRAM cache medium, an HBM cache medium and a NAND Flash.

The SSD controller comprises a PCIE interface, an NVME protocol controller and an FTL mapping manager which are sequentially connected, the NAND controller, a DRAM controller and an MRAM controller are respectively connected with the FTL mapping manager, a DRAM cache medium and an HBM cache medium are external caches, the DRAM cache medium is connected with the DRAM cache controller, the HBM cache medium is connected with the HBM cache controller, and the NAND Flash is connected with the NAND controller.

The components and the functions of each part are as follows:

the PCIE host interface is used for carrying out data transmission with an application of a computing node (server);

the NVMe protocol controller is used for processing an NVMe storage protocol between the computing node and the SSD solid-state disk, completing command analysis of the protocol such as session identification, session control, data packet reading and data packet writing, and completing session management and data transmission instructions with the DRAM controller, the HBM controller and the NAND controller.

And the FTL address mapping manager is responsible for maintaining the mapping relation from the logical block address LBA to the physical block address PBA of the flash memory medium. The FTL address mapping manager places the mapping table and the data cache in an external DRAM medium through a DRAM controller; when the HBM cache is started, the FTL address mapping manager places data in an external HBM cache medium through the HBM controller; when the NAND flash memory medium is used, the FTL address mapping manager places the data cache and the Log data in an external NAND through the NAND controller; when the SSD solid state disk executes garbage collection operation, the HBM controller receives data from the NAND controller, completes alignment and other operations, and then sends the data to the NAND controller, so that the access to the DRAM controller is reduced, and the interruption frequency of the DRAM controller in processing the FTL is reduced.

The DRAM controller comprises a DRAM redundancy error correction module and a DRAM medium interface module, is responsible for storing an FTL address mapping table and a data read-write control instruction in a running state, and completes data interaction with the HBM controller and the NAND controller.

The HBM controller comprises an HBM ECC unit and an HBM interface and is responsible for completing data access with an external HBM in an external cache medium layer, wherein the HBM ECC unit adopts a redundancy error correction algorithm to perform data redundancy error correction protection. Interacting with a DRAM controller according to the reading and writing positions of data, and receiving a data reading instruction and a data writing instruction sent by the DRAM controller; and interacting with the NAND controller to write the cache data in the HBM into the NAND flash memory medium or read the application data from the NAND flash memory medium.

The NAND controller comprises a NAND redundancy error correction module and a NAND medium interface module and is responsible for completing data access with external NAND in the flash memory storage medium layer, wherein the NAND redundancy error correction module adopts an LDPC error correction algorithm and an RAID error correction algorithm which are commonly used in the industry to perform redundancy protection on the application data block.

The flow direction of the application data and the Log data is that the data writing direction enters the DRAM cache medium from a PCIe host interface, through an NVMe protocol controller and according to an FTL address mapping manager through a path I to the DRAM controller, and enters the NAND flash memory medium through a path II according to whether the data is to be written completely or not. The data reading direction is from the NAND controller to the DRAM controller through a path III, enters a DRAM cache medium and is from the FTL mapping manager through a path I; and the NAND controller passes through the path according to whether the read is transparent or notDirectly into the FTL mapping manager. This way is the data flow of a standard SSD disk.

And controlling the read-write mode of the application data according to the busy degree of the NAND controller, and adopting a write-back mode when the NAND controller is busy or executes garbage collection. The data writing direction is received by SSD controller, the writing command is transmitted to DRAM controller through pathCompleting HBM controller address conversion and routingUpdating write commands to the DRAM controller, writing data through the pathWriting to the HBM cache medium indicates a write success. In the read-back mode, the NAND controller adopts the sequential read mode to pass the large data block through the path in the data read directionReading into HBM controller and entering HBM buffer medium, SSD controller passing through HBM controller via pathReading data from the HBM cache medium indicates success. The large-scale data writing and reading are completed through a high-capacity and high-speed HBM cache medium, the interruption times of the NAND controller for processing the access operation are reduced, and the data reading and writing performance can be remarkably improved.

When the computing node requires that the SSD solid state disk keeps strong data consistency, a write-through mode is started, and the data flow direction is completely consistent with that of a standard SSD solid state disk; when the read-through mode is started, the data flow is completely consistent with a standard SSD solid state disk.

Data flow for data redundancy error correction and consistency protection: the data read direction is routed by the NAND controllerTo an external HBM controller, enters an HBM cache medium and passes through a pathTo FTL mapping manager; performing data alignment, consistency check and redundancy error correction in an HBM cache medium; routing new data through data write directionTo FTL mapping manager, assign new addresses, discard old addresses, and then traverse the pathTo the NAND controller, the NAND flash media that falls into the new address.

The data flow direction of the address mapping table is as, the address writing direction is from the NAND controller to the DRAM controller through the route c; the address read direction is routed from the DRAM controller to the NAND controller.

The SSD solid state disk has the beneficial effects that:

1. the storage and processing modes of FTL address mapping data are not changed, but the processing efficiency is improved. The invention still adopts the DRAM controller and the DRAM medium, but reduces the access frequency of data reading and writing operations to the DRAM controller, reduces the interruption times of the DRAM controller, and ensures that all the resources of the DRAM are used for processing the FTL address mapping information.

2. The high-performance and large-capacity HBM is used as a data read-write buffer, so that the whole time delay of the whole disk is reduced, and the more stable data read-write speed is ensured. The high-performance and high-capacity HBM cache replaces a DRAM to serve as a data cache medium, application data fall into the HBM cache firstly and then are written into a NAND flash memory medium, read-write conflicts of the NAND flash memory medium in the data writing and reading processes are avoided better, parallel pressure of a NAND controller during concurrent reading and writing is reduced, overall low time delay of the SSD controller is guaranteed, and read-write bandwidth is improved.

3. The influence of NAND write amplification on the performance of the whole SSD is reduced, the redundancy error correction and consistency check operation of data in the traditional SSD solid-state disk depends on the SSD controller to move the fragment data from one NAND to another NAND, and the NAND controller has high load and large pressure and has large influence on the performance of the whole read-write. The large-capacity HBM cache is adopted, the fragment data directly enter the HBM cache, the transmission speed and the error correction speed are high, the large-capacity cache can wait for the NAND controller to queue for writing, and the influence on the read-write performance of the whole SSD is small.

4. According to the scheme for realizing the high-capacity and high-speed cache-based SSD solid-state disk, if the same data power-down protection effect of the traditional SSD is achieved, a capacitor with larger capacity needs to be configured or a power-down protection mechanism depending on the whole machine needs to be configured.

Example 2

The embodiment discloses an SSD solid-state disk based on HBM cache, which makes full use of the characteristics of high capacity, high performance and low time delay of a video processing cache chip, purposefully reduces the read-write time delay of an SSD main control chip and the solid-state disk, accelerates the access performance of video data, and ensures the receiving and storage quality of application data. As shown in fig. 2, the SSD controller includes an SSD controller, an HBM cache controller, an NAND controller, a NAND Flash, and an HBM cache medium, the SSD controller includes a PCIE interface, an NVME protocol controller, and an FTL mapping manager that are sequentially connected, the HBM cache controller and the NAND controller are respectively connected to the FTL mapping manager, the HBM cache medium is connected to the HBM cache controller, and the NAND Flash is connected to the NAND controller.

The components and the functions of each part are as follows:

the PCIE host interface is used for carrying out data transmission with an application of a computing node (server);

the NVMe protocol controller is used for processing an NVMe storage protocol between the computing node and the SSD solid-state disk, completing command analysis of the protocol such as session identification, session control, data packet reading, data packet writing and the like, and completing session management and data transmission instructions with the HBM controller and the NAND controller.

And the FTL address mapping manager is responsible for maintaining the mapping relation from the logical block address LBA to the physical block address PBA of the flash memory medium. When an external HBM cache medium is used, the FTL address mapping manager places a mapping table and a data cache in the external HBM medium through the HBM controller; when using NAND flash media, FTL address mapping manager puts data cache, Log data in external NAND through NAND controller.

The NAND controller comprises a NAND redundancy error correction module and a NAND medium interface module and is responsible for completing data access with external NAND in the flash memory storage medium layer, wherein the NAND redundancy error correction module adopts an LDPC error correction algorithm and an RAID error correction algorithm which are commonly used in the industry to perform redundancy protection on the application data block.

The HMB controller comprises an HBM ECC unit and an HBM interface and is responsible for completing data access with an external HBM in an external cache medium layer, wherein the HBM ECC unit adopts a redundancy error correction algorithm to perform data redundancy error correction protection. And according to the reading and writing positions of the data, interacting with the NAND controller, and writing the cache data in the HBM into the NAND flash memory medium or reading the application data from the NAND flash memory medium.

The flow direction of the application data and the Log data is that the data writing direction enters an HBM cache medium from a PCIe host interface, through an NVMe protocol controller, according to an FTL address mapping manager and through a path (i) to the HBM controller,and entering the NAND flash memory medium through a path II to the NAND controller according to whether the data needs to be completely written. The data reading direction is from the NAND controller to the external HBM controller through a path c, enters the HBM cache medium and is from the FTL mapping manager through a path I; and the NAND controller passes through the path according to whether the read is transparent or notDirectly into the FTL mapping manager.

According to the busy degree of the NAND controller, the read-write mode of the application data can be controlled, when the NAND controller is busy, a write-back mode (the SSD controller writes the received data into the HBM cache medium to indicate successful write) and a read-back mode (the NAND controller reads the large block data into the HBM cache medium in a sequential read mode, and the SSD controller reads the data from the HBM cache medium through the HBM controller to indicate successful read) are adopted; when the NAND controller is idle, a write-through mode (the SSD controller writes the received computing node data into the NAND flash memory medium through the HBM controller and the NAND controller, that is, it indicates that the write is successful) and a read-through mode (the SSD controller reads the received data read command, reads the actual data in the NAND flash memory medium through the HBM controller and the NAND controller, and performs redundancy check, and then returns a success).

Data flow for data redundancy error correction and consistency protection: the data reading direction is from the NAND controller to the external HBM controller through a path c, enters the HBM cache medium and is from the FTL mapping manager through a path I; performing data alignment, consistency check and redundancy error correction in an HBM cache medium; in the data writing direction, new data is sent to the FTL mapping manager through a path I, new addresses are distributed, old addresses are abandoned, and then the new data is sent to the NAND controller through a path II and falls into a NAND flash memory medium of the new addresses.

The data flow direction of the address mapping table is as, the address writing direction is from the NAND controller to the HBM controller through a route c; the address reading direction is routed from the HBM controller to the NAND controller.

This embodiment the solid state disk's beneficial effect does:

the data writing and reading speed is fast: the cache capacity is large, the speed is high, the cache space can be used as a storage space of an FTL address mapping table, can also be used as a cache space of application data (the data is written into the HBM faster than the data falls into the NAND), and can also be used as a data cache space in the data redundancy error correction and consistency check process (the data processing speed in the HBM is faster than the processing speed in the NAND).

As a data read-write buffer, the whole time delay is reduced, and the more stable data I/O speed is ensured. The HBM cache is used for replacing a DRAM, application data fall into the HBM cache firstly and then are written into a NAND flash memory medium, read-write conflicts of the NAND flash memory medium in the data writing and reading processes are avoided better, parallel pressure of a NAND controller during concurrent reading and writing is reduced, and overall low time delay of the SSD controller is guaranteed.

The influence of NAND write amplification on the performance of the whole SSD is reduced, the redundancy error correction and consistency check operation of data in the traditional SSD solid-state disk depends on the SSD controller to move the fragment data from one NAND to another NAND, and the NAND controller has high load and large pressure and has large influence on the performance of the whole read-write. The large-capacity HBM cache is adopted, the fragment data directly enter the HBM cache, the transmission speed is high, the error correction processing speed is high, the large-capacity cache can wait for the NAND controller to queue for writing, and the influence on the read-write performance of the whole SSD is small.

The physical space is saved, one large-capacity HBM cache (16 GB) is equivalent to eight common DRAM caches (2G), a 16TB SSD solid-state disk can save 7 DRAM chip spaces, the PCB area is reduced, the quantity of NAND flash memory media in the solid-state disk is increased, and the storage space of the solid-state disk is enlarged.

According to the scheme for realizing the high-capacity and high-speed cache-based SSD solid-state disk, if the same data power-down protection effect of the traditional SSD is achieved, a capacitor with larger capacity needs to be configured or a power-down protection mechanism depending on the whole machine needs to be configured.

The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.