阅读说明：本技术 一种基于FPGA和MBS架构的spacewire总线控制器 (Spacewire bus controller based on FPGA and MBS framework ) 是由 陈润娜 薛时凯 戴春泉 邵志阳 权衡 于 2021-09-28 设计创作，主要内容包括：本发明涉及了一种基于FPGA和MBS架构的spacewire总线控制器,由MBS实现上层控制,FPGA搭建底层逻辑。采用FPGA搭建不同的寄存器读写电路,通过HOCI底层接口逻辑和COMI底层接口逻辑实现对spacewire接口芯片BM4802的读写控制。本控制器的底层逻辑由FPGA搭建,简化了MBS的使用,也能使底层驱动更加灵活的适应各种应用场景,且对HOCI接口和COMI接口不区分使用方法,MBS可直接发送命令,增加了底层驱动可读性与复用性；COMI底层接口逻辑里增加了大容量双口RAM,减少了板卡上的RAM缓存,使硬件更加简洁的同时减小了成本。同时FPGA+MBS的结合使得HOCI接口具备了COMI接口的一部分特性,当使用HOCI接口读写数据时,MBS只需发一次命令,由FPGA解析可循环去读写BM4802的FIFO,极大程度的提高了HOCI接口的传输速率。(The invention relates to a spacewire bus controller based on an FPGA and an MBS framework, wherein the MBS realizes upper layer control, and the FPGA builds bottom layer logic. Different register read-write circuits are built by adopting FPGA, and read-write control of the spacewire interface chip BM4802 is realized through HOCI bottom layer interface logic and COMI bottom layer interface logic. The bottom layer logic of the controller is built by the FPGA, the use of the MBS is simplified, the bottom layer drive can be more flexibly adapted to various application scenes, the use methods of the HOCI interface and the COMI interface are not distinguished, the MBS can directly send commands, and the readability and the reusability of the bottom layer drive are improved; a high-capacity double-port RAM is added in COMI bottom layer interface logic, RAM cache on a board card is reduced, hardware is simpler, and cost is reduced. Meanwhile, the combination of the FPGA and the MBS enables the HOCI interface to have a part of characteristics of the COMI interface, when the HOCI interface is used for reading and writing data, the MBS only needs to send a command once, the FPGA analyzes the FIFO which can be circularly read and written by the BM4802, and the transmission rate of the HOCI interface is greatly improved.)

1. The utility model provides a spacewire bus controller based on FPGA and MBS framework, contains FPGA, MBS, HOCI interface and COMI interface, its characterized in that: the MBS realizes upper layer control, the FPGA builds bottom layer logic, the HOCI interface and the COMI interface are used for the FPGA to build different register read-write circuits, the MBS transmits the command to MBS command analysis, the MBS command analysis transmits the command to the bottom layer control center, and the bottom layer control center selects the HOCI bottom layer interface logic built by the FPGA or the COMI bottom layer interface logic built by the FPGA to be used to transmit a read-write starting command, a read-write register starting address and a read-write length command.

2. The spacewire bus controller based on the FPGA and MBS framework as claimed in claim 1, wherein: the COMI bottom layer interface logic built by the FPGA comprises a double-port RAM, the MBS and the BM4802 transmit commands to an arbitration module, and the arbitration module distinguishes read and write commands and stores data into the double-port RAM through RAM read control and RAM write control.

3. The spacewire bus controller based on the FPGA and MBS framework as claimed in claim 1, wherein: the spacewire chip used by the controller is a BM4802 control chip.

4. The spacewire bus controller based on the FPGA and MBS framework as claimed in claim 1, wherein: the COMI bottom layer interface logic built by the FPGA and the HOCI bottom layer interface logic built by the FPGA are the same as the command port of the MBS.

Technical Field

The invention belongs to the technical field of spacewire bus controllers, and particularly relates to a spacewire bus controller based on an FPGA and an MBS framework.

Background

The Spacewire bus is used as a high-speed and point-to-point full-duplex serial bus facing spaceflight and comprises two interfaces of HOCI and COMI, wherein the HOCI is simple and easy to control, and the transmission rate is low; the COMI transfer rate is fast but the control method is complex. The common control methods comprise software control and hardware control, the software control is flexible but complex and is not easy to use, and the hardware control is convenient to use but is not flexible. The controller is designed for improving the service performance and the operability of the two interfaces.

Disclosure of Invention

The invention aims to solve the problems and provides a spacewire bus controller based on an FPGA and an MBS framework, wherein the FPGA and the MBS framework are adopted for controlling, the FPGA builds a bottom layer logic, and the MBS realizes an upper layer control. Because the basic logic is built by the FPGA, the MBS control circuit is very simple, and the MBS can also drive the bottom layer, thereby being more flexibly suitable for various applications.

In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a spacewire bus controller based on FPGA and MBS framework, contains FPGA, MBS, HOCI interface and COMI interface, MBS realizes upper control, FPGA sets up the bottom logic, HOCI interface and COMI interface are used for FPGA to set up different register read-write circuit, MBS conveys the order to MBS order analysis, MBS order analysis conveys the order to the bottom control center, bottom control center selects the HOCI bottom interface logic of setting up by FPGA that needs to use or the COMI bottom interface logic of setting up by FPGA, sends and begins read-write command and read-write register start address and read-write length command.

Further: the COMI bottom layer interface logic built by the FPGA comprises a double-port RAM, the MBS and the BM4802 transmit commands to an arbitration module, and the arbitration module distinguishes read and write commands and stores data into the double-port RAM through RAM read control and RAM write control.

Further: the spacewire chip used by the controller is a BM4802 control chip.

Further: the COMI bottom layer interface logic built by the FPGA and the HOCI bottom layer interface logic built by the FPGA are the same as the command port of the MBS.

Compared with the prior art, the invention has the beneficial effects that:

1. MBS software can be flexibly controlled, and the MBS does not distinguish the use method of COMI bottom layer interface logic constructed by the FPGA and HOCI bottom layer interface logic constructed by the FPGA, and the MBS can directly send commands, so that the readability and the reusability are improved;

2. when the HOCI interface is used for reading and writing data, the MBS only needs to send a command once, the FPGA analyzes the FIFO which can be circularly read and written in the BM4802, the efficiency of the software for directly controlling the HOCI interface is improved, the MBS can configure the reading and writing times once, and the MBS does not need to be reconfigured when reading one number each time;

3. the COMI bottom layer interface logic built by the FPGA increases a large-capacity double-port RAM, reduces RAM cache on a board card, makes hardware more concise and reduces cost;

4. the combination of FPGA and MBS ensures that the HOCI interface has part of the characteristics of the COMI interface, and greatly improves the transmission rate of the HOCI interface.

Drawings

In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings needed to be used in the description of the embodiment will be briefly introduced below, it is obvious that the drawings in the following description are only for more clearly illustrating the embodiment of the present invention or the technical solution in the prior art, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic view of the overall structure of the present invention;

fig. 2 is a schematic diagram of the control state machine of the underlying HOCI interface according to the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood and implemented by those skilled in the art, the present invention is further described with reference to the following specific examples, which are provided for illustration only and are not intended to limit the present invention.

The spacewire bus controller based on the FPGA and the MBS framework comprises an FPGA and an MBS, the MBS realizes upper layer control, the FPGA builds bottom layer logic, the HOCI interface and the COMI interface are used for the FPGA to build different register read-write circuits, the MBS transmits a command to MBS command analysis, the MBS command analysis transmits the command to a bottom layer control center, and the bottom layer control center selects the HOCI bottom layer interface logic built by the FPGA or the COMI bottom layer interface logic built by the FPDA to be used to transmit a read-write start command, a read-write register start address and a read-write length command.

The COMI bottom layer interface logic built by the FPGA comprises a double-port RAM, the MBS and the BM4802 transmit commands to an arbitration module, and the arbitration module distinguishes read and write commands and stores data into the double-port RAM through RAM read control and RAM write control.

The COMI bottom layer interface logic built by the FPGA and the HOCI bottom layer interface logic built by the FPGA are reserved for the same command port of the MBS, namely the MBS can directly send the command without distinguishing the HOCI interface and the COMI interface.

Preferably: different register read-write circuits are built by adopting FPGA, and read-write control of the spacewire interface chip BM4802 is realized through HOCI bottom layer interface logic and COMI bottom layer interface logic.

When the COMI interface is used for reading and writing data, the MBS only needs to send a command once, and the FPGA analyzes the FIFO which can be circularly read and written in the BM4802, so that the efficiency of directly controlling the HOCI interface by software is improved.

Key points and protection points of the invention:

1. MBS software can be flexibly controlled, and the MBS does not distinguish the use method of COMI bottom layer interface logic constructed by the FPGA and HOCI bottom layer interface logic constructed by the FPGA, and the MBS can directly send commands, so that the readability and the reusability are improved;

2. when the HOCI interface is used for reading and writing data, the MBS only needs to send a command once, the FPGA analyzes the FIFO which can be circularly read and written in the BM4802, the efficiency of the software for directly controlling the HOCI interface is improved, the MBS can configure the reading and writing times once, and the MBS does not need to be reconfigured when reading one number each time;

3. a high-capacity double-port RAM is added in COMI bottom layer interface logic built by the FPGA, RAM cache on a board card is reduced, hardware is simpler, and cost is reduced;

4. the combination of FPGA and MBS ensures that the HOCI interface has part of the characteristics of the COMI interface, and greatly improves the transmission rate of the HOCI interface.

The controller adopts FPGA to build different register read-write circuits, read-write control of a spacewire interface chip BM4802 is realized through HOCI bottom layer interface logic and COMI bottom layer interface logic, command ports reserved for MBS by the two interface control circuits are consistent, namely for MBS, the two interfaces do not need to be distinguished, only a bottom layer control center needs to be configured to use the COMI bottom layer interface logic built by the FPGA and the HOCI bottom layer interface logic built by the FPGA, and a read-write command, a read-write register start address and a read-write length are sent. The controller greatly reduces the workload of the MBS software, has less error rate, greatly improves the debugging efficiency and increases the reusability.

The details of the present invention not described in detail are prior art.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.