阅读说明：本技术 一种eSPI设备报警方法、装置及电子设备和存储介质 (eSIP equipment alarm method and device, electronic equipment and storage medium ) 是由 王朝辉 刘同强 邹晓峰 于 2021-08-20 设计创作，主要内容包括：本申请公开了一种eSPI设备报警方法、装置及一种电子设备和计算机可读存储介质,该方法包括：当芯片选择信号为高电平时,对报警引脚进行下拉操作；其中,若主机检测到所述报警引脚为低电平,则拉低所述芯片选择信号；当检测到所述芯片选择信号为低电平时,释放所述报警引脚,以使所述报警引脚恢复为高电平,完成所述eSPI设备的报警操作。由此可见,本申请提供的eSPI设备报警方法,eSPI设备通过下拉报警引脚主动向主机发送报警请求,在不影响主机其他业务的前提下实现eSPI设备的报警。(The application discloses an alarm method and device for eSPI equipment, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: when the chip selection signal is at a high level, the alarm pin is pulled down; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down; and when the chip selection signal is detected to be at a low level, releasing the alarm pin so that the alarm pin is recovered to be at a high level, and finishing the alarm operation of the eSIP equipment. Therefore, according to the alarm method for the eSIP equipment, the eSIP equipment actively sends the alarm request to the host through the pull-down alarm pin, and the alarm of the eSIP equipment is realized on the premise of not influencing other services of the host.)

1. An eSIP device alarm method is applied to an eSIP device and comprises the following steps:

when the chip selection signal is at a high level, the alarm pin is pulled down; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

and when the chip selection signal is detected to be at a low level, releasing the alarm pin so that the alarm pin is recovered to be at a high level, and finishing the alarm operation of the eSIP equipment.

2. The eSPI device alarm method of claim 1, wherein the alarm pin is an external pin of an alarm signal if the host corresponds to a plurality of eSPI devices.

3. The eSPI device alarm method of claim 2, wherein the alarm signal is output through a tri-state gate, and the pulling down the alarm pin when the chip select signal is high comprises:

selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

when the target signal is at a high level, the control signal of the tri-state gate is at a high level, and the output of the tri-state gate is enabled, so that the alarm pin is at a low level;

correspondingly, when it is detected that the chip selection signal is at a low level, releasing the alarm pin to enable the alarm pin to be at a high level includes:

and when the target signal is detected to be at a low level, the tri-state gate control signal is at a low level, and the tri-state of the alarm signal is recovered, so that the alarm pin is recovered to be at a high level.

4. The eSPI device alert method of claim 1, wherein if the host corresponds to one of the eSPI devices, the alert pin is specifically a target pin corresponding to a first bit of a data signal.

5. The eSPI device alarm method of claim 4, wherein the data signal is output through a tri-state gate, and the pulling down the alarm pin when the chip select signal is high comprises:

selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

when the target signal is at a high level, an alarm enabling signal is at a high level, and the output of the tri-state gate is enabled, so that the target pin is at a low level;

correspondingly, when it is detected that the chip selection signal is at a low level, releasing the alarm pin to enable the alarm pin to be at a high level includes:

when the chip selection signal is detected to be at a low level, the alarm enabling signal is at a low level, the output enabling signal is at a low level, and the alarm pin is restored to be at a high level; the output enable signal is the OR operation of the alarm enable signal and the data enable signal, and the data enable signal is the tri-state enable of the data signal under the condition of no alarm.

6. The eSPI device alert method of claim 3 or 5, wherein said selecting the local clock comprises:

the AHB bus clock is selected as the local clock.

7. The eSPI device alert method of claim 1, wherein the host is specifically a baseboard management controller.

8. An eSIP device alarm device, applied to an eSIP device, comprising:

the pull-down module is used for performing pull-down operation on the alarm pin when the chip selection signal is at a high level; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

and the release module is used for releasing the alarm pin when the chip selection signal is detected to be at a low level, so that the alarm pin is recovered to be at a high level, and the alarm operation of the eSIP equipment is completed.

9. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the eSPI device alert method of any one of claims 1 to 7 when the computer program is executed.

10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the eSPI device alert method of any one of claims 1 to 7.

Technical Field

The present application relates to the field of computer technologies, and in particular, to an eSPI device alarm method, an eSPI device alarm apparatus, an electronic device, and a computer-readable storage medium.

Background

With the increasing emphasis on server management, large server manufacturers have correspondingly enhanced the manageability features of servers on their respective hardware platforms, and have increasingly strengthened their functions. The system Management software manages each managed device by communicating with a BMC (Baseboard Management Controller). The physical interface between the BMC and the system management software adopts an eSPI (enhanced Serial Peripheral interface) communication protocol, that is, the BMC can be used as a host to communicate with the eSPI device where the system management software is located.

In general, the host processes other traffic, and therefore does not always initiate data transmission with the eSPI device, the eSPI device must send an alert request (alert) to the host if it needs to service, and after receiving the alert request, the host sends a status acquisition COMMAND (COMMAND) to the eSPI device, and the eSPI device responds to current status information (RESPONSE) so that the host determines whether to continue to transmit data. If the host allows the data to continue to be transferred, a data acquisition command is sent to the eSIP device, and the eSIP device responds to the data to be transferred.

Therefore, in the related art, the host actively issues a command to periodically query the state of the eSPI device, which is inefficient, and other services of the host are interrupted due to the periodic query of the state of the eSPI device.

Therefore, how to implement the alarm of the eSPI device without affecting other services of the host is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The application aims to provide an alarm method and device for eSIP equipment, electronic equipment and a computer-readable storage medium, and the alarm of the eSIP equipment is realized on the premise of not influencing other services of a host.

In order to achieve the above object, the present application provides an eSPI device alarm method, which is applied to an eSPI device, and includes:

when the chip selection signal is at a high level, the alarm pin is pulled down; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

and when the chip selection signal is detected to be at a low level, releasing the alarm pin so that the alarm pin is recovered to be at a high level, and finishing the alarm operation of the eSIP equipment.

And if the host corresponds to a plurality of eSPI devices, the alarm pin is specifically an external pin of an alarm signal.

Wherein, alarm signal is through tristate gate output, then when chip select signal is the high level, carry out the pull-down operation to warning pin, include:

selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

when the target signal is at a high level, the control signal of the tri-state gate is at a high level, and the output of the tri-state gate is enabled, so that the alarm pin is at a low level;

correspondingly, when it is detected that the chip selection signal is at a low level, releasing the alarm pin to enable the alarm pin to be at a high level includes:

and when the target signal is detected to be at a low level, the tri-state gate control signal is at a low level, and the tri-state of the alarm signal is recovered, so that the alarm pin is recovered to be at a high level.

And if the host corresponds to one of the eSIP devices, the alarm pin is specifically a target pin corresponding to a first bit of a data signal.

Wherein, the data signal is output through the tri-state gate, and then when the chip select signal is the high level, carry out the pull-down operation to the warning pin, include:

selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

when the target signal is at a high level, an alarm enabling signal is at a high level, and the output of the tri-state gate is enabled, so that the target pin is at a low level;

correspondingly, when it is detected that the chip selection signal is at a low level, releasing the alarm pin to enable the alarm pin to be at a high level includes:

when the chip selection signal is detected to be at a low level, the alarm enabling signal is at a low level, the output enabling signal is at a low level, and the alarm pin is restored to be at a high level; the output enable signal is the OR operation of the alarm enable signal and the data enable signal, and the data enable signal is the tri-state enable of the data signal under the condition of no alarm.

Wherein, the selecting the local clock comprises:

the AHB bus clock is selected as the local clock.

The host is specifically a baseboard management controller.

In order to achieve the above object, the present application provides an eSPI device alarm device, which is applied to an eSPI device, and includes:

the pull-down module is used for performing pull-down operation on the alarm pin when the chip selection signal is at a high level; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

and the release module is used for releasing the alarm pin when the chip selection signal is detected to be at a low level, so that the alarm pin is recovered to be at a high level, and the alarm operation of the eSIP equipment is completed.

To achieve the above object, the present application provides an electronic device including:

a memory for storing a computer program;

a processor configured to implement the steps of the eSPI device alert method described above when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above eSPI device alert method.

According to the scheme, the alarm method for the eSPI equipment comprises the following steps: when the chip selection signal is at a high level, the alarm pin is pulled down; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down; and when the chip selection signal is detected to be at a low level, releasing the alarm pin so that the alarm pin is recovered to be at a high level, and finishing the alarm operation of the eSIP equipment.

According to the alarm method for the eSPI equipment, under the condition that the chip selection signal is at the high level, the alarm pin is pulled down, namely the alarm pin is set at the low level, the alarm pin is detected to be at the low level by the host, the chip selection signal is pulled down, and when the chip selection signal is detected to be at the low level by the eSPI equipment, the alarm pin is released, namely the alarm pin is restored to the high level, so that the alarm operation is completed. Therefore, according to the alarm method for the eSIP equipment, the eSIP equipment actively sends the alarm request to the host through the pull-down alarm pin, and the alarm of the eSIP equipment is realized on the premise of not influencing other services of the host. The application also discloses an eSIP equipment alarm device, electronic equipment and a computer readable storage medium, and the technical effects can be realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

fig. 1 is a flow diagram illustrating an eSPI device alerting method in accordance with an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating an alarm operation using an external pin for an alarm signal in accordance with an exemplary embodiment;

FIG. 3 is a schematic diagram illustrating an alarm operation using a target pin corresponding to a first bit of a data signal in accordance with an exemplary embodiment;

fig. 4 is a flow chart illustrating another eSPI device alerting method in accordance with an exemplary embodiment;

FIG. 5 is a signal timing diagram illustrating an alarm operation using an external pin for an alarm signal in accordance with an exemplary embodiment;

fig. 6 is a flow chart illustrating yet another eSPI device alerting method in accordance with an exemplary embodiment;

FIG. 7 is a signal timing diagram illustrating an alarm operation using a target pin corresponding to a first bit of a data signal in accordance with an exemplary embodiment;

fig. 8 is a block diagram of an eSPI device alert apparatus according to an exemplary embodiment;

FIG. 9 is a block diagram illustrating an electronic device in accordance with an exemplary embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In addition, in the embodiments of the present application, "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a specific order or a sequential order.

The embodiment of the application discloses an alarm method of eSIP equipment, which realizes the alarm of the eSIP equipment on the premise of not influencing other services of a host.

Referring to fig. 1, a flowchart of an eSPI device alerting method according to an exemplary embodiment is shown, as shown in fig. 1, including:

s101: when the chip selection signal is at a high level, the alarm pin is pulled down; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

the execution subject of this embodiment is an eSPI device, that is, the device communicates with a host through an eSPI protocol, where the host may be specifically a baseboard management controller. In this step, the alarm operation must be performed when the Chip Select signal (Chip Select #) is at a high level, and at this time, the alarm pin is pulled down, that is, the alarm pin is set to a low level, and the host detects that the alarm pin is at a low level, and pulls down the Chip Select signal.

As a possible implementation manner, if the host corresponds to a plurality of eSPI devices, the alarm pin is specifically an external pin of an alarm signal. In a specific implementation, the external pin of the alarm signal (Alert #) can be selected as the alarm pin, which is externally provided with a weak pull-up. As shown in fig. 2, the alarm operation must pull down Alert # when Chip Select # is high, pull down the Chip Select # signal when the host detects this low level, and then Alert # releases and returns to a high level.

As another possible implementation, if the host corresponds to one of the eSPI devices, the alarm pin is specifically a target pin corresponding to a first bit of a data signal. In a specific implementation, if one host corresponds to one eSPI device, the first bit IO [1 ] of the Data line Data can be used]And the target pin corresponding to the first bit of the data signal is also used as an alarm pin. As shown in FIG. 3, the alarm operation must be performed on IO [1 ] when Chip Select # is high]Performing pull-down operation, and when the host detects the low level, pulling down the Chip Select # signal at time T_SLAZ(Chip Select # is high, IO [1 ]]The shortest time that can be pulled down), IO [1 ]]Must be released and restored high.

S102: and when the chip selection signal is detected to be at a low level, releasing the alarm pin so that the alarm pin is recovered to be at a high level, and finishing the alarm operation of the eSIP equipment.

In this step, when the eSPI device detects that the chip selection signal is at a low level, the alarm pin is released, that is, the alarm pin is restored to a high level, and the alarm operation is completed.

According to the alarm method for the eSIP equipment, under the condition that the chip selection signal is at the high level, the alarm pin is pulled down, namely the alarm pin is set at the low level, the host detects that the alarm pin is at the low level, the chip selection signal is pulled down, and when the eSIP equipment detects that the chip selection signal is at the low level, the alarm pin is released, namely the alarm pin is restored to the high level, so that the alarm operation is completed. Therefore, according to the alarm method for the eSIP device, the eSIP device actively sends the alarm request to the host through the pull-down alarm pin, and the alarm of the eSIP device is realized on the premise of not influencing other services of the host.

The embodiment of the application discloses an alarm method for eSIP equipment, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, the method comprises the following steps:

referring to fig. 4, a flow diagram of another eSPI device alerting method, as shown in fig. 4, is shown in accordance with an exemplary embodiment, including:

s201: selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

s202: when the target signal is at a high level, the control signal of the tri-state gate is at a high level, and the output of the tri-state gate is enabled, so that the alarm pin is at a low level;

s203: and when the target signal is detected to be at a low level, the tri-state gate control signal is at a low level, and the tri-state of the alarm signal is recovered, so that the alarm pin is recovered to be at a high level, and the alarm operation of the eSIP equipment is completed.

In this embodiment, Alert # passes through a tri-state gate, which is controlled by a tri-state gate control signal (Alert _ oe). When Chip Select # is high, ALert must default to a low level. Since the clock from the host is suspended during the alarm request phase, the slave clock of the eSPI cannot be used, and therefore a local clock, here the AHB bus clock HCLK, must be selected as the local clock. To use the Chip Select # signal, the signal must be tapped two beats to eliminate the meta-stability before it can be used. In the present embodiment, the Chip Select # signal after three beats, i.e., the target signal (Chip _ sel _ n _ ff3) that delays the Chip Select # signal by three clock cycles is used. As shown in FIG. 5, when chip _ sel _ n _ ff3 is detected high, alert _ oe is 1 in the next beat, i.e., the output of the tri-state gate is enabled. The Alert # data output is 0, i.e., low, and once enabled, the data on the external bus appears low. Once chip _ sel _ n _ ff3 goes low, Alert _ oe goes low and Alert # goes back to tri-state.

The embodiment of the application discloses an alarm method for eSIP equipment, and compared with the first embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, the method comprises the following steps:

referring to fig. 6, a flowchart of yet another eSPI device alerting method, as shown in fig. 6, in accordance with an exemplary embodiment, includes:

s301: selecting a local clock, and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

s302: when the target signal is at a high level, an alarm enabling signal is at a high level, and the output of the tri-state gate is enabled, so that the target pin is at a low level;

s303: when the chip selection signal is detected to be at a low level, the alarm enabling signal is at a low level, the output enabling signal is at a low level, and the alarm pin is restored to be at a high level, so that the alarm operation of the eSIP device is completed; the output enable signal is the OR operation of the alarm enable signal and the data enable signal, and the data enable signal is the tri-state enable of the data signal under the condition of no alarm.

In this embodiment, all four data lines need to pass through a tri-state gate. IO [1 ] when Chip Select # is high]The low level must be defaulted. Since the host-originated clock is suspended during the alert phase, the slave clock of the eSPI cannot be used, and therefore a local clock must be selected, where the AHB (Advanced High-performance Bus) Bus clock HCLK can be selected as the local clock. To use the Chip Select # signal, the signal must be tapped two beats to eliminate the meta-stability before it can be used. The present embodiment takes into account T_SHAAThe Chip Select # signal after three beats, i.e., the target signal (Chip _ sel _ n _ ff3) that delays the Chip Select # signal by three clock cycles is used. As shown in FIG. 7, when chip _ sel _ n _ ff3 is detected to be high, the alarm enable signal (io1_ alert _ en) is 1 in the next beat, i.e., the output of the tri-state gate is enabled. At this time, because IO [1 ]]The data of (2) is defaulted to 0, i.e., low, and once the tri-state gate is enabled, the data on the external bus appears low. Because T is taken into account_SLAZThe time is very short and the frequency of HCLK is generally not satisfactory, so chip _ sel _ n (original chip select signal) is used as the reset of io1_ alert _ en, so io1_ alert _ en goes low for a short time when chip _ sel _ n goes low. The output enable signal (io1_ output _ en) is an or operation of io1_ alert _ en and the data enable signal (io1_ data _ en). io1_ data _ en represents tri-state enabling of normal data in a non-alarm situation. Because the external bus has a weak pull-up, the tri-state data bus appears high when io1_ output _ en is 0.

In the following, an eSPI device alarm apparatus provided by an embodiment of the present application is introduced, and an eSPI device alarm apparatus described below and an eSPI device alarm method described above may be referred to each other.

Referring to fig. 8, a block diagram of an eSPI device alert apparatus according to an exemplary embodiment is shown, as shown in fig. 8, including:

the pull-down module 801 is used for performing pull-down operation on the alarm pin when the chip selection signal is at a high level; if the host detects that the alarm pin is at a low level, the chip selection signal is pulled down;

a releasing module 802, configured to release the alarm pin when it is detected that the chip selection signal is at a low level, so that the alarm pin is restored to a high level, and an alarm operation of the eSPI device is completed.

The eSPI equipment alarm device that this application embodiment provided, under the condition that chip selection signal is the high level, drop-down warning pin is about to report to the police the pin and set up low level, and the host computer detects that the warning pin is the low level, draws down chip selection signal, and when the eSPI equipment detected that chip selection signal is the low level, release warning pin is about to report to the police the pin and resume to the high level, accomplishes the alarm operation. Therefore, according to the alarm device for the eSIP equipment provided by the embodiment of the application, the eSIP equipment actively sends the alarm request to the host through the pull-down alarm pin, and the alarm of the eSIP equipment is realized on the premise of not influencing other services of the host.

On the basis of the foregoing embodiment, as a preferred implementation manner, if the host corresponds to a plurality of eSPI devices, the alarm pin is specifically an external pin of an alarm signal.

On the basis of the above embodiment, as a preferred implementation manner, the alarm signal is output through a tri-state gate, and the pull-down module 801 includes:

the selection unit is used for selecting a local clock and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

the first enabling unit is used for enabling the output of the tri-state gate when the target signal is at a high level and the control signal of the tri-state gate is at a high level so as to enable the alarm pin to be at a low level;

correspondingly, the releasing module 802 is specifically a module that when the target signal is detected to be at a low level, the tri-state gate control signal is at a low level, and the tri-state of the alarm signal is restored, so that the alarm pin is restored to be at a high level.

On the basis of the foregoing embodiment, as a preferred implementation manner, if the host corresponds to one of the eSPI devices, the alarm pin is specifically a target pin corresponding to a first bit of a data signal.

On the basis of the foregoing embodiment, as a preferred implementation manner, the data signal is output through a tri-state gate, and the pull-down module 801 includes:

the selection unit is used for selecting a local clock and delaying the chip selection signal for three clock cycles based on the local clock to obtain a target signal;

the second enabling unit is used for enabling the output of the tri-state gate when the target signal is at a high level and the alarm enabling signal is at a high level so as to enable the target pin to be at a low level;

correspondingly, the release module 802 is specifically a module that when the chip select signal is detected to be at a low level, the alarm enable signal is at a low level, the output enable signal is at a low level, and the alarm pin returns to a high level; the output enable signal is the OR operation of the alarm enable signal and the data enable signal, and the data enable signal is the tri-state enable of the data signal under the condition of no alarm.

On the basis of the foregoing embodiment, as a preferred implementation manner, the selecting unit specifically selects an AHB bus clock as a local clock, and delays the chip selection signal by three clock cycles based on the local clock to obtain a target signal.

On the basis of the above embodiments, as a preferred implementation, the host is specifically a baseboard management controller.

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present application, an embodiment of the present application further provides an electronic device, and fig. 9 is a structural diagram of an electronic device according to an exemplary embodiment, as shown in fig. 9, the electronic device includes:

a communication interface 1 capable of information interaction with other devices such as network devices and the like;

and the processor 2 is connected with the communication interface 1 to realize information interaction with other equipment, and is used for executing the eSIP equipment alarm method provided by one or more technical schemes when running a computer program. And the computer program is stored on the memory 3.

In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For the sake of clarity, however, the various buses are labeled as bus system 4 in fig. 9.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 2 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the above embodiment of the present application may be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 2. The processor 2 described above may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 3, and the processor 2 reads the program in the memory 3 and in combination with its hardware performs the steps of the aforementioned method.

When the processor 2 executes the program, the corresponding processes in the methods according to the embodiments of the present application are realized, and for brevity, are not described herein again.

In an exemplary embodiment, the present application further provides a storage medium, i.e. a computer storage medium, specifically a computer readable storage medium, for example, including a memory 3 storing a computer program, which can be executed by a processor 2 to implement the steps of the foregoing method. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.