Integrated assembly and method of forming an integrated assembly
阅读说明：本技术 集成式组合件和形成集成式组合件的方法 (Integrated assembly and method of forming an integrated assembly ) 是由 S·索尔斯 K·舍罗特瑞 M·托鲁姆 于 2021-04-28 设计创作，主要内容包括：本申请涉及集成式组合件及形成集成式组合件的方法。一些实施例包含一种集成式组合件,其具有交替的绝缘和导电层级的竖直堆叠。所述导电层级具有端子区域和非端子区域。所述端子区域在竖直方向上厚于所述非端子区域。沟道材料竖直延伸穿过所述堆叠。隧穿材料邻近所述沟道材料。电荷存储材料邻近所述隧穿材料。高k介电材料处于所述电荷存储材料和所述导电层级的所述端子区域之间。所述绝缘层级在相邻导电层级的所述端子区域之间具有含碳第一区域,且在所述相邻导电层级的所述非端子区域之间具有第二区域。一些实施例包含形成集成式组合件的方法。(The present application relates to an integrated assembly and a method of forming an integrated assembly. Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and non-terminal regions. The terminal region is vertically thicker than the non-terminal region. Channel material extends vertically through the stack. A tunneling material is adjacent the channel material. A charge storage material is adjacent the tunneling material. A high-k dielectric material is between the charge storage material and the terminal region of the conductive level. The insulating levels have a first region comprising carbon between the terminal regions of adjacent conductive levels and a second region between the non-terminal regions of the adjacent conductive levels. Some embodiments include methods of forming an integrated assembly.)
1. An integrated assembly, comprising:
a vertical stack of alternating insulating levels and conductive levels;
the conductive level layer having a terminal region and a non-terminal region in the vicinity of the terminal region; the terminal region is vertically thicker than the non-terminal region;
channel material extending vertically through the stack;
a tunneling material adjacent to the channel material;
a charge storage material adjacent to the tunneling material;
a high-k dielectric material between the charge storage material and the terminal region of the conductive level layer;
the insulating levels having a first region vertically between the terminal regions of adjacent conductive levels and having a second region vertically between the non-terminal regions of the adjacent conductive levels; and
the first region of the insulating level comprises carbon.
2. The integrated assembly of claim 1, wherein the first region of the insulating level comprises a combination of the carbon and one or more of silicon, oxygen, and nitrogen.
3. The integrated assembly of claim 2, wherein the first region of the insulating levels has a horizontal thickness in a range of about 1nm to about 12 nm.
4. The integrated assembly of claim 2, wherein the first region of the insulating levels has a horizontal thickness in a range of about 2nm to about 4 nm.
5. The integrated assembly of claim 1, wherein the second region of the insulating levels comprises silicon dioxide.
6. The integrated assembly of claim 1, wherein the second region of the insulating levels comprises voids.
7. The integrated assembly of claim 1, wherein the first region of the insulating level comprises SiOC, wherein the formula indicates a majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1 at% to about 50 at%.
8. The integrated assembly of claim 7, wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
9. The integrated assembly of claim 1, wherein the first region of the insulating level layers comprises SiC, wherein the formula indicates a majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1 at% to about 50 at%.
10. The integrated assembly of claim 9, wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
11. The integrated assembly of claim 1, wherein the first region of the insulating level layer comprises SiNC, where formula indicates a majority rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1ppm to about 5 at%.
12. The integrated assembly of claim 1, wherein:
the conductive level comprises a conductive liner material along an outer perimeter of a conductive core material;
the composition of the conductive liner material is different from the conductive core material;
the terminal region comprises only the conductive liner material; and is
The non-terminal region includes both the conductive liner material and the conductive core material.
13. The integrated assembly of claim 12, wherein the terminal region is joined with the non-terminal region at a corner having an angle of about 90 °.
14. The integrated assembly of claim 12, wherein the terminal regions are substantially straight along a vertical direction.
15. The integrated assembly of claim 12, wherein the conductive liner material comprises a metal nitride.
16. The integrated assembly of claim 15, wherein the metal nitride comprises titanium nitride; and wherein the conductive core material is comprised of tungsten.
17. The integrated assembly of claim 1, wherein the non-terminal region is substantially vertically centered with respect to the terminal region along each of the conductive levels.
18. An integrated assembly, comprising:
a vertical stack of alternating insulating levels and conductive levels;
the conductive level layer having a terminal region and a non-terminal region in the vicinity of the terminal region; the terminal region is vertically thicker than the non-terminal region;
the conductive level comprises a conductive liner material along an outer perimeter of a conductive core material;
the composition of the conductive liner material is different from the conductive core material;
the terminal region comprises only the conductive liner material;
the non-terminal region includes both the conductive liner material and the conductive core material; the conductive liner material has a substantially uniform thickness along the non-terminal and terminal regions of the conductive levels;
the terminal region joined to the non-terminal region at a corner having an angle of about 90 °;
the non-terminal region is substantially vertically centered with respect to the terminal region along the conductive level;
channel material extending vertically through the stack;
a tunneling material adjacent to the channel material;
a charge storage material adjacent to the tunneling material;
a charge blocking material adjacent to the charge storage material; and
a high-k dielectric material between the charge blocking material and the terminal region of the conductive level.
19. The integrated assembly of claim 18, wherein the conductive liner material comprises titanium nitride; and is
Wherein the conductive core material is comprised of tungsten.
20. The integrated assembly of claim 18, wherein the terminal region of the conductive level has a first vertical thickness; wherein the non-terminal region of the conductive level layer has a second vertical thickness; and wherein the first vertical thickness is greater than the second vertical thickness by an amount in a range from about 1nm to about 20 nm.
21. The integrated assembly of claim 18, wherein the amount ranges from about 1nm to about 8 nm.
22. The integrated assembly of claim 18, wherein the second vertical thickness is in a range from about 15nm to about 40 nm.
23. The integrated assembly of claim 18, wherein the insulating levels have a first region vertically between the terminal regions of adjacent conductive levels and have a second region vertically between the non-terminal regions of the adjacent conductive levels; and wherein a void extends across the first and second regions.
24. The integrated assembly of claim 18, wherein the insulating levels have a first region vertically between the terminal regions of adjacent conductive levels and have a second region vertically between the non-terminal regions of the adjacent conductive levels; and wherein the composition of the first region is different from the second region.
25. The integrated assembly of claim 24, wherein the first region comprises one or more of SiC, SiOC, and SiNC, wherein formula indicates a majority component rather than a specific stoichiometry.
26. The integrated assembly of claim 18, wherein:
the high-k dielectric material is disposed in a first segment of the vertical stack;
the charge blocking material is disposed in a second section of the vertical stack; and is
The charge storage material is disposed in a third segment of the vertical stack.
27. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material;
forming an opening extending through the stack, the opening having a peripheral sidewall;
forming a liner along the peripheral sidewall; the liner is a carbonaceous material; the liner has a first region along the first level and a second region along the second level;
forming a dielectric barrier material adjacent to the liner;
forming a charge blocking material adjacent to the dielectric blocking material;
forming a charge storage material adjacent to the charge blocking material;
forming a tunneling material adjacent to the charge storage material;
forming a channel material adjacent to the tunneling material;
removing the second material to leave voids between the first levels and expose the second regions of the liner;
oxidizing the exposed second region of the liner to form an oxidized section of the liner; the oxidized section of the liner is a first section of the liner; the first sections of the liner vertically alternate with second sections of the liner;
removing the first section of the liner to expose a region of the dielectric barrier material; and
forming a conductive level within the void; the conductive level has a front end with a front surface along and directly against an exposed region of the dielectric barrier material.
28. The method of claim 27, wherein the first section of the liner has a terminal portion that extends beyond the second level to follow the first level.
29. The method of claim 28, wherein the terminal portion extends beyond the second level by at least about 1 nm.
30. The method of claim 27, wherein the carbonaceous material comprises SiOC, wherein the formula indicates the major constituent rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
31. The method of claim 27, wherein the carbon-containing material comprises SiC, wherein the formula indicates the major constituent rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
32. The method of claim 27 wherein the carbon-containing material comprises SiCN, wherein the formula indicates a majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in the range of about 1ppm to about 5 at%.
33. The method of claim 27, wherein the first material is silicon dioxide and the second material is silicon nitride.
34. The method of claim 27, wherein the void is a first void, and further comprising removing the first material to leave a second void.
35. The method of claim 27, wherein the exposed region of the dielectric barrier material is a first region of the dielectric barrier material; wherein the void is a first void; and the method further comprises:
removing the first material to leave a second void exposing the second section of the liner;
oxidizing the exposed second section of the liner;
removing the oxidized second segment of the liner to expose a second region of the dielectric barrier material;
lining the second void with a sacrificial material to narrow the second void;
extending a narrowed second void through the second region of the dielectric barrier material, through the charge blocking material, and through the charge storage material; and
removing the sacrificial material.
36. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material;
forming an opening extending through the stack, the opening having a peripheral sidewall;
forming a dielectric barrier material adjacent the peripheral sidewall;
forming a charge blocking material adjacent to the dielectric blocking material;
forming a charge storage material adjacent to the charge blocking material;
forming a tunneling material adjacent to the charge storage material;
forming a channel material adjacent to the tunneling material;
removing the second material to leave first voids between the first levels;
forming a conductive level within the first void; the conductive level has a front end with a front surface; the front surface is along and directly against the dielectric barrier material;
removing the first material to leave a second void;
lining the second void with a sacrificial material to narrow the second void;
extending the narrowed second void through the dielectric barrier material, the charge blocking material, and the charge storage material; and
removing the sacrificial material.
37. The method of claim 36, further comprising forming a liner material along the peripheral sidewall, and wherein the dielectric barrier material is formed along the liner material.
38. The method of claim 37, wherein the liner material comprises a metal.
39. The method of claim 38, wherein the metal comprises one or both of tungsten and ruthenium.
40. The method of claim 37, wherein the liner material comprises carbon.
41. The method of claim 40, wherein the liner material comprises a combination of the carbon and one or more of silicon, oxygen, and nitrogen.
42. The method of claim 41, wherein the liner material comprises SiOC, wherein the formula indicates the majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
43. The method of claim 41, wherein the liner material comprises SiC, wherein the formula indicates the majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 4 at% to about 20 at%.
44. The method of claim 41 wherein the liner material comprises SiCN, wherein the formula indicates the majority component rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1ppm to about 5 at%.
Technical Field
An integrated assembly (e.g., an integrated NAND memory). A method of forming an integrated assembly.
Background
The memory provides data storage for the electronic system. Flash memory is a type of memory that has found widespread use in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, computers and other devices are increasingly utilizing flash memory in solid state drives in place of traditional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support standardized new communication protocols and provides the ability to remotely upgrade devices to enhance features.
NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.
Before describing NAND in detail, it may be helpful to describe more generally the relationship of memory arrays within an integrated arrangement. FIG. 1 shows a block diagram of a prior art device 1000, including a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, as well as an access line 1004 (e.g., a word line for conducting signals WL0 through WLm) and a first data line 1006 (e.g., a bit line for conducting signals BL0 through BLn). Access line 1004 and first data line 1006 may be used to transfer information to and from memory cells 1003. Row decoder 1007 and column decoder 1008 decode address signals a0 through AX on address lines 1009 to determine which of memory cells 1003 to access. Sense amplifier circuit 1015 is used to determine the value of the information read from memory cell 1003. I/O circuitry 1017 transfers values of information between memory array 1002 and input/output (I/O) lines 1005. Signals DQ0 through DQN on I/O line 1005 may represent values of information read from memory cells 1003 or to be written into memory cells 1003. Other devices may communicate with device 1000 through I/O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 is used to control memory operations to be performed on memory cells 1003 and uses signals on control lines 1020. Device 1000 may receive a supply voltage signal Vcc on a first supply line 1030 and a supply voltage signal Vss on a second supply line 1032. The device 1000 includes a selection circuit 1040 and an input/output (I/O) circuit 1017. Selection circuit 1040 may reply to signals CSEL 1-CSELn via I/O circuit 1017 to select signals on first data line 1006 and second data line 1013 that may represent values of information to be read from memory cell 1003 or programmed into memory cell 1003. Column decoder 1008 may selectively activate the CSEL 1-CSELn signals based on the A0-AX address signals on address lines 1009. During read and program operations, the selection circuitry 1040 may select signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I/O circuitry 1017.
The memory array 1002 of FIG. 1 can be a NAND memory array, and FIG. 2 shows a schematic of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of FIG. 1. The device 200 includes multiple strings of charge storage devices. In the first direction (Z-Z'), each string of charge storage devices may include, for example, 32 charge storage devices stacked on top of each other, where each charge storage device corresponds to, for example, one of 32 layers (e.g., Tier0 through Tier 31). The charge storage devices of a respective string may share a common channel region, such as that formed in a respective pillar of semiconductor material (e.g., polysilicon) around which the string of charge storage devices is formed. In the second direction (X-X'), each of the plurality of strings, e.g., sixteen first groups, may include, e.g., eight strings sharing a plurality (e.g., 32) of access lines (i.e., "global Control Gate (CG) lines," also referred to as word lines WL). Each access line may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and thus corresponding to the same layer) may be logically grouped into, for example, two pages, e.g., P0/P32, P1/P33, P2/P34, and so on. In a third direction (Y-Y'), each of the plurality of strings, e.g., eight second groups, may include sixteen strings coupled by a corresponding one of eight data lines. The size of a memory block may include 1,024 pages for a total of approximately 16MB (e.g., 16WL x 32 layer x2 bits 1,024 pages/block, block size 1,024 pages x16 KB/page 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and/or pages may be greater or less than those shown in FIG. 2.
Figure 3 shows a cross-sectional view of the memory block 300 of the 3D NAND memory device 200 of figure 2 in the X-X' direction,fifteen strings of charge storage devices in one of the sixteen first string groups described with respect to fig. 2 are included. The multi-string memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columnsIAnd the piece columnjAnd a jigsaw puzzle columnKWhere each subset (e.g., tile column) comprises a "partial block" of memory block 300. A global drain side Select Gate (SGD) line 340 may be coupled to the SGDs of the plurality of strings. For example, the global SGD line 340 may be coupled to a plurality (e.g., three) of sub-SGD lines 342, 344, 346 via a corresponding one of a plurality (e.g., three) of sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., a tile column). Each of the sub-SGD drivers 332, 334, 336 may couple or disconnect SGDs of strings of a corresponding partial block (e.g., a tile column) in parallel independently of SGDs of other partial blocks. A global source side Select Gate (SGS) line 360 may be coupled to the SGS of the plurality of strings. For example, global SGS line 360 may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a respective subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 may couple or disconnect SGSs of strings of a corresponding partial block (e.g., a tile column) in parallel independently of SGSs of other partial blocks. A global access line (e.g., a global CG line) 350 may couple charge storage devices corresponding to respective layers of each of the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers may couple or decouple the charge storage devices corresponding to the respective partial block and/or layer in parallel independently of the charge storage devices of the other partial blocks and/or other layers. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and respective layers may comprise "partial layers" (e.g., a single "tile") of the charge storage devices. Strings corresponding to respective subsets (e.g., partial blocks) may be coupled to respective ones of sub-sources 372, 374, and 376 (e.g., "tile sources"), with each sub-source coupled to a respective power supply.
Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG. 4.
The memory array 200 includes word lines 2021To 202NAnd bit line 2281To 228M。
The memory array 200 also includes NAND strings 2061To 206M. Each NAND string includes a charge storage transistor 2081To 208N. The charge storage transistor may use a floating gate material (e.g., polysilicon) to store charge, and may also use a charge trapping material (e.g., silicon nitride, metal nanodots, etc.) to store charge.
The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistors 208 of each NAND string 206 are connected in source-drain series between a source select device (e.g., source-side select gate SGS)210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of a string 206 and a source select line 214, while each drain select device 212 is located at the intersection of a string 206 and a drain select line 215. The selection devices 210 and 212 may be any suitable access device and are generally illustrated by the blocks in FIG. 4.
The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source select device 2101Is connected to the corresponding NAND string 2061Charge storage transistor 2081Of the substrate. The source select device 210 is connected to a source select line 214.
The drain of each drain select device 212 is connected to a bit line (i.e., digit line) 228 at a drain contact. For example, the drain select device 2121Is connected to a bit line 2281. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the drain select device 2121Is connected to the corresponding NAND string 2061Charge storage crystal ofBody tube 208NOf the substrate.
Charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 has its control gate 236 coupled to the word line 202. A column of charge storage transistors 208 are those transistors within a NAND string 206 that are coupled to a given bit line 228. A row of charge storage transistors 208 are those transistors commonly coupled to a given word line 202.
It is desirable to develop improved NAND architectures and improved methods for fabricating NAND architectures.
Disclosure of Invention
In one aspect, the present disclosure relates to an integrated assembly comprising: a vertical stack of alternating insulating levels and conductive levels; the conductive level layer having a terminal region and a non-terminal region in the vicinity of the terminal region; the terminal region is vertically thicker than the non-terminal region; channel material extending vertically through the stack; a tunneling material adjacent to the channel material; a charge storage material adjacent to the tunneling material; a high-k dielectric material between the charge storage material and the terminal region of the conductive level layer; the insulating levels having a first region vertically between the terminal regions of adjacent conductive levels and having a second region vertically between the non-terminal regions of the adjacent conductive levels; and the first region of the insulating level comprises carbon.
In another aspect, the present disclosure relates to an integrated assembly comprising: a vertical stack of alternating insulating levels and conductive levels; the conductive level layer having a terminal region and a non-terminal region in the vicinity of the terminal region; the terminal region is vertically thicker than the non-terminal region; the conductive level comprises a conductive liner material along an outer perimeter of a conductive core material; the composition of the conductive liner material is different from the conductive core material; the terminal region comprises only the conductive liner material; the non-terminal region includes both the conductive liner material and the conductive core material; the conductive liner material has a substantially uniform thickness along the non-terminal and terminal regions of the conductive levels; the terminal region joined to the non-terminal region at a corner having an angle of about 90 °; the non-terminal region is substantially vertically centered with respect to the terminal region along the conductive level; channel material extending vertically through the stack; a tunneling material adjacent to the channel material; a charge storage material adjacent to the tunneling material; a charge blocking material adjacent to the charge storage material; and a high-k dielectric material between the charge blocking material and the terminal region of the conductive level.
In another aspect, the present disclosure relates to a method of forming an integrated assembly, comprising: forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material; forming an opening extending through the stack, the opening having a peripheral sidewall; forming a liner along the peripheral sidewall; the liner is a carbonaceous material; the liner has a first region along the first level and a second region along the second level; forming a dielectric barrier material adjacent to the liner; forming a charge blocking material adjacent to the dielectric blocking material; forming a charge storage material adjacent to the charge blocking material; forming a tunneling material adjacent to the charge storage material; forming a channel material adjacent to the tunneling material; removing the second material to leave voids between the first levels and expose the second regions of the liner; oxidizing the exposed second region of the liner to form an oxidized section of the liner; the oxidized section of the liner is a first section of the liner; the first sections of the liner vertically alternate with second sections of the liner; removing the first section of the liner to expose a region of the dielectric barrier material; and forming a conductive level within the void; the conductive level has a front end with a front surface along and directly against an exposed region of the dielectric barrier material.
In yet another aspect, the present disclosure relates to a method of forming an integrated assembly, comprising: forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material; forming an opening extending through the stack, the opening having a peripheral sidewall; forming a dielectric barrier material adjacent the peripheral sidewall; forming a charge blocking material adjacent to the dielectric blocking material; forming a charge storage material adjacent to the charge blocking material; forming a tunneling material adjacent to the charge storage material; forming a channel material adjacent to the tunneling material; removing the second material to leave first voids between the first levels; forming a conductive level within the first void; the conductive level has a front end with a front surface; the front surface is along and directly against the dielectric barrier material; removing the first material to leave a second void; lining the second void with a sacrificial material to narrow the second void; extending the narrowed second void through the dielectric barrier material, the charge blocking material, and the charge storage material; and removing the sacrificial material.
Drawings
FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.
FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.
FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the X-X' direction.
FIG. 4 is a schematic of a prior art NAND memory array.
Fig. 5 and 6 are schematic cross-sectional side views of the area of an integrated assembly shown at example sequential process stages of an example method for forming an example NAND memory array.
Fig. 6A is a diagrammatic top view of a portion of the integrated assembly of fig. 6.
Figures 7-9 are schematic cross-sectional side views of the regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 7 may follow the process stage of fig. 6.
FIG. 9A is a top down diagrammatic view of a portion of the integrated assembly of FIG. 9.
10-14 are schematic cross-sectional side views of the regions of the integrated assembly of FIG. 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 10 may follow the process stage of fig. 9.
Fig. 14A is a schematic cross-sectional side view of the region of the integrated assembly of fig. 5 shown at an example continuous process stage, which may follow the process stage of fig. 14.
FIG. 15 is a schematic cross-sectional side view of the region of the integrated assembly of FIG. 5 shown at an example continuous process stage that may follow the process stage of FIG. 14
Fig. 15A is a schematic cross-sectional side view of the region of the integrated assembly of fig. 5 shown at an example continuous process stage, which may follow the process stage of fig. 15.
Fig. 16 is a schematic cross-sectional side view of the region of the integrated assembly of fig. 5 shown at an example continuous process stage, which may follow the process stage of fig. 15.
Fig. 16A is a schematic cross-sectional side view of the region of the integrated assembly of fig. 5 shown at an example continuous process stage, which may follow the process stage of fig. 16.
Figures 17-20 are schematic cross-sectional side views of the regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 17 may follow the process stage of fig. 16.
Figures 21-27 are schematic cross-sectional side views of the regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 21 may follow the process stage of fig. 10.
Figures 28-35 are schematic cross-sectional side views of the regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 28 may follow the process stage of fig. 6.
Figures 36-40 are schematic cross-sectional side views of the regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 36 may follow the process stage of fig. 31.
Detailed Description
Some embodiments include an integrated assembly having alternating conductive and insulative levels; and having a carbonaceous material in the region of the insulating level. Some embodiments include methods of forming an integrated assembly. The methods can use an etch stop material (e.g., a carbon-containing material, a metal-containing material, etc.) to protect the dielectric barrier material during removal of material adjacent to the dielectric material. Alternatively, the method may omit the etch stop material and may alternatively use etch conditions that selectively remove one or more materials relative to the dielectric barrier material.
Operation of a NAND memory cell involves the movement of charge between the channel material and the charge storage material. For example, programming of a NAND memory cell can include moving charge (i.e., electrons) from the channel material into the charge storage material, then storing the charge within the charge storage material. Erasing of the NAND memory cell can include moving holes into the charge storage material to recombine with electrons stored in the charge storage material and thereby release charge from the charge storage material. The charge storage material may include a charge trapping material (e.g., silicon nitride, metal dots, etc.). A problem with conventional NAND may be that the charge trapping material extends across multiple memory cells of the memory array, which may result in charge migration from one memory cell to another. Charge migration can cause data retention problems. Some embodiments include NAND architectures with breaks in the charge trapping material in the regions between memory cells; and such rupture may advantageously impede charge migration between memory cells.
Example embodiments are described with reference to fig. 5-40.
Referring to fig. 5, a construction (integrated assembly, integrated structure) 10 includes a vertical stack 12 of alternating first and second levels 14, 16. The first level 14 includes a first material 60 and the second level 16 includes a second material 62. The first and second materials may comprise any suitable composition and have compositions that are different from one another. In some embodiments, first material 60 may comprise, consist essentially of, or consist of silicon dioxide; and second material 62 may comprise, consist essentially of, or consist of silicon nitride. Levels 14 and 16 may have any suitable thickness; and may have the same thickness as each other, or may have different thicknesses from each other. In some embodiments, levels 14 and 16 may have vertical thicknesses in the range of about 10 nanometers (nm) to about 400 nm. In some embodiments, levels 14 and 16 may have a vertical thickness in the range of about 10nm to about 50 nm. In some embodiments, the first level 14/second level 16 may have a vertical thickness in a range of about 15nm to about 40nm, in a range of about 15nm to about 20nm, and so on.
The stack 12 is shown supported on a substrate 18 (i.e., formed over the substrate 18). Substrate 18 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist entirely of monocrystalline silicon. The base 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, base 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusing materials, insulator materials, and the like.
A gap is provided between stack 12 and substrate 18 to indicate that other components and materials may be provided between stack 12 and substrate 18. Such other components and materials may include additional stack levels, source line levels, source side Select Gates (SGS), and so forth.
Referring to fig. 6, an opening 64 is formed that extends through the stack 12. The opening 64 has sidewalls 65 that extend along the first material 60 and the second material 62.
Fig. 6A is a top view of one level 14 of the area of the assembly 10 at the process stage of fig. 6, showing that the opening 64 may have a closed shape (circular, oval, square or other polygonal, etc.) when viewed from above. In the illustrated embodiment, the opening 64 is circular when viewed from above. The sidewall 65 along the cross-section of fig. 6 is part of a continuous sidewall 65, as shown by the top view of fig. 6A. The sidewall 65 may be referred to as a peripheral sidewall of the opening, or as a peripheral sidewall surface of the opening. The terms "peripheral sidewall" and "peripheral sidewall surface" may be used interchangeably. The use of one term in some instances and another term in other instances can be a matter of providing language variation within the present disclosure to simplify antecedent basis in the claims that follow.
Opening 64 may represent a large number of substantially identical openings formed at the process stage of fig. 6 and 6A and used to fabricate NAND memory cells of a NAND memory array. The term "substantially the same" means the same within reasonable tolerances for manufacturing and measurement.
Referring to fig. 7, the liner 20 is formed along the peripheral sidewall 65. The liner comprises liner material 22. Liner material 22 may serve as an etch stop in subsequent processing and may comprise any suitable composition.
In some embodiments, the liner material 22 may be a carbonaceous material. For example, the liner material 22 may comprise, consist essentially of, or consist of a combination of carbon and one or more of silicon, oxygen, and nitrogen.
In some embodiments, the liner material 22 may include, consist essentially of, or consist of SiOC, where the formula indicates the major constituent rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1 atomic percent (at%) to about 50 at%. In some embodiments, carbon may be present in the SiOC at a concentration in the range of about 4 at% to about 20 at%.
In some embodiments, liner material 22 may comprise, consist essentially of, or consist of SiC, where the formula indicates the major constituent rather than a specific stoichiometry; and wherein the carbon is present at a concentration in a range of about 1 atomic percent (at%) to about 50 at%. In some embodiments, carbon may be present in the SiC at a concentration in a range of about 4 at% to about 20 at%.
In some embodiments, liner material 22 may comprise, consist essentially of, or consist of SiNC, where the formula indicates the major constituent rather than a specific stoichiometry; and wherein the carbon is present at a concentration in the range of about one part per million (1ppm) to about 5 at%.
In some embodiments, the liner material 22 may include, consist essentially of, or consist of one or more metals (e.g., one or both of tungsten and ruthenium).
The liner may include any suitable horizontal thickness T. In some embodiments, such horizontal thicknesses may range from about 1nm to about 12 nm; in the range of about 2nm to about 4 nm; and so on.
Although the liner 20 is shown as having a single homogeneous composition, in other embodiments (not shown), the liner 20 may include a laminate having two or more different compositions.
The liner 20 may be considered to have a first region 24 along the first level 14 and a second region 26 along the second level 16.
Referring to fig. 8, a high-k dielectric material (dielectric barrier material) 28 is formed along the liner 20 (adjacent to the liner 20). The dielectric barrier material 28 can be considered to be adjacent the sidewalls 65 of the opening 64, but in the illustrated embodiment it is spaced from the sidewalls by the liner 20.
The term "high-k" means a dielectric constant that is greater than the dielectric constant of silicon dioxide. In some embodiments, the high-k dielectric material 28 may comprise, consist essentially of, or consist of: one or more of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO); where the chemical formula indicates the major constituent rather than a specific stoichiometry.
The high-k dielectric material 28 has a substantially uniform thickness, where the term "substantially uniform" means uniform within reasonable tolerances in fabrication and measurement. The high-k dielectric material 28 may be formed to any suitable thickness; and in some embodiments may be formed to a thickness in the range of about 1nm to about 5 nm.
Referring to figures 9 and 9A (where figure 9A is a top view of one level 14 of figure 9), charge blocking material 34 is formed along dielectric blocking material 28. Charge blocking material 34 may include any suitable composition; and in some embodiments may include silicon oxynitride (SiON) and silicon dioxide (SiO)2) One or two of silicon oxynitride (SiON) and silicon dioxide (SiO)2) Or one or two of silicon oxynitride (SiON) and silicon dioxide (SiO)2) One or two of them.
A charge storage material 38 is formed adjacent to the charge blocking material 34. The charge storage material 38 may comprise any suitable composition. In some embodiments, the charge storage material 38 may comprise a charge trapping material; such as silicon nitride, silicon oxynitride, conductive nanodots, and the like. For example, in some embodiments, the charge storage material 38 may comprise, consist essentially of, or consist of silicon nitride. In an alternative embodiment, the charge storage material 38 may be configured to include a floating gate material (e.g., polysilicon).
In the embodiment shown in fig. 9, the charge storage material 38 has a planar configuration. The term "flat configuration" means that material 38 has a substantially continuous thickness and extends substantially vertically straight, rather than undulating.
A gate dielectric material (i.e., tunneling material, charge transport material) 42 is formed adjacent the charge storage material 38. Gate dielectric material 42 may comprise any suitable composition. In some embodiments, the gate dielectric material 42 may comprise, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and the like. The gate dielectric material 42 may be band gap engineered to achieve desired electrical characteristics; and thus may comprise a combination of two or more different materials.
Channel material 44 is formed adjacent to gate dielectric material 42 and extends vertically along stack 12. Channel material 44 comprises a semiconductor material; and may comprise any suitable composition or combination of compositions. For example, the channel material 44 may include one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, and the like; wherein the term III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table (groups III and V are old nomenclature and are now referred to as groups 13 and 15). In some embodiments, the channel material 44 may comprise, consist essentially of, or consist of silicon.
Insulative material 36 is formed adjacent channel material 44 and fills the remainder of opening 64 (fig. 8). Insulating material 36 may include any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.
In the embodiment shown in fig. 9 and 9A, channel material 44 is configured as a loop around insulative material 36. Such a configuration of channel material may be considered to include a hollow channel configuration in which the insulating material 36 is provided within a "hollow body" in a toroidal channel configuration. In other embodiments (not shown), the channel material may be configured in a solid pillar configuration.
Referring to fig. 10, the second material 62 (fig. 9) is removed, leaving voids 30 along the second levels 16 (i.e., between the first levels 14). The voids 30 may be referred to as first voids to distinguish them from other voids formed at a later stage of the process.
Voids 30 may be formed using any suitable process that selectively removes material 62 (fig. 9) relative to materials 60 and 22. In some embodiments, such processes may use hot phosphoric acid.
The second region 26 of the liner 20 is exposed through the void 30.
Referring to fig. 11, the exposed second region 26 (fig. 10) of the liner 20 is oxidized to form an oxidized segment 46. In the illustrated embodiment, stippling is used to help the reader identify the oxide section 46. The oxidation zone 46 may be referred to as a first stage. Such first sections 46 vertically alternate with non-oxidized second sections 48 of the liner 20. In the illustrated embodiment, the first segment is oxidized to extend beyond the second region 26 of the liner (fig. 10, where such first region is a region along the second level 16) to include the terminal portion 50 along the first level 14. The terminal portions 50 may be considered to extend beyond the second level by a distance D. In some embodiments, such distance D may be 0 (i.e., terminal portion 50 may not be present). In other embodiments, the distance D may be greater than 0, greater than 0.5nm, greater than 1nm, greater than 2nm, and so forth. In some example embodiments, distance D may be in the range of about 0 to about 10nm, in the range of about 0 to about 4nm, and so forth.
The oxidation zone (oxidation stage, first stage) 46 may be formed under any suitable conditions; involving, for example, exposure to O2、H2O2、O3And so forth.
In some embodiments, liner material 22 comprises a carbonaceous material, and oxidized region 46 comprises an oxidized form of the carbonaceous material. Such oxidation formation may have the physical characteristics of a powdered material or fluff.
Referring to fig. 12, the oxidation section 46 (fig. 11) is removed. Such removal may be accomplished using any suitable process. For example, if the oxidation stage 46 includes silicon, carbon, and oxygen, removal of such stage may use an etchant that includes hydrofluoric acid. The removal of the oxide segment 46 exposes the surface 29 of the dielectric barrier material 28.
It should be noted that in some embodiments, the oxidation of fig. 11 may be omitted and the exposed segment 26 of liner material 22 of fig. 10 may simply be removed with one or more appropriate etches to form a configuration similar to that of fig. 12. For example, in some embodiments, the liner material 22 may comprise one or more metals, and these metals may be removed using an appropriate etch without first being oxidized.
Referring to fig. 13, conductive regions 32 are formed within voids 30 (fig. 10).
The conductive region 32 may include two or more conductive materials; and in the illustrated embodiment, includes a pair of conductive materials 52 and 54. Conductive materials 52 and 54 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The compositions of the conductive materials 52 and 54 are different from each other.
Material 52 may be referred to as a conductive core material and material 54 may be referred to as a conductive liner material. The conductive liner material 54 is along the outer perimeter of the conductive core material 52.
In some embodiments, the conductive core material 52 may comprise one or more metals (e.g., may comprise tungsten) and the conductive liner material 54 may comprise one or more metal nitrides (e.g., may comprise titanium nitride).
In the illustrated embodiment, the high-k dielectric material 28 is directly against the conductive liner material 54.
Level 16 may be considered a conductive level at the process stage of fig. 13, where such a conductive level comprises a conductive region 32. At the process stage of fig. 13, conductive levels 16 alternate with insulating levels 14 in the vertical stack 12.
The conductive level 16 has a terminal area 56 facing the dielectric barrier material 28 and has a non-terminal area 58 near the terminal area 56. In the illustrated embodiment, the terminal areas 56 include only the conductive liner material 54, and the non-terminal areas 58 include both the conductive liner material 54 and the conductive core material 52. The conductive liner material 54 has a substantially uniform thickness along the non-terminal and terminal regions (where the term "substantially uniform thickness" means a uniform thickness within reasonable tolerances for manufacturing and measurement).
Conductive level 16 may be considered to have a front surface 57 along terminal region 56. Such front surface extends along the dielectric barrier material 28 and directly against the dielectric barrier material 28. In some embodiments, the dielectric barrier material 28 may be considered to comprise an exposed surface 29 at the process stage of fig. 12, and the front surface 57 may be considered to be directly against such surface 29 of the dielectric barrier material 28.
Terminal region 56 joins with non-terminal region 58 at corner 66. In the embodiment shown, such corners have an angle of about 90 °. The term "about 90" means 90 within reasonable tolerances for manufacturing and measurement.
The terminal regions 56 are shown as being substantially straight along the vertical direction, and in particular as being vertically straight along the dielectric barrier material 28. This may be advantageous because it may improve the coupling of the terminal region 56 with the charge storage material 38 compared to conventional arrangements in which terminal regions of similar conductive levels may be curved rather than vertically straight.
The terminal areas 56 have a first vertical dimension D1The non-terminal region 58 has a second vertical dimension D2. First vertical dimension D1May be equal to or greater than the second vertical dimension D2(i.e., terminal regions 56 may be vertically thicker than non-terminal regions 58). In some embodiments, the first vertical thickness D1Can be compared with the second vertical thickness D2An amount in the range of about 1nm to about 20 nm; amounts in the range of about 1nm to about 8nm, and the like.
In the illustrated embodiment, the non-terminal region 58 is substantially vertically centered along each of the conductive levels 16 relative to the terminal region 56 (where the term "substantially vertically centered" means vertically centered within reasonable tolerances of manufacture and measurement).
The insulating levels 14 may be considered to have a first region 68 between the terminal regions 56 of vertically adjacent conductive levels 16 and a second region 70 between the non-terminal regions 58 of vertically adjacent conductive levels. In the embodiment shown in fig. 13, the first region 68 and the second region 70 comprise different compositions. Specifically, first region 68 includes liner material 22 and second region 70 includes insulating material 60. In some embodiments, the insulating material 60 may comprise, consist essentially of, or consist of silicon dioxide; and the liner material 22 may comprise carbon (e.g., may comprise a combination of carbon and one or more of silicon, oxygen, and nitrogen).
The conductive levels 16 may be considered levels of memory cells (also referred to herein as word line levels) of a NAND configuration. The NAND configuration includes strings of memory cells (i.e., NAND strings), where the number of memory cells in a string is determined by the number of vertically stacked levels 16. A NAND string can include any suitable number of levels of memory cells. For example, a NAND string may have 8 levels of memory cells, 16 levels of memory cells, 32 levels of memory cells, 64 levels of memory cells, 512 levels of memory cells, 1024 levels of memory cells, etc. The vertical stacks 12 are indicated as extending vertically beyond the area shown, showing that there may be more vertical stack levels than those specifically shown in the drawing of fig. 13.
The NAND memory cell 40 includes dielectric barrier material 28, charge blocking material 34, charge storage material 38, gate dielectric material 42, and channel material 44. The illustrated NAND memory cell 40 forms part of a vertically extending string of memory cells. Such strings may represent a large number of substantially identical NAND strings formed during the fabrication of a NAND memory array (where the term "substantially identical" means identical within reasonable tolerances of fabrication and measurement).
Each of the NAND memory cells 40 includes a control gate region 72 within the conductive level 16. The control gate region 72 includes a control gate similar to the control gates described above with reference to fig. 1-4. The conductive level 16 includes a region 74 adjacent (near) the control gate region 72. The area 74 may be referred to as a routing area or a wordline area. The control gate region 72 includes the terminal region 56 of the conductive level 16 and the routing region 74 includes the non-terminal region 58 of the conductive level 16.
The configuration of FIG. 13 may be the final structure of the memory configuration (e.g., configured as an assembly including NAND memory). Alternatively, the configuration of fig. 13 may be subjected to further processing to form a memory configuration. For example, fig. 14 shows a stage of the process that may follow that of fig. 13. First material 60 (fig. 13) is removed to form second voids 76 along levels 14 (i.e., leaving second voids 76). The formation of the second void 76 exposes the remaining segment 48 of the liner material 22.
Fig. 14A shows a stage of the process that may follow that of fig. 14. In particular, the ends of voids 76 may be capped with an electrostatic insulating material 78 (e.g., silicon dioxide) to form a final assembly (e.g., a NAND memory assembly) comprising alternating insulating levels 14 and conductive levels 16; wherein insulating level 14 includes voids 76, cap material 78, and remaining segments 48 of liner material 22. The voids 76 are between the non-terminal regions 58 of vertically adjacent conductive levels 16 and the liner material 22 is between the terminal regions 56 of vertically adjacent conductive levels 16. In other words, the insulating level 14 may be considered to include the liner material 22 within the first region 68 and to include the void 76 within the second region 70.
Fig. 15 shows another stage of the process which may follow that of fig. 14. The segments 48 of liner material 22 are oxidized using a process similar to that described above with reference to fig. 11. The oxidized section 48 may be referred to as an oxidized second section of liner material.
Fig. 15A shows a stage of the process that may follow that of fig. 15. In particular, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly). The oxide regions 48 are between vertically adjacent terminal regions 56 of the conductive levels 16.
Fig. 16 shows another stage of the process which may follow that of fig. 15. The oxidized segments 48 (figure 15) are removed to expose the segments 31 of the dielectric barrier material 28. In some embodiments, the exposed section 31 may be referred to as a second region of dielectric barrier material so as to be distinguished from the first region 29 of dielectric barrier material exposed at the process stage of figure 12. The oxidation stage 48 may be removed using a process similar to that described above with reference to fig. 12.
Fig. 16A shows a stage of the process that may follow that of fig. 16. In particular, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly). The gap 76 extends between the terminal regions 56 of vertically adjacent conductive levels 16 and between the non-terminal regions 58 of vertically adjacent conductive levels 16.
Fig. 17 shows a stage of the process which may follow that of fig. 16. Second void 76 is lined with sacrificial material 80 to narrow second void 76. The sacrificial material 80 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon nitride. It is contemplated that the sacrificial material 80 may be configured as a strip 82.
Referring to fig. 18, the narrowed second void 76 extends through the dielectric blocking material 28, the charge blocking material 34, and the charge storage material 38. The extended void 76 divides the dielectric barrier material 28 into vertically spaced first linear segments 84, the charge blocking material 34 into vertically spaced second linear segments 86, and the charge storage material 38 into vertically spaced third linear segments 88.
In the embodiment shown in FIG. 18, the segments 84, 86 and 88 have a substantially flat configuration. Also, the channel material 44 has a substantially planar configuration. A planar channel material may positively affect the string current compared to a non-planar configuration. Also, the flat section 88 of charge storage material may have a good charge distribution.
The embodiment of fig. 18 shows that the voids 76 extend through the materials 28, 34, and 38 and stop at the tunneling material 42. In other embodiments, the voids 76 may extend through the tunneling material.
Referring to fig. 19, the sacrificial material 80 (fig. 18) is removed.
Referring to fig. 20, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly). The gap 76 extends between the terminal regions 56 of vertically adjacent conductive levels 16 and between the non-terminal regions 58 of vertically adjacent conductive levels 16.
As discussed above, in some embodiments, the exposed section 26 of liner material 22 of fig. 10 may be removed directly using an appropriate etch, rather than oxidized according to the process of fig. 11. Fig. 21 shows a stage of the process that may follow that of fig. 10, and shows the exposed section 26 of liner material 22 (fig. 10) removed using one or more appropriate etches. In some embodiments, the liner material 22 may include one or more metals (e.g., one or both of tungsten and ruthenium), and the exposed segments 26 may be removed by selectively etching such metals relative to the dielectric barrier material 28 and the insulating material 60. If the etch removes one material faster than the other, then the etch is considered selective to the one material over the other; the etch may include, but is not limited to, an etch that is 100% selective to one material over another.
Referring to fig. 22, the assembly 10 is shown at a processing stage subsequent to that of fig. 21, and this assembly is similar to that described above with reference to fig. 13. Specifically, conductive materials 52 and 54 are formed within voids 30 (fig. 21).
The configuration of FIG. 22 may be the final structure of the memory configuration (e.g., configured as an assembly including NAND memory). Alternatively, the configuration of fig. 22 may be subjected to further processing to form a memory configuration. For example, fig. 23 shows a stage of the process that may follow that of fig. 22. Materials 60 and 22 have been removed from levels 14 by a suitable etch, leaving voids 76 along levels 14.
Referring to fig. 24, a sacrificial material 80 is formed within the voids 76 to narrow the voids using a process similar to that described above with reference to fig. 17.
Referring to fig. 25, the narrowed void 76 extends through the dielectric barrier material 28, the charge blocking material 34 and the charge storage material 38 using a process similar to that described above with reference to fig. 18.
Referring to fig. 26, sacrificial material 80 (fig. 25) is removed using a process similar to that described above with reference to fig. 19.
Referring to fig. 27, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly).
In some embodiments, the liner material 22 (fig. 9) may be omitted. For example, fig. 28 shows an assembly 10 similar to that of fig. 9, but without the liner material 22. The process stage of fig. 28 may follow the process stage of fig. 6.
Referring to fig. 29, the sacrificial material 62 (fig. 28) is removed, leaving voids 30 along the levels 16.
Referring to fig. 30, conductive materials 52 and 54 are formed within voids 30 (fig. 29).
The configuration of FIG. 30 may be the final structure of the memory configuration (e.g., configured as an assembly including NAND memory). Alternatively, the configuration of fig. 30 may be subjected to further processing to form a memory configuration. For example, fig. 31 shows a stage of the process that may follow that of fig. 30. Material 60 has been removed from levels 14 using a suitable etch, leaving voids 76 along levels 14.
Referring to fig. 32, a sacrificial material 80 is formed within the voids 76 to narrow the voids using a process similar to that described above with reference to fig. 17.
Referring to fig. 33, the narrowed voids 76 extend through the dielectric barrier material 28, the charge blocking material 34 and the charge storage material 38 using a process similar to that described above with reference to fig. 18.
Referring to fig. 34, sacrificial material 80 (fig. 33) is removed using a process similar to that described above with reference to fig. 19.
Referring to fig. 35, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly).
The process of figure 32 shows sacrificial material 80 formed within voids 76 prior to etching through dielectric barrier material 28. In other embodiments, the dielectric barrier material 28 may be etched prior to forming the sacrificial material 80 within the voids 76. For example, figure 36 shows a stage of processing that may follow that of figure 31, and shows the dielectric barrier material 28 etched to expose the surface 35 of the charge blocking material 34. In the embodiment shown, the etching of the dielectric barrier material recesses such material relative to the front face (front surface) 57 of the conductive levels 16, leaving cavities 90. In other embodiments, the dielectric barrier material may not be recessed relative to the front face 57, and thus the cavity 90 may not be formed.
Referring to fig. 37, a sacrificial material 80 is formed within the voids 76 to narrow the voids using a process similar to that described above with reference to fig. 17.
Referring to fig. 38, narrowed void 76 extends through charge blocking material 34 and charge storage material 38 using a process similar to that described above with reference to fig. 18.
Referring to fig. 39, sacrificial material 80 (fig. 38) is removed using a process similar to that described above with reference to fig. 19.
Referring to fig. 40, the ends of the voids 76 are capped with an electrostatically insulating material 78 by a process similar to that described above with reference to fig. 14A to form the final assembly (e.g., a NAND memory assembly).
In operation, the charge storage material 38 may be configured to store information in the memory cells 40 of the various embodiments described herein. The value of the information stored in the various memory cells (where the term "value" denotes one bit or multiple bits) may be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the memory cell. The amount of charge within each charge storage region may be controlled (e.g., increased or decreased) based at least in part on the value of the voltage applied to the associated gate 72 (with example gates 72 labeled in fig. 13) and/or based on the value of the voltage applied to channel material 44.
The tunneling material 42 forms a tunneling region of the memory cell 40. Such tunneling regions may be configured to enable a desired migration (e.g., transport) of charge (e.g., electrons) between the charge storage material 38 and the channel material 44. The tunneling region may be configured (i.e., engineered) to achieve a selected criterion, such as, but not limited to, an Equivalent Oxide Thickness (EOT). The EOT quantifies the electrical characteristics of the tunneling region (e.g., capacitance) in terms of representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that is required to have the same capacitance density as a given dielectric, but without regard to leakage current and reliability.
The charge blocking material 34 may provide a mechanism for preventing charge from flowing from the charge storage material 38 to the associated gate 72.
The dielectric barrier material (high-k material) 28 may be used to inhibit reverse tunneling of charge carriers from the gate 72 to the charge storage material 38. In some embodiments, the dielectric barrier material 28 may be considered to form a dielectric barrier region within the memory cell 40.
The assemblies and structures discussed above may be used within an integrated circuit (the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Electronic systems may be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lights, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and so forth.
Unless otherwise specified, the various materials, species, components, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.
The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used to provide a linguistic variation within the disclosure to simplify the premise foundation within the appended claims, rather than to indicate any significant chemical or electrical difference.
The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. In some cases one term and in other cases another term may be used to provide a linguistic variation within the disclosure to simplify the premise foundation within the appended claims.
The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims refer to any structure having a described relationship between various features, whether the structure is in a particular orientation in the figures or rotated relative to such orientation.
Unless otherwise indicated, the cross-sectional views of the accompanying figures show only features within the cross-sectional plane and not material behind the cross-sectional plane in order to simplify the drawings.
When a structure is referred to as being "on," "adjacent to," or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present. The terms "directly under", "directly above", and the like do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate upright alignment.
Structures (e.g., layers, materials, etc.) may be referred to as "vertically extending," to indicate that the structures generally extend upward from an underlying base (e.g., substrate). The vertically extending structures may or may not extend substantially orthogonally relative to the upper surface of the base.
Some embodiments include an integrated assembly having a vertical stack of alternating insulating and conductive levels. The conductive level has a terminal region and a non-terminal region in the vicinity of the terminal region. The terminal area is thicker than the non-terminal area in the vertical direction. The channel material extends vertically through the stack. A tunneling material is adjacent to the channel material. The charge storage material is adjacent to the tunneling material. The high-k dielectric material is between the charge storage material and the terminal region of the conductive level. The insulating levels have a first region vertically between the terminal regions of adjacent conductive levels and have a second region vertically between the non-terminal regions of adjacent conductive levels. The first region of the insulating level contains carbon.
Some embodiments include an integrated assembly comprising a vertical stack of alternating insulating and conductive levels. The conductive level has a terminal region and a non-terminal region in the vicinity of the terminal region. The terminal area is thicker than the non-terminal area in the vertical direction. The conductive level comprises a conductive liner material along an outer perimeter of the conductive core material. The composition of the conductive liner material is different from the conductive core material. The terminal area includes only the conductive liner material. The non-terminal region includes both the conductive liner material and the conductive core material. The conductive liner material has a substantially uniform thickness along the non-terminal and terminal regions of the conductive levels. The terminal region joins the non-terminal region at a corner having an angle of about 90 deg.. The non-terminal region is substantially vertically centered with respect to the terminal region along the conductive levels. The channel material extends vertically through the stack. A tunneling material is adjacent to the channel material. The charge storage material is adjacent to the tunneling material. The charge blocking material is adjacent to the charge storage material. The high-k dielectric material is between the charge blocking material and the terminal region of the conductive level.
Some embodiments include a method of forming an integrated assembly. Forming a vertical stack of alternating first and second levels. The first level includes a first material and the second level includes a second material. An opening is formed extending through the stack. The opening has a peripheral sidewall. A liner is formed along the peripheral sidewall. The lining is a carbonaceous material. The liner has a first region along a first level and a second region along a second level. A dielectric barrier material is formed adjacent to the liner. A charge blocking material is formed adjacent to the dielectric blocking material. A charge storage material is formed adjacent to the charge blocking material. A tunneling material is formed adjacent to the charge storage material. A channel material is formed adjacent to the tunneling material. The second material is removed to leave voids between the first levels and to expose a second region of the liner. The exposed second region of the liner is oxidized to form an oxidized section of the liner. The oxidized section of the liner is the first section of the liner. The first sections of the liner alternate vertically with the second sections of the liner. The first section of the liner is removed to expose a region of the dielectric barrier material. A conductive level is formed within the void. The conductive level has a front end with a front surface along and directly against an exposed region of the dielectric barrier material.
Some embodiments include a method of forming an integrated assembly. Forming a vertical stack of alternating first and second levels. The first level includes a first material and the second level includes a second material. An opening is formed extending through the stack. The opening has a peripheral sidewall. A dielectric barrier material is formed adjacent the peripheral sidewall. A charge blocking material is formed adjacent to the dielectric blocking material. A charge storage material is formed adjacent to the charge blocking material. A tunneling material is formed adjacent to the charge storage material. A channel material is formed adjacent to the tunneling material. The second material is removed to leave first voids between the first levels. A conductive level is formed within the first void. The conductive level has a front end with a front surface. The front surface is along and directly against the dielectric barrier material. The first material is removed to leave a second void. The second void is lined with a sacrificial material to narrow the second void. The narrowed second void extends through the dielectric barrier material, the charge blocking material, and the charge storage material. The sacrificial material is removed.
In accordance with the provisions, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are, therefore, to be accorded the full scope as literally set forth and appropriately interpreted in accordance with the doctrine of equivalents.