阅读说明：本技术 显示面板及其制备方法、显示装置 (Display panel, preparation method thereof and display device ) 是由 刘宁 程磊磊 张扬 黄腾飞 周斌 闫梁臣 于 2021-07-28 设计创作，主要内容包括：本发明实施例提供了一种显示面板及其制备方法、显示装置,涉及显示技术领域,用以降低像素驱动电路中的电容器对其所在的两个图案层的依赖。所述显示面板包括：衬底、第一图案层、电路层和第二图案层。第一图案层位于衬底上,包括第一导电图案；电路层位于第一图案层远离衬底的一侧,包括：薄膜晶体管、第二导电图案和第三导电图案,第三导电图案与薄膜晶体管的栅极和第二导电图案分别耦接,且第二导电图案比第三导电图案靠近衬底；第二图案层位于电路层远离衬底的一侧,包括第四导电图案。其中,第一导电图案和第二导电图案构成第一电容器的两个极板,第三导电图案和第四导电图案构成第二电容器的两个极板,第一导电图案和第四导电图案耦接。(The embodiment of the invention provides a display panel, a preparation method thereof and a display device, relates to the technical field of display, and aims to reduce the dependence of a capacitor in a pixel driving circuit on two pattern layers where the capacitor is located. The display panel includes: the circuit board comprises a substrate, a first pattern layer, a circuit layer and a second pattern layer. The first pattern layer is positioned on the substrate and comprises a first conductive pattern; the circuit layer is located the first pattern layer and keeps away from the side of substrate, includes: the thin film transistor, the second conductive pattern and the third conductive pattern, the third conductive pattern is coupled with the grid of the thin film transistor and the second conductive pattern respectively, and the second conductive pattern is closer to the substrate than the third conductive pattern; the second pattern layer is positioned on one side of the circuit layer far away from the substrate and comprises a fourth conductive pattern. Wherein the first conductive pattern and the second conductive pattern constitute two plates of a first capacitor, the third conductive pattern and the fourth conductive pattern constitute two plates of a second capacitor, and the first conductive pattern and the fourth conductive pattern are coupled.)

1. A display panel having a plurality of sub-pixel regions, the display panel comprising:

a substrate;

a first patterned layer on the substrate, comprising: a first conductive pattern in a subpixel region;

the circuit layer is positioned on one side, far away from the substrate, of the first pattern layer and comprises: a thin film transistor, a second conductive pattern and a third conductive pattern in the subpixel region, the third conductive pattern being coupled to a gate of the thin film transistor and the second conductive pattern, respectively, and the second conductive pattern being closer to the substrate than the third conductive pattern;

the second pattern layer is positioned on one side of the circuit layer far away from the substrate and comprises: a fourth conductive pattern at the subpixel region;

wherein the first and second conductive patterns constitute two plates of a first capacitor, the third and fourth conductive patterns constitute two plates of a second capacitor, and the first and fourth conductive patterns are coupled.

2. The display panel according to claim 1,

the second conductive pattern includes a first exposed portion, the first exposed portion is a portion of the second conductive pattern that is not covered by the third conductive pattern, and the first exposed portion and the fourth conductive pattern form two plates of a third capacitor.

3. The display panel according to claim 2,

the first conductive pattern, the second conductive pattern, and the third conductive pattern are all transparent to light.

4. The display panel according to claim 1,

the third conductive pattern includes a second exposed portion,

the second exposed portion and the first conductive pattern constitute two plates of a fourth capacitor.

5. The display panel according to any one of claims 1 to 4,

the circuit layer includes:

a third patterned layer comprising: the second conductive pattern and an active layer, a first electrode region portion and a second electrode region portion of the thin film transistor;

the fourth pattern layer is positioned on one side of the third pattern layer far away from the substrate and comprises: a gate electrode of the thin film transistor;

the fifth pattern layer is positioned on one side, far away from the substrate, of the fourth pattern layer and comprises: the third conductive pattern and a fifth conductive pattern at the subpixel region;

wherein the fifth conductive pattern is coupled with the fourth conductive pattern and the first conductive pattern, respectively.

6. The display panel according to claim 5,

the fifth conductive pattern is coupled with the second diode portion of the thin film transistor.

7. The display panel according to claim 1, further comprising:

the first insulating layer is positioned on one side, far away from the substrate, of the circuit layer;

and the second insulating layer is positioned between the first insulating layer and the second pattern layer.

8. The display panel according to claim 5, further comprising:

a metal pattern layer comprising: and the light shielding pattern is positioned in the sub-pixel area, and the orthographic projection of the light shielding pattern on the substrate covers the orthographic projection of the active layer of the thin film transistor on the substrate.

9. The display panel according to claim 8,

the light blocking pattern is in contact with the first conductive pattern.

10. The display panel according to claim 1,

the plurality of sub-pixel regions includes: the light-emitting color of the first subpixel region is different from that of the second subpixel region;

the opposite area between the two polar plates of the first capacitor in the first sub-pixel area is different from the opposite area between the two polar plates of the first capacitor in the second sub-pixel area;

and/or the presence of a gas in the gas,

the right facing area between the two polar plates of the second capacitor in the first sub-pixel area is different from the right facing area of the two polar plates of the second capacitor in the second sub-pixel area.

11. The display panel according to claim 10,

the shape and the size of the first conductive pattern in the first sub-pixel region are different from those of the first conductive pattern in the second sub-pixel region;

and/or the presence of a gas in the gas,

the shape and size of the second conductive pattern in the first subpixel region are different from those of the second conductive pattern in the second subpixel region.

12. The display panel according to claim 5,

the fifth pattern layer further includes: a power line coupled with the thin film transistor;

the fourth pattern layer further includes: an auxiliary line to which the power supply line is coupled at a plurality of connection positions.

13. A display device, comprising:

the display panel of any one of claims 1 to 12.

14. A method for manufacturing a display panel is characterized in that,

the display panel of any one of claims 1 to 12, the display panel having a plurality of sub-pixel regions;

the preparation method comprises the following steps:

forming a substrate;

forming a first pattern layer on the substrate, the first pattern layer comprising: a first conductive pattern in a subpixel region;

forming a circuit layer on a side of the first pattern layer away from the substrate, the circuit layer comprising: a thin film transistor, a second conductive pattern and a third conductive pattern in the subpixel region, the third conductive pattern being coupled to a gate of the thin film transistor and the second conductive pattern, respectively, and the second conductive pattern being closer to the substrate than the third conductive pattern;

forming a second pattern layer on the side of the circuit layer far away from the substrate, wherein the second pattern layer comprises: a fourth conductive pattern at the subpixel region;

wherein the first and second conductive patterns constitute two plates of a first capacitor, the third and fourth conductive patterns constitute two plates of a second capacitor, and the first and fourth conductive patterns are coupled.

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a preparation method of the display panel and a display device.

Background

The self-luminous display device, such as an Organic Light-Emitting Diode (OLED) display panel, has the advantages of self-luminescence, lightness, thinness, low power consumption, good color rendition, sensitive response, wide viewing angle and the like, and has a wide development prospect.

The pixel driving circuit in the OLED display panel includes a capacitor to store a driving voltage for driving the light emitting device to emit light, so that the light emitting device can continuously emit light in one frame. The OLED display panel generally forms a pixel driving circuit by laminating a plurality of pattern layers on a substrate, and in the related art, a first plate of a capacitor belongs to a source-drain pattern layer (SD layer for short) and a second plate of the capacitor belongs to a pattern layer located above the SD layer (away from the substrate), for example, an anode of a light emitting device (located at an anode layer) is multiplexed as a second plate of the capacitor in the related art. However, in order to make the capacitor in the pixel driving circuit have a larger capacitance value, a smaller distance between the first plate and the second plate is required, so that the structure greatly limits the relative position of the SD layer and the pattern layers above the SD layer, thereby reducing the flexibility of adjusting the positions of the pattern layers, which is not beneficial to improving the pattern layers.

Disclosure of Invention

In order to reduce the limitation (or dependence) of the capacitor in the pixel driving circuit on the relative position between two pattern layers (including the SD layer and the anode layer, for example), the following technical solutions are adopted in the embodiments of the present invention:

in a first aspect, a display panel is provided, the display panel having a plurality of sub-pixel regions, the display panel comprising: the circuit board comprises a substrate, a first pattern layer, a circuit layer and a second pattern layer. A first pattern layer is on the substrate, including: a first conductive pattern in a subpixel region; the circuit layer is located the first pattern layer and keeps away from the side of substrate, includes: the thin film transistor, the second conductive pattern and the third conductive pattern are positioned in the sub-pixel area, the third conductive pattern is respectively coupled with the grid electrode of the thin film transistor and the second conductive pattern, and the second conductive pattern is closer to the substrate than the third conductive pattern; the second pattern layer is positioned on one side of the circuit layer far away from the substrate and comprises: and a fourth conductive pattern in the subpixel region. Wherein the first conductive pattern and the second conductive pattern constitute two plates of a first capacitor, the third conductive pattern and the fourth conductive pattern constitute two plates of a second capacitor, and the first conductive pattern and the fourth conductive pattern are coupled.

In some embodiments, the second conductive pattern includes a first exposed portion, the first exposed portion is a portion of the second conductive pattern that is not covered by the third conductive pattern, and the first exposed portion and the fourth conductive pattern constitute two plates of the third capacitor.

In some embodiments, the first conductive pattern, the second conductive pattern, and the third conductive pattern are all capable of transmitting light.

In some embodiments, the third conductive pattern includes a second exposed portion that forms two plates of the fourth capacitor with the first conductive pattern.

In some embodiments, the circuit layer comprises: the third pattern layer, the fourth pattern layer and the fifth pattern layer. The third pattern layer includes: a second conductive pattern and an active layer, a first electrode region portion and a second electrode region portion of the thin film transistor; the fourth pattern layer is positioned on one side of the third pattern layer, which is far away from the substrate, and comprises a grid electrode of the thin film transistor; the fifth pattern layer is positioned on the side of the fourth pattern layer far away from the substrate and comprises a third conductive pattern and a fifth conductive pattern positioned in the sub-pixel area. The fifth conductive pattern is coupled to the fourth conductive pattern and the first conductive pattern, respectively.

In some embodiments, the fifth conductive pattern is coupled to the second diode portion of the thin film transistor.

In some embodiments, the display panel further comprises: the first insulating layer is positioned on one side of the circuit layer, which is far away from the substrate; the second insulating layer is located between the first insulating layer and the second pattern layer.

In some embodiments, the display panel further includes a metal pattern layer including a light blocking pattern at the subpixel region, and an orthogonal projection of the light blocking pattern on the substrate covers an orthogonal projection of an active layer of the thin film transistor on the substrate.

In some embodiments, the light blocking pattern is in contact with the first conductive pattern.

In some embodiments, the plurality of sub-pixel regions includes a first sub-pixel region and a second sub-pixel region, and the first sub-pixel region and the second sub-pixel region have different colors of light emission; the opposite area between the two polar plates of the first capacitor in the first sub-pixel area is different from the opposite area between the two polar plates of the first capacitor in the second sub-pixel area; and/or the opposite area between the two plates of the second capacitor in the first sub-pixel region is different from the opposite area of the two plates of the second capacitor in the second sub-pixel region.

In some embodiments, the shape and size of the first conductive pattern in the first subpixel region are different from those of the first conductive pattern in the second subpixel region; and/or the shape and size of the second conductive patterns in the first subpixel region are different from those in the second subpixel region.

In some embodiments, the fifth pattern layer further includes a power line coupled to the thin film transistor; the fourth pattern layer further includes auxiliary lines to which the power supply lines are coupled at a plurality of connection locations.

In the embodiment of the invention, the capacitor in the pixel driving circuit comprises a first capacitor and a second capacitor which are connected in parallel, and the two capacitors are connected in parallel, so that the total capacity of the capacitor in the pixel driving circuit is improved; meanwhile, the first capacitor plays a main role in the two capacitors, so that the arrangement of the capacitors in the pixel driving circuit is no longer completely dependent on the two pattern layers (including the SD layer and the anode layer, for example) where the second capacitor is located. Further, since the capacitor in the pixel driving circuit provided by the embodiment of the invention is formed by connecting the first capacitor and the second capacitor in parallel, compared with the pixel driving circuit with the same capacity and only one capacitor, the area of each electrode plate in the first capacitor and the second capacitor can be properly reduced, so that the area of the sub-pixel is reduced, and the resolution of the display panel is improved.

In a second aspect, a display device is provided, which includes the display panel according to any one of the above embodiments.

The beneficial effects that can be achieved by the display device provided by the embodiment of the present invention are the same as those achieved by the display panel described in any of the above embodiments, and are not described herein again.

In a third aspect, a method for manufacturing a display panel having a plurality of sub-pixel regions is provided; the preparation method comprises the following steps:

forming a substrate;

forming a first pattern layer on a substrate, the first pattern layer comprising: a first conductive pattern in a subpixel region;

forming a circuit layer on the side of the first pattern layer far away from the substrate, wherein the circuit layer comprises: the thin film transistor, the second conductive pattern and the third conductive pattern are positioned in the sub-pixel area, the third conductive pattern is respectively coupled with the grid electrode of the thin film transistor and the second conductive pattern, and the second conductive pattern is closer to the substrate than the third conductive pattern;

forming a second pattern layer on the side of the circuit layer far away from the substrate, wherein the second pattern layer comprises: a fourth conductive pattern at the subpixel region;

wherein the first conductive pattern and the second conductive pattern constitute two plates of a first capacitor, the third conductive pattern and the fourth conductive pattern constitute two plates of a second capacitor, and the first conductive pattern and the fourth conductive pattern are coupled.

The beneficial effects that can be achieved by the preparation method of the display panel provided by the embodiment of the invention are the same as those that can be achieved by the display panel described in any one of the embodiments, and are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1A is a top view of a display panel according to some embodiments of the present invention;

FIG. 1B is a cross-sectional view of a display panel according to some embodiments of the present invention;

FIG. 2 is a partial top view of another display panel according to some embodiments of the invention;

fig. 3 is a cross-sectional view taken along line a-a' in the display panel shown in fig. 2;

FIG. 4 is a cross-sectional view of a display panel of the related art;

fig. 5 is a cross-sectional view taken along line a-a' in the display panel shown in fig. 2;

fig. 6 is an equivalent circuit diagram of a display panel according to some embodiments of the invention;

FIG. 7 is a partial top view of yet another display panel according to some embodiments of the invention;

FIG. 8A is a partial top view of yet another display panel according to some embodiments of the invention;

FIG. 8B is a partial top view of yet another display panel according to some embodiments of the invention;

fig. 9 to 10 are flowcharts illustrating a method for manufacturing a display panel according to some embodiments of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

"plurality" means at least two.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" or "according to" means open and inclusive, as a process, step, calculation, or other action that is "based on" or "according to" one or more stated conditions or values may in practice be based on additional conditions or exceeding the stated values.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

The display device refers to a product having an image display function, and may be, for example: a display, a television, a billboard, a Digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a Digital camera, a camcorder, a viewfinder, a monitor, a navigator, a vehicle, a large-area wall, a home appliance, an information inquiry apparatus (e.g., a business inquiry apparatus in the departments of e-government, banking, hospital, electric power, etc., a monitor, a car rearview mirror, a fitting mirror, etc.).

In some embodiments, a display device includes a display panel configured to display an image. Illustratively, the display panel may emit light of three primary colors (e.g., including red, green, and blue), and the display panel may display a color image by adjusting the brightness of the light of the three primary colors. As another example, the display panel may emit light of three primary colors and white light; the display panel displays a color image by adjusting the brightness of the three primary color light and the white light. As yet another example, the display panel may emit only white light; the display panel displays a gray image by adjusting the brightness of the white light. At this time, the display device may further include a color filter disposed at a light emitting side of the display panel to convert the white light into light of three primary colors, thereby implementing display of a color image.

The display panel may be, for example, an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diode) display panel, a micro LED (including a miniLED or a micro LED, where the LED is a Light Emitting Diode) display panel, and the like.

In addition, the display device may further include other components, such as a power supply system that supplies power to the display panel, a circuit board connected to the display panel, and the like.

Fig. 1A illustrates a top view of a display panel provided by some embodiments of the present invention. The display panel 1 has a display area AA and a peripheral area SS disposed on at least one side of the display area AA, and fig. 1A illustrates that the peripheral area SS is disposed around the display area AA, but is not limited thereto. The display panel 1 further includes a plurality of sub-pixels P disposed in the display area AA, and the plurality of sub-pixels P in the display panel 1 may be arranged in an array as shown in fig. 1A, for example, to form a plurality of sub-pixel rows and a plurality of sub-pixel columns. Of course, the number and arrangement of the sub-pixels P are not limited to those shown in the drawings, and may be designed as needed.

Fig. 1B is a cross-sectional view of a display panel according to some embodiments of the invention. The display panel 1 may include a driving backplane 10 and a plurality of light emitting devices 20, illustratively, the driving backplane 10 includes a substrate 11 and a plurality of pixel driving circuits 12 disposed on the substrate 11, each pixel driving circuit 12 is coupled with one light emitting device 20 to constitute one sub-pixel P, and the pixel driving circuit 12 is configured to drive the light emitting device 20 coupled thereto to emit light. The arrangement of the plurality of sub-pixels P depends on the arrangement of the pixel driving circuits, and the plurality of pixel driving circuits 12 may be arranged on the substrate 11 in order, for example, the plurality of pixel driving circuits 12 are distributed on the substrate 11 in an array.

The light emitting devices 20 are main structures where the sub-pixels P realize light emission, and each light emitting device 20 may be a structure in which a plurality of thin films are stacked. Illustratively, the light emitting device 20 includes a cathode 230 and an anode 210, and a light emitting functional layer 220 positioned between the cathode 230 and the anode 210. The light emitting function Layer 220 may include, for example, a light emitting Layer 224, a Hole Transporting Layer 222(Hole Transporting Layer) between the light emitting Layer 224 and the anode 210, and an electron Transporting Layer 226 (electron Transporting Layer) between the light emitting Layer 224 and the cathode 230. Of course, in some embodiments, a Hole Injection Layer 221(Hole Injection Layer) may be further disposed between the Hole transport Layer 222 and the anode 210, and an electron Injection Layer 227 (electron Injection Layer) may be disposed between the electron transport Layer 226 and the cathode 230, as needed. An Electron Blocking Layer 223(Electron Blocking Layer) may be provided between the Hole transport Layer 222 and the light emitting Layer 224, and a Hole Blocking Layer 225(Hole Blocking Layer) may be provided between the Electron transport Layer 226 and the light emitting Layer 224.

Illustratively, the anode 210 may include, for example, a conductive layer formed of a conductive material having a high work function, which may be a transparent conductive material, including, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Zinc Oxide (GZO) zinc oxide (ZnO), indium oxide (In2O3), aluminum zinc oxide (AlZO), carbon nanotubes, and the like. The cathode 230 may include, for example, a conductive layer formed of a conductive material having high conductivity and a low work function, and the conductive material may include an alloy such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl) or a simple metal such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag). The material of the light-emitting layer 224 may be selected according to the color of light emitted therefrom. For example, the material of the light emitting layer 224 includes a fluorescent light emitting material or a phosphorescent light emitting material. For another example, the light-emitting layer 224 may be a doped system in which a host light-emitting material is mixed with a dopant material to obtain a usable light-emitting material. For example, as the host light-emitting material, a metal compound material, a derivative of anthracene, an aromatic diamine compound, a triphenylamine compound, an aromatic triamine compound, a biphenyldiamine derivative, a triarylamine polymer, or the like can be used.

Fig. 2 is a partial top view of a display panel according to some embodiments of the present invention, and fig. 3 is a cross-sectional view taken along line a-a' of the display panel shown in fig. 2. Referring to fig. 2 and 3, the display panel 1 has a plurality of sub-pixel regions PA, wherein one sub-pixel region PA refers to a space occupied by one sub-pixel P in the display panel 1. Illustratively, the display panel 1 includes a plurality of color sub-pixels P, and the light emission colors of the different color sub-pixels are different. For example, the light emission colors of the sub-pixels in the display panel 1 are three primary colors of light, i.e., red (R), green (G), blue (B), and white (W), the corresponding sub-pixels are red sub-pixel Pr, green sub-pixel Pg, blue sub-pixel Pb, and white sub-pixel Pw, and the sub-pixel regions corresponding to the sub-pixels Pr, Pg, Pb, and Pw of the four colors are red sub-pixel region PAr, green sub-pixel region PAg, blue sub-pixel region PAb, and white sub-pixel region PAw, respectively.

Referring to fig. 2 and 3, the display panel 1 includes a substrate 11, a circuit layer 120, a first pattern layer 121, and a second pattern layer 122. The first pattern layer 121 is on the substrate 11, and includes: the first conductive pattern C1 located at a subpixel region PAr; the circuit layer 120 is located on a side of the first pattern layer 121 away from the substrate 11, and includes: a thin film transistor TFT, a second conductive pattern C2, and a third conductive pattern C3 in the sub-pixel region PA, the third conductive pattern C3 being coupled to the gate electrode G of the thin film transistor TFT and the second conductive pattern C2, respectively, and the second conductive pattern C2 being closer to the substrate 11 than the third conductive pattern C3; the second pattern layer 122 is located on a side of the circuit layer 120 away from the substrate 11, and the second pattern layer 122 includes a fourth conductive pattern C4 located in the subpixel region PAr.

The substrate 11 is configured to carry a plurality of film layers of the display panel 1, and exemplarily, the substrate 11 may be a rigid substrate, and a material of the rigid substrate may be, for example, glass or Polymethyl methacrylate (PMMA). Further illustratively, the substrate 11 may be a flexible substrate, and the material of the flexible substrate may be, for example, Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), Polyimide (PI), or the like.

The circuit layer 120 is a general term for several film layers in the display panel 1, and exemplarily, the circuit layer 120 includes a plurality of film layers, the plurality of film layers in the circuit layer 120 includes a plurality of functional patterns, and the functional patterns are coupled to each other to form a circuit. For example, a part of the functional pattern in the circuit layer 120 may form a thin film transistor TFT. The functional pattern in the circuit layer 120 may be a conductive pattern or a semiconductor pattern, etc.

The circuit layer 120 includes a second conductive pattern C2 and a third conductive pattern C3, and the distances from the second conductive pattern C2 and the third conductive pattern C3 to the substrate 11 are different, and illustratively, the second conductive pattern C2 and the third conductive pattern C3 are respectively located at different film layers, for example, the film layer where the second conductive pattern C2 is located is closer to the substrate 11 than the film layer where the third conductive pattern C3 is located, so that the distance from the second conductive pattern C2 to the substrate 11 is smaller than the distance from the third conductive pattern C3 to the substrate 11.

The first and second conductive patterns C1 and C2 constitute two plates of a first capacitor Cst1, the third and fourth conductive patterns C3 and C4 constitute two plates of a second capacitor Cst2, and the first and fourth conductive patterns C1 and C1 are coupled. Illustratively, the first capacitor Cst1 includes opposite portions C11 and C21 between the first conductive pattern C1 and the second conductive pattern C2, for example, a C21 portion in the second conductive pattern C2 as a first plate of the first capacitor Cst1, and a C11 portion in the first conductive pattern C1 as a second plate of the first capacitor Cst1, wherein the opposite portions refer to portions in the first conductive pattern C1 and the second conductive pattern C2 corresponding to an overlapping portion between a forward projection of the first conductive pattern C1 on the substrate 11 and a forward projection of the second conductive pattern C2 on the substrate 11. Similarly, the second capacitor Cst2 includes facing portions C32 and C42 between the third conductive pattern C3 and the fourth conductive pattern C4, for example, a portion of C32 in the third conductive pattern C3 as a first plate of the second capacitor Cst2, and a portion of C42 in the fourth conductive pattern C4 as a second plate of the second capacitor Cst 2. In addition, at least one insulating layer may be included between both plates of the first capacitor Cst1 and the second capacitor Cst 2.

The second conductive pattern C2 is coupled to the third conductive pattern C3, and the first conductive pattern C1 is coupled to the fourth conductive pattern C4 such that the first plate of the first capacitor Cst1 is coupled to the first plate of the second capacitor Cst2, and the second plate of the first capacitor Cst1 is coupled to the second plate of the second capacitor Cst2, then the first capacitor Cst1 and the second capacitor Cst2 form a parallel capacitance, thereby increasing the total capacitance of the capacitors located in the subpixel region PAr.

In the display panel 1, the facing area of both plates in the first capacitor Cst1 may be controlled to be larger than the facing area of both plates in the second capacitor Cst2, so that the first capacitor Cst1 plays a major role in the subpixel Pr. In the case where the first plate (a part of the third conductive pattern C3) in the second capacitor Cst2 is positioned between the SD layer and the substrate 11, the first capacitor Cst1 is positioned between the SD layer and the substrate 11, and then the first capacitor Cst1, which plays a main role in the subpixel P, may be closer to the substrate 11 than the SD layer, i.e., both plates in the first capacitor Cst1 are positioned at a side of the SD layer close to the substrate 11, so that the dependency of the total capacity of the capacitors positioned in the subpixel region PAr on the SD layer and the above film layers may be reduced accordingly.

In addition, in some embodiments, the fourth conductive pattern C4 may multiplex the anode of the light emitting device, at least one organic insulating layer may be included between the SD layer and the anode of the light emitting device, the thickness of the organic insulating layer is greater than that of the inorganic insulating layer, and only one inorganic insulating layer may be included between the first conductive pattern C1 and the second conductive pattern C2, such that the distance between the two plates of the first capacitor Cst1 is smaller than that of the second capacitor Cst2, further increasing the capacity of the first capacitor Cst 1; meanwhile, other components may be accommodated between the two plates of the second capacitor Cst2, for example, when the display panel 1 includes the color film pattern CF, the color film pattern CF may be disposed between the two plates of the second capacitor Cst2, so that the space utilization of the display panel 1 is increased.

In the related art, referring to fig. 4, the display panel 1 'generally uses facing portions between the conductive pattern C3' in the SD layer and the anode 210 'of the light emitting device as a first plate Cst 1' and a second plate Cst2 'of a capacitor, respectively, and in order to reduce a distance between the first plate Cst 1' and the second plate Cst2 'to increase a capacity of the capacitor, a via hole V' needs to be formed on an organic insulating layer therebetween. The orthographic projection of the via V 'on the substrate 11' needs to overlap as much as possible with the orthographic projection of the conductive pattern C3 'in the SD layer on the substrate 11' to ensure sufficient facing area between the two plates of the capacitor. Therefore, in the related art, the area of the via hole V' formed on the organic insulating layer is generally large.

In an embodiment of the present invention, referring to fig. 3, since the first capacitor Cst1 may not depend on the SD layer and the above film layers, the first via V1 on the organic insulating layer between the fourth conductive pattern C4 and the third conductive pattern C3 may not need to occupy a large space, for example, the orthographic projection of the first via V1 on the substrate 11 may be much smaller than the orthographic projection of the third conductive pattern C3 on the substrate 11, for example, the first via V1 only needs to satisfy a space requirement for coupling the fourth conductive pattern C4 with the lower pattern (e.g., the first conductive pattern C1).

In some embodiments, referring to fig. 5, the second conductive pattern C2 includes a first exposed portion C21, the first exposed portion C21 is a portion of the second conductive pattern C2 that is not shielded by the third conductive pattern C3, that is, an orthogonal projection of the first exposed portion C21 on the substrate 11 does not overlap an orthogonal projection of the third conductive pattern C3 on the substrate 11, and the first exposed portion C21 and the fourth conductive pattern C4 constitute two plates of the third capacitor Cst 3.

Illustratively, an orthogonal projection of the first exposed portion C21 on the substrate 11 and an orthogonal projection of the fourth conductive pattern C4 on the substrate 11 have overlapping portions, and the third capacitor Cst3 includes opposite portions C213 and C43 between the first exposed portion C21 and the fourth conductive pattern C4, for example, a portion of C213 in the first exposed portion C21 serves as a first plate of the third capacitor Cst3, and a portion of C43 in the fourth conductive pattern C4 serves as a second plate of the third capacitor Cst 3. In the display panel 1, since the first exposed portion C21 is a portion of the second conductive pattern C2 and C43 is a portion of the fourth conductive pattern C4, the first plate of the third capacitor Cst3 is coupled to the first plate of the first capacitor Cst1 and the second plate of the third capacitor Cst3 is coupled to the second plate of the second capacitor Cst2, so that the third capacitor Cst3 is further in a parallel relationship with the first capacitor Cst1 and the second capacitor Cst2, thereby further increasing the total capacitance of the capacitors located in the subpixel region PAr.

In some embodiments, the first, second, and third conductive patterns C1, C2, and C3 are all capable of transmitting light. Illustratively, the first, second, and third conductive patterns C1, C2, and C3 are each capable of transmitting light emitted from the light emitting device, for example, at least one of the first, second, and third conductive patterns C1, C2, and C3 is a transparent electrode.

In the related art, referring to fig. 4, in the case where the first plate Cst1 '(conductive pattern C3') of the capacitor is formed of a non-light transmissive material, for example, the conductive pattern C3 'is located at an SD layer in the display panel 1', the SD layer is generally formed using a metal material, and for the bottom emission type display panel 1 ', the facing portion of the anode 210' of the light emitting device and the conductive pattern C3 '(i.e., the second plate Cst 2') cannot be used for light emission, and the larger the area of the facing portion of the anode 210 'of the light emitting device and the conductive pattern C3' is, the smaller the area for light emission in the subpixel is, and thus, in order to secure a sufficient capacity of the capacitor, the aperture ratio of the subpixel must be sacrificed. In the embodiment of the present invention, referring to fig. 3, in the case where the third conductive pattern C3 is formed of a non-light-transmissive material, since the capacitor in the display panel is no longer completely dependent on the SD layer and the film layers above it, the total capacity of the capacitor is also not dependent on the area of the third conductive pattern C3. Therefore, the area of the third conductive pattern C3 can be appropriately reduced to increase the aperture ratio of the subpixel Pr.

In some embodiments, referring to fig. 5, the third conductive pattern C3 includes a second exposed portion C32, and the second exposed portion C32 and the first conductive pattern C1 constitute two plates of the fourth capacitor Cst 4. The second exposed portion C32 is a portion of the third conductive pattern C3 that is not covered by other patterns and directly faces the first conductive pattern C1. Directly opposite means that there is no conductive material between them in the thickness direction of the display panel. Exemplarily, the second exposed portion C32 is a portion of the third conductive pattern C3 that is not shielded by the second conductive pattern C2 and the driving transistor TFT.

Illustratively, an orthogonal projection of the second exposed portion C32 on the substrate 11 and an orthogonal projection of the first conductive pattern C1 on the substrate 11 have overlapping portions, and the fourth capacitor Cst4 includes opposite portions C324 and C14 between the second exposed portion C32 and the first conductive pattern C1, for example, a portion of C324 in the second exposed portion C32 serves as a first plate of the fourth capacitor Cst4, and a portion of C14 in the first conductive pattern C1 serves as a second plate of the fourth capacitor Cst 4. In the display panel 1, since the second exposed portion C32 is a portion of the third conductive pattern C3 and C14 is a portion of the first conductive pattern C1, the first plate of the fourth capacitor Cst4 is coupled to the first plate of the second capacitor Cst2, and the second plate of the fourth capacitor Cst4 is coupled to the second plate of the first capacitor Cst1, so that the fourth capacitor Cst4 is further in parallel relationship with the first capacitor Cst1 and the second capacitor Cst2, further increasing the total capacitance of the capacitors in the subpixel region PAr.

In some embodiments, referring to fig. 3 and 5, the circuit layer 120 includes: a third pattern layer 123, a fourth pattern layer 124, and a fifth pattern layer 125. The third pattern layer 123 includes: the second conductive pattern C2, and the active layer a, the first and second electrode portions S1 and S2 of the thin film transistor TFT, wherein the first electrode portion S1 may be one of a source region portion and a drain region portion of the thin film transistor TFT, and the second electrode portion S2 is the other of the source region portion and the drain region portion of the thin film transistor TFT. The fourth pattern layer 124 is located on a side of the third pattern layer 123 away from the substrate 11, and the fourth pattern layer 124 includes a gate electrode G of the thin film transistor TFT. The fifth pattern layer 125 is positioned on a side of the fourth pattern layer 124 away from the substrate 11, and the fifth pattern layer 125 includes a third conductive pattern C3 and a fifth conductive pattern C5 positioned in the subpixel region PAr. The fifth conductive pattern C5 is coupled to the fourth conductive pattern C4 and the first conductive pattern C1, respectively.

Illustratively, the third pattern layer 123 may be an active layer in the display panel 1, the fourth pattern layer 124 may be a Gate layer in the display panel 1, and the fifth pattern layer 125 may be an SD layer in the display panel 1.

Referring to fig. 6, fig. 6 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present invention. The pixel driving circuit is of a 3T1C structure, and comprises: one driving transistor DT, two switching transistors T1, T2, and one capacitor Cst, wherein the capacitor Cst is connected in parallel by a first capacitor Cst1 and a second capacitor Cst 2. The driving process of the pixel driving circuit comprises the following steps: a data writing phase, a holding phase and a light emitting phase. In the data writing phase, the switching transistors T1, T2 are turned on in response to an active signal supplied from the scan signal terminal GL to write a data signal (data voltage) supplied from the data signal terminal DA to one of the gate electrode of the driving transistor DT and the plate of the capacitor, and to write a sensing signal (initial voltage) supplied from the sensing signal terminal Se to the anode electrode of the light emitting device 20 and the other plate of the capacitor Cst; in the holding phase, the switching transistors T1, T2 are turned off in response to the inactive signal provided by the scan signal terminal GL, the driving transistor DT is continuously turned on by the holding action of the capacitor Cst, and the gate voltage is gradually raised by the "bootstrap" action of the capacitor Cst, so that the driving transistor DT is turned on more and more sufficiently until the current flowing through the driving transistor DT increases to the light emitting current of the OLED device, entering the light emitting phase; in the light emitting stage, the light emitting device 20 continuously emits light by the capacitor Cst.

Referring to fig. 8A, the scanning signal terminal GL, the data signal terminal DA, and the sensing signal terminal Se may be provided by the scanning signal line GL, the data signal line DA, and the sensing signal line Se, respectively, in the display panel provided in the embodiment of the present invention.

In some embodiments, the fifth conductive pattern C5 is coupled with the second electrode portion S2 of the thin film transistor TFT. Exemplarily, in the case where the pixel driving circuit in the display panel 1 is of a 3T1C structure, referring to fig. 3, 5, and 6, the thin film transistor TFT may be the driving transistor DT in the pixel driving circuit shown in fig. 6. Wherein the fourth conductive pattern C4 is multiplexed as an anode of the light emitting device 20. The third conductive pattern C3 is coupled with the second conductive pattern C2 to form one plate of the capacitor Cst, the plate being coupled with a gate electrode of the thin film transistor TFT (driving transistor), and the first conductive pattern C1 and the second conductive pattern C2 are coupled with the fifth conductive pattern C5 to form the other plate of the capacitor Cst, the plate being further coupled with the second electrode region portion S2 of the thin film transistor TFT through the fifth conductive pattern C5.

In some embodiments, the material of the active layer a of the thin film transistor TFT is an oxide semiconductor or polysilicon; the material of the second conductive pattern C2 and the first and second electrode portions S1 and S2 of the thin film transistor TFT is made of an oxide semiconductor or polysilicon through electrical conduction. Among them, the oxide semiconductor may include Indium Tin Oxide (ITO), Indium Gallium Zinc Oxide (IGZO), and the like. Illustratively, the third pattern layer 123 in the display panel 1 is an active pattern layer, and the step of forming the third pattern layer 123 includes: first, a semiconductor active pattern layer is formed, wherein the semiconductor active pattern layer includes a second semiconductor pattern formed of an oxide semiconductor or polysilicon, an active layer of the thin film transistor TFT, a first semiconductor region and a second semiconductor region of the thin film transistor TFT, and then the second semiconductor pattern, the first semiconductor region and the second semiconductor region of the thin film transistor TFT are conductorzed to obtain a second conductive pattern C2, a first pole region portion S1 and a second pole region portion S2 of the thin film transistor TFT.

In some embodiments, referring to fig. 3 and 5, the display panel 1 further includes a first insulating layer 126 and a second insulating layer 127, the first insulating layer 126 is located on a side of the circuit layer 120 away from the substrate 11, and the second insulating layer 127 is located between the first insulating layer 126 and the second pattern layer 122. Illustratively, the first insulating layer 126 is an inorganic insulating layer, and the second insulating layer 127 is an organic insulating layer, wherein the first insulating layer 126 is dense and is formed on the circuit layer 120 to protect the circuit layer 120, for example, the first insulating layer 126 covers the third conductive pattern C3 and the fifth conductive pattern C5 in the fifth pattern layer 125 to prevent corrosion thereof by moisture, oxygen, and the like, and the second insulating layer 127 can be flat, for example, the second insulating layer 127 can provide a more flat carrying surface for the fourth conductive pattern C4.

In some embodiments, the display panel 1 further includes a metal pattern layer 128, the metal pattern layer 128 includes a light blocking pattern 1281 located at the subpixel region PAr, and an orthogonal projection of the light blocking pattern 1281 on the substrate 11 covers an orthogonal projection of the active layer a of the thin film transistor TFT on the substrate 11. Illustratively, the light shielding pattern 1281 is closer to the substrate 11 than the active layer a of the thin film transistor TFT, for example, the light shielding pattern 1281 is directly formed on the substrate 11; for another example, the light blocking pattern 1281 is positioned between the first pattern layer 121 and the active layer a of the thin film transistor TFT. The metal pattern layer 128 may be formed of a metal simple substance or a metal alloy material, and the light blocking pattern 1281 is used to block light from irradiating the active layer of the thin film transistor TFT.

In some embodiments, the light blocking pattern 1281 is in contact with the first conductive pattern C1. Illustratively, the first conductive pattern C1 partially overlaps the light blocking pattern 1281.

It should be noted that the above embodiments are described by taking the red subpixel Pr (corresponding to the red subpixel region PAr) as an example, but the features of the display panel described in any of the above embodiments are applicable to any subpixel in the display panel without limitation.

Fig. 7 is a partial top view of a display panel according to some embodiments of the present invention, and in some embodiments, referring to fig. 7, a plurality of sub-pixel regions in the display panel 1 includes: the first subpixel region and the second subpixel region have different light emitting colors. For example, the first subpixel region and the second subpixel region are subpixel regions corresponding to subpixels of different colors, for example, the first subpixel region and the second subpixel region are any two of a red subpixel region PAr, a green subpixel region PAg, a blue subpixel region PAb, and a white subpixel region PAw, respectively, for example, the first subpixel region is the red subpixel region PAr, and the second subpixel region is the green subpixel region PAg, or the first subpixel region is the red subpixel region PAr, and the second subpixel region is the blue subpixel region PAb, or the first subpixel region is the blue subpixel region PAb, and the second subpixel region is the green subpixel region PAg.

A facing area between both plates of the first capacitor Cst1 in the first subpixel region is different from a facing area between both plates of the first capacitor Cst1 in the second subpixel region. Illustratively, the facing area between the two plates of the first capacitor Cst1 in each subpixel region is set according to the color of light extraction of the subpixel region, and the facing area between the two plates of the first capacitor Cst1 in subpixel regions of different color of light extraction is different. For example, the right facing areas between the two plates of the first capacitor Cst1 in the red subpixel region PAr, the green subpixel region PAg, the blue subpixel region PAb, and the white subpixel region PAw in the display panel 1 are all different. Since the sub-pixels of different colors have different light intensities and different facing areas are matched for the different sub-pixels, the first capacitor Cst1 in the sub-pixels of different colors can have a capacity matched with the sub-pixel, and thus the light intensities of the sub-pixels of different colors are more uniform.

Similarly, referring to fig. 8A and 8B, a facing area between both plates of the second capacitor Cst2 in the first subpixel region is different from a facing area of both plates of the second capacitor Cst2 in the second subpixel region. Embodiments and advantageous effects thereof are similar to those of the first capacitor Cst1 described above, and thus are not described in detail.

In some embodiments, referring to fig. 7, the shape and size of the first conductive pattern C1 located in the first subpixel region are not the same as the shape and size of the first conductive pattern C1 located in the second subpixel region. Since the first conductive patterns C1 in the first and second subpixel regions are not the same in shape and size, the facing areas between the two plates of the first capacitor Cst1 in the first and second subpixel regions are different. Similarly, the shape and size of the second conductive pattern C2 located in the first subpixel region are different from those of the second conductive pattern C2 located in the second subpixel region.

In some embodiments, referring to fig. 8A and 8B, the fifth pattern layer 125 further includes a power line VDD coupled to the first electrode portion S1 of the thin film transistor TFT. The fourth pattern layer 124 further includes an auxiliary line GA to which the power supply line VDD is coupled at a plurality of connection locations. The connection position is a position where the second via V2 between the power line VDD and the auxiliary line GA is located, one via V2 corresponds to one connection position, and the power line VDD and the auxiliary line GA are coupled through a plurality of second vias V2. Because the power line VDD and the auxiliary line GA are respectively positioned at different layers, the power line VDD and the auxiliary line GA are connected in parallel, the voltage drop on the power line VDD is reduced, and the accuracy of voltage transmission is improved.

In some embodiments, the data lines DA, the sensing signal lines Se are also coupled with the auxiliary lines GA at a plurality of connection positions to improve the accuracy of data signal transmission.

In some embodiments, the power supply line VDD may also be coupled to the first electrode region portion S1 of the thin film transistor TFT through the via pattern 1282. Illustratively, one pixel in the display panel 1 includes four sub-pixels, for example, one pixel includes one red sub-pixel Pr, one green sub-pixel Pg, one blue sub-pixel Pb, and one white sub-pixel Pw, and two sub-pixels in the one pixel, for example, the white sub-pixel Pw and the blue sub-pixel Pb, may be coupled to the corresponding power line VDD through the via pattern 1282, so that the two sub-pixels may share the power line VDD, thereby saving the layout area of the display panel 1. Exemplarily, the via pattern 1282 may be located at the metal pattern layer 128.

The embodiment of the invention provides a preparation method of a display panel. The display panel provided in any of the above embodiments has a plurality of subpixel regions.

Referring to fig. 9 and 10, the method of manufacturing a display panel includes:

st 1: forming a substrate 11;

st 2: forming a first pattern layer 121 on the substrate 11, the first pattern layer 121 including: a first conductive pattern C1 located at a subpixel region;

st 3: forming a circuit layer 120 on a side of the first pattern layer 121 away from the substrate 11, the circuit layer 120 including: the thin film transistor TFT, the second conductive pattern C2, and the third conductive pattern C3 located in the subpixel region, the third conductive pattern C3 being coupled to the gate G of the thin film transistor TFT and the second conductive pattern C2, respectively, and the second conductive pattern C2 being closer to the substrate 11 than the third conductive pattern C3;

st 4: forming a second pattern layer 122 on a side of the circuit layer 120 away from the substrate 11, the second pattern layer 122 including: and a fourth conductive pattern C4 positioned at the subpixel region.

Wherein the first conductive pattern C1 and the second conductive pattern C2 constitute two plates of the first capacitor Cst1, the third conductive pattern C3 and the fourth conductive pattern C4 constitute two plates of the second capacitor Cst2, and the first conductive pattern C1 and the fourth conductive pattern C4 are coupled.

In some embodiments, the method for manufacturing a display panel further includes:

st11 before forming the first pattern layer 121, a metal pattern layer 128 is formed on the substrate 11, the metal pattern layer 128 including a light blocking pattern 1281 at the subpixel region as described above.

In some embodiments, the step of forming the circuit layer 120 on the side of the first pattern layer 121 away from the substrate 11 further includes:

st 301: forming a third pattern layer 123 on a side of the first pattern layer 121 away from the substrate 11, wherein the third pattern layer 123 includes: the second conductive pattern C2, and the active layer a, the first electrode portion S1, and the second electrode portion S2 of the thin film transistor TFT.

St 302: a fourth pattern layer 124 is formed on a side of the third pattern layer 123 away from the substrate 11, wherein the fourth pattern layer 124 includes a gate electrode G of the thin film transistor TFT.

St 303: a fifth pattern layer 125 is formed on a side of the fourth pattern layer 124 away from the substrate 11, wherein the fifth pattern layer 125 includes a third conductive pattern C3 and a fifth conductive pattern C5 located at the subpixel region. The fifth conductive pattern C5 is coupled to the fourth conductive pattern C4 and the first conductive pattern C1, respectively.

In addition, the preparation method of the display panel further comprises the following steps: an insulating layer is formed between adjacent two pattern layers, for example, a first insulating layer 126 and a second insulating layer 127 are formed between the fifth pattern layer 125 and the second pattern layer 122.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.